2020-04-02 00:33:15 +00:00
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/*-
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2023-05-10 15:40:58 +00:00
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* SPDX-License-Identifier: BSD-2-Clause
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2020-04-02 00:33:15 +00:00
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*
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* Copyright (c) 2019 Axiado Corporation
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* All rights reserved.
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*
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* This software was developed in part by Nick O'Brien and Rishul Naik
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* for Axiado Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/clock.h>
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#include <sys/eventhandler.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <sys/sdt.h>
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#include <sys/time.h>
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#include <sys/timespec.h>
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#include <sys/timex.h>
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#include <sys/watchdog.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <machine/bus.h>
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#include <machine/clock.h>
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#include <machine/intr.h>
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#include <machine/resource.h>
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#include "clock_if.h"
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#define FEAON_AON_WDT_BASE 0x0
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#define FEAON_AON_RTC_BASE 0x40
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#define FEAON_AON_CLKCFG_BASE 0x70
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#define FEAON_AON_BACKUP_BASE 0x80
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#define FEAON_AON_PMU_BASE 0x100
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/* Watchdog specific */
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#define FEAON_WDT_CFG 0x0
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#define FEAON_WDT_COUNT 0x8
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#define FEAON_WDT_DOGS 0x10
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#define FEAON_WDT_FEED 0x18
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#define FEAON_WDT_KEY 0x1C
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#define FEAON_WDT_CMP 0x20
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#define FEAON_WDT_CFG_SCALE_MASK 0xF
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#define FEAON_WDT_CFG_RST_EN (1 << 8)
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#define FEAON_WDT_CFG_ZERO_CMP (1 << 9)
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#define FEAON_WDT_CFG_EN_ALWAYS (1 << 12)
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#define FEAON_WDT_CFG_EN_CORE_AWAKE (1 << 13)
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#define FEAON_WDT_CFG_IP (1 << 28)
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#define FEAON_WDT_CMP_MASK 0xFFFF
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#define FEAON_WDT_FEED_FOOD 0xD09F00D
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#define FEAON_WDT_KEY_UNLOCK 0x51F15E
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#define FEAON_WDT_TIMEBASE_FREQ 31250
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#define FEAON_WDT_TIMEBASE_RATIO (NANOSECOND / FEAON_WDT_TIMEBASE_FREQ)
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/* Real-time clock specific */
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#define FEAON_RTC_CFG 0x40
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#define FEAON_RTC_LO 0x48
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#define FEAON_RTC_HI 0x4C
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#define FEAON_RTC_CMP 0x60
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#define FEAON_RTC_CFG_SCALE_MASK 0xF
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#define FEAON_RTC_CFG_EN (1 << 12)
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#define FEAON_RTC_CFG_IP (1 << 28)
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#define FEAON_RTC_HI_MASK 0xFFFF
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#define FEAON_RTC_TIMEBASE_FREQ 31250LL
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#define FEAON_LOCK(sc) mtx_lock(&(sc)->mtx)
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#define FEAON_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
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#define FEAON_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
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#define FEAON_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED)
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#define FEAON_READ_4(sc, reg) bus_read_4(sc->reg_res, reg)
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#define FEAON_WRITE_4(sc, reg, val) bus_write_4(sc->reg_res, reg, val)
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#define FEAON_WDT_WRITE_4(sc, reg, val) do { \
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FEAON_WRITE_4(sc, (FEAON_WDT_KEY), (FEAON_WDT_KEY_UNLOCK)); \
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FEAON_WRITE_4(sc, reg, val); \
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} while (0)
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struct feaon_softc {
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device_t dev;
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struct mtx mtx;
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/* Resources */
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int reg_rid;
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struct resource *reg_res;
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/* WDT */
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eventhandler_tag ev_tag;
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};
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static void
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feaon_wdt_event(void *arg, unsigned int cmd, int *err)
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{
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struct feaon_softc *sc;
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uint32_t scale, val;
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uint64_t time;
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sc = (struct feaon_softc *)arg;
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FEAON_LOCK(sc);
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/* First feed WDT */
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FEAON_WDT_WRITE_4(sc, FEAON_WDT_FEED, FEAON_WDT_FEED_FOOD);
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if ((cmd & WD_INTERVAL) == WD_TO_NEVER) {
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/* Disable WDT */
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val = FEAON_READ_4(sc, FEAON_WDT_CFG);
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val &= ~(FEAON_WDT_CFG_EN_ALWAYS | FEAON_WDT_CFG_EN_CORE_AWAKE);
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FEAON_WDT_WRITE_4(sc, FEAON_WDT_CFG, val);
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goto exit;
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}
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/* Calculate time in WDT frequency */
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time = 1LL << (cmd & WD_INTERVAL);
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time /= FEAON_WDT_TIMEBASE_RATIO;
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/* Fit time in CMP register with scale */
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scale = 0;
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while (time > FEAON_WDT_CMP_MASK) {
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time >>= 1;
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scale++;
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}
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if (time > FEAON_WDT_CMP_MASK || scale > FEAON_WDT_CFG_SCALE_MASK) {
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device_printf(sc->dev, "Time interval too large for WDT\n");
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*err = EINVAL;
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goto exit;
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}
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/* Program WDT */
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val = FEAON_READ_4(sc, FEAON_WDT_CFG);
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val &= ~FEAON_WDT_CFG_SCALE_MASK;
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val |= scale | FEAON_WDT_CFG_RST_EN | FEAON_WDT_CFG_EN_ALWAYS |
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FEAON_WDT_CFG_ZERO_CMP;
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FEAON_WDT_WRITE_4(sc, FEAON_WDT_CMP, (uint32_t)time);
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FEAON_WDT_WRITE_4(sc, FEAON_WDT_CFG, val);
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exit:
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FEAON_UNLOCK(sc);
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}
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static int
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feaon_rtc_settime(device_t dev, struct timespec *ts)
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{
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struct feaon_softc *sc;
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uint64_t time;
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uint32_t cfg;
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uint8_t scale;
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scale = 0;
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sc = device_get_softc(dev);
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FEAON_LOCK(sc);
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clock_dbgprint_ts(dev, CLOCK_DBG_WRITE, ts);
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time = ts->tv_sec * FEAON_RTC_TIMEBASE_FREQ;
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/* Find an appropriate scale */
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while (time >= 0xFFFFFFFFFFFFLL) {
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scale++;
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time >>= 1;
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}
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if (scale > FEAON_RTC_CFG_SCALE_MASK) {
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device_printf(sc->dev, "Time value too large for RTC\n");
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FEAON_UNLOCK(sc);
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return (1);
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}
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cfg = FEAON_READ_4(sc, FEAON_RTC_CFG) & ~FEAON_RTC_CFG_SCALE_MASK;
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cfg |= scale;
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FEAON_WRITE_4(sc, FEAON_RTC_CFG, cfg);
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FEAON_WRITE_4(sc, FEAON_RTC_LO, (uint32_t)time);
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FEAON_WRITE_4(sc, FEAON_RTC_HI, (time >> 32) & FEAON_RTC_HI_MASK);
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FEAON_UNLOCK(sc);
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return (0);
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}
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static int
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feaon_rtc_gettime(device_t dev, struct timespec *ts)
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{
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struct feaon_softc *sc;
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uint64_t time;
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uint8_t scale;
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sc = device_get_softc(dev);
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FEAON_LOCK(sc);
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time = FEAON_READ_4(sc, FEAON_RTC_LO);
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time |= ((uint64_t)FEAON_READ_4(sc, FEAON_RTC_HI)) << 32;
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scale = FEAON_READ_4(sc, FEAON_RTC_CFG) & FEAON_RTC_CFG_SCALE_MASK;
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time <<= scale;
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ts->tv_sec = time / FEAON_RTC_TIMEBASE_FREQ;
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ts->tv_nsec = (time % FEAON_RTC_TIMEBASE_FREQ) *
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(NANOSECOND / FEAON_RTC_TIMEBASE_FREQ);
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clock_dbgprint_ts(dev, CLOCK_DBG_READ, ts);
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FEAON_UNLOCK(sc);
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return (0);
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}
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static int
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feaon_attach(device_t dev)
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{
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struct feaon_softc *sc;
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int err;
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sc = device_get_softc(dev);
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sc->dev = dev;
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/* Mutex setup */
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mtx_init(&sc->mtx, device_get_nameunit(sc->dev), NULL, MTX_DEF);
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/* Resource setup */
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sc->reg_rid = 0;
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if ((sc->reg_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
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&sc->reg_rid, RF_ACTIVE)) == NULL) {
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device_printf(dev, "Error allocating memory resource.\n");
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err = ENXIO;
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goto error;
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}
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/* Enable RTC */
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clock_register(dev, 1000000); /* 1 sec resolution */
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FEAON_LOCK(sc);
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FEAON_WRITE_4(sc, FEAON_RTC_CFG, FEAON_RTC_CFG_EN);
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FEAON_UNLOCK(sc);
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/* Register WDT */
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sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, feaon_wdt_event, sc, 0);
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return (0);
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error:
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bus_release_resource(dev, SYS_RES_MEMORY, sc->reg_rid, sc->reg_res);
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mtx_destroy(&sc->mtx);
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return (err);
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}
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static int
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feaon_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "sifive,aon0"))
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return (ENXIO);
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device_set_desc(dev, "SiFive FE310 Always-On Controller");
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return (BUS_PROBE_DEFAULT);
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}
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static device_method_t feaon_methods[] = {
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DEVMETHOD(device_probe, feaon_probe),
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DEVMETHOD(device_attach, feaon_attach),
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/* RTC */
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DEVMETHOD(clock_gettime, feaon_rtc_gettime),
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DEVMETHOD(clock_settime, feaon_rtc_settime),
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DEVMETHOD_END
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};
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static driver_t feaon_driver = {
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"fe310aon",
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feaon_methods,
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sizeof(struct feaon_softc)
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};
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2022-05-10 17:21:38 +00:00
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DRIVER_MODULE(fe310aon, simplebus, feaon_driver, 0, 0);
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