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freebsd-src/sys/powerpc/include/openpicvar.h

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/* -> /*- for license, minor formatting changes
2005-01-07 02:29:27 +00:00
/*-
spdx: The BSD-2-Clause-FreeBSD identifier is obsolete, drop -FreeBSD The SPDX folks have obsoleted the BSD-2-Clause-FreeBSD identifier. Catch up to that fact and revert to their recommended match of BSD-2-Clause. Discussed with: pfg MFC After: 3 days Sponsored by: Netflix
2023-05-10 15:40:58 +00:00
* SPDX-License-Identifier: BSD-2-Clause
sys/powerpc: further adoption of SPDX licensing ID tags. Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
2017-11-27 15:09:59 +00:00
*
Driver for OpenPIC compatible interrupt controllers. It's fairly PowerMac specific at the moment, but that should be fixable.
2002-07-09 11:26:10 +00:00
* Copyright (C) 2002 Benno Rice.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _POWERPC_OPENPICVAR_H_
#define _POWERPC_OPENPICVAR_H_
Make the OpenPic driver bus-independent, with attachments for the MacIO chip and PSIM's IOBus. Bus-specific drivers should use the identify method to attach themselves to nexus so interrupt can be allocated before the h/w is probed. The 'early attach' routine in openpic is used for this stage of boot. When h/w is probed, the openpic can be attached properly. It will enable interrupts allocated prior to this.
2004-01-13 11:24:36 +00:00
#define OPENPIC_DEVSTR "OpenPIC Interrupt Controller"
#define OPENPIC_IRQMAX 256 /* h/w allows more */
powerpc: Bind IRQs to only one interrupt on QorIQ SoCs The QorIQ SoCs don't actually support multicast interrupts, and the references state explicitly that multicast is undefined behavior. Avoid the undefined behavior by binding to only a single CPU, using a quirk to determine if this is necessary. MFC after: 3 weeks
2019-02-06 03:52:14 +00:00
#define OPENPIC_QUIRK_SINGLE_BIND 1 /* Bind interrupts to only 1 CPU */
powerpc/mpc85xx: Add MSI support for Freescale PowerPC SoCs Freescale SoCs use a set of IRQs at the high end of the OpenPIC IRQ list, not counted in the NIRQs of the Feature reporting register. Some SoCs include a MSI inbound window in the PCIe controller configuration registers as well, but some don't. Currently, this only handles the SoCs *with* the MSI window. There are 256 MSIs per MSI bank (32 per MSI IRQ, 8 IRQs per MSI bank). The P5020 has 3 banks, yielding up to 768 MSIs; older SoCs have only one bank.
2019-11-08 03:36:19 +00:00
#define OPENPIC_QUIRK_HIDDEN_IRQS 2 /* May have IRQs beyond FRR[NIRQ] */
powerpc: Bind IRQs to only one interrupt on QorIQ SoCs The QorIQ SoCs don't actually support multicast interrupts, and the references state explicitly that multicast is undefined behavior. Avoid the undefined behavior by binding to only a single CPU, using a quirk to determine if this is necessary. MFC after: 3 weeks
2019-02-06 03:52:14 +00:00
Add suspend/resume state saving for OpenPIC on PowerMac. It's likely this can be used on the others (cpcht and psim), but that has not been tested.
2013-12-21 04:31:54 +00:00
/* Names match the macros in openpicreg.h. */
struct openpic_timer {
uint32_t tcnt;
uint32_t tbase;
uint32_t tvec;
uint32_t tdst;
};
Driver for OpenPIC compatible interrupt controllers. It's fairly PowerMac specific at the moment, but that should be fixable.
2002-07-09 11:26:10 +00:00
struct openpic_softc {
Revamp the interrupt handling in support of INTR_FILTER. This includes: o Revamp the PIC I/F to only abstract the PIC hardware. The resource handling has been moved to nexus, where it belongs. o Include EOI and MASK+EOI methods to the PIC I/F in support of INTR_FILTER. o With the allocation of interrupt resources and setup of interrupt handlers in the common platform code we can delay talking to the PIC hardware after enumeration of all devices. Introduce a call to powerpc_intr_enable() in configure_final() to achieve that and have powerpc_setup_intr() only program the PIC when !cold. o As a consequence of the above, remove all early_attach() glue from the OpenPIC and Heathrow PIC drivers and have them register themselves when they're found during enumeration. o Decouple the interrupt vector from the interrupt request line. Allocate vectors increasingly so that they can be used for the intrcnt index as well. Extend the Heathrow PIC driver to translate between IRQ and vector. The OpenPIC driver already has the support for vectors in hardware. Approved by: re (blanket)
2007-08-11 19:25:32 +00:00
device_t sc_dev;
struct resource *sc_memr;
Provide for multiple, cascaded PICs on PowerPC systems, and extend the OFW interrupt map interface to also return the device's interrupt parent. MFC after: 8.1-RELEASE
2010-06-18 14:06:27 +00:00
struct resource *sc_intr;
Revamp the interrupt handling in support of INTR_FILTER. This includes: o Revamp the PIC I/F to only abstract the PIC hardware. The resource handling has been moved to nexus, where it belongs. o Include EOI and MASK+EOI methods to the PIC I/F in support of INTR_FILTER. o With the allocation of interrupt resources and setup of interrupt handlers in the common platform code we can delay talking to the PIC hardware after enumeration of all devices. Introduce a call to powerpc_intr_enable() in configure_final() to achieve that and have powerpc_setup_intr() only program the PIC when !cold. o As a consequence of the above, remove all early_attach() glue from the OpenPIC and Heathrow PIC drivers and have them register themselves when they're found during enumeration. o Decouple the interrupt vector from the interrupt request line. Allocate vectors increasingly so that they can be used for the intrcnt index as well. Extend the Heathrow PIC driver to translate between IRQ and vector. The OpenPIC driver already has the support for vectors in hardware. Approved by: re (blanket)
2007-08-11 19:25:32 +00:00
bus_space_tag_t sc_bt;
bus_space_handle_t sc_bh;
Driver for OpenPIC compatible interrupt controllers. It's fairly PowerMac specific at the moment, but that should be fixable.
2002-07-09 11:26:10 +00:00
char *sc_version;
Revamp the interrupt handling in support of INTR_FILTER. This includes: o Revamp the PIC I/F to only abstract the PIC hardware. The resource handling has been moved to nexus, where it belongs. o Include EOI and MASK+EOI methods to the PIC I/F in support of INTR_FILTER. o With the allocation of interrupt resources and setup of interrupt handlers in the common platform code we can delay talking to the PIC hardware after enumeration of all devices. Introduce a call to powerpc_intr_enable() in configure_final() to achieve that and have powerpc_setup_intr() only program the PIC when !cold. o As a consequence of the above, remove all early_attach() glue from the OpenPIC and Heathrow PIC drivers and have them register themselves when they're found during enumeration. o Decouple the interrupt vector from the interrupt request line. Allocate vectors increasingly so that they can be used for the intrcnt index as well. Extend the Heathrow PIC driver to translate between IRQ and vector. The OpenPIC driver already has the support for vectors in hardware. Approved by: re (blanket)
2007-08-11 19:25:32 +00:00
int sc_rid;
Provide for multiple, cascaded PICs on PowerPC systems, and extend the OFW interrupt map interface to also return the device's interrupt parent. MFC after: 8.1-RELEASE
2010-06-18 14:06:27 +00:00
int sc_irq;
void *sc_icookie;
Driver for OpenPIC compatible interrupt controllers. It's fairly PowerMac specific at the moment, but that should be fixable.
2002-07-09 11:26:10 +00:00
u_int sc_ncpu;
u_int sc_nirq;
Revamp the interrupt handling in support of INTR_FILTER. This includes: o Revamp the PIC I/F to only abstract the PIC hardware. The resource handling has been moved to nexus, where it belongs. o Include EOI and MASK+EOI methods to the PIC I/F in support of INTR_FILTER. o With the allocation of interrupt resources and setup of interrupt handlers in the common platform code we can delay talking to the PIC hardware after enumeration of all devices. Introduce a call to powerpc_intr_enable() in configure_final() to achieve that and have powerpc_setup_intr() only program the PIC when !cold. o As a consequence of the above, remove all early_attach() glue from the OpenPIC and Heathrow PIC drivers and have them register themselves when they're found during enumeration. o Decouple the interrupt vector from the interrupt request line. Allocate vectors increasingly so that they can be used for the intrcnt index as well. Extend the Heathrow PIC driver to translate between IRQ and vector. The OpenPIC driver already has the support for vectors in hardware. Approved by: re (blanket)
2007-08-11 19:25:32 +00:00
int sc_psim;
powerpc: Bind IRQs to only one interrupt on QorIQ SoCs The QorIQ SoCs don't actually support multicast interrupts, and the references state explicitly that multicast is undefined behavior. Avoid the undefined behavior by binding to only a single CPU, using a quirk to determine if this is necessary. MFC after: 3 weeks
2019-02-06 03:52:14 +00:00
u_int sc_quirks;
Add suspend/resume state saving for OpenPIC on PowerMac. It's likely this can be used on the others (cpcht and psim), but that has not been tested.
2013-12-21 04:31:54 +00:00
/* Saved states. */
uint32_t sc_saved_config;
uint32_t sc_saved_ipis[4];
uint32_t sc_saved_prios[4];
struct openpic_timer sc_saved_timers[OPENPIC_TIMERS];
uint32_t sc_saved_vectors[OPENPIC_SRC_VECTOR_COUNT];
powerpc: clean up empty lines in .c and .h files
2020-09-01 21:20:08 +00:00
Driver for OpenPIC compatible interrupt controllers. It's fairly PowerMac specific at the moment, but that should be fixable.
2002-07-09 11:26:10 +00:00
};
Make the OpenPic driver bus-independent, with attachments for the MacIO chip and PSIM's IOBus. Bus-specific drivers should use the identify method to attach themselves to nexus so interrupt can be allocated before the h/w is probed. The 'early attach' routine in openpic is used for this stage of boot. When h/w is probed, the openpic can be attached properly. It will enable interrupts allocated prior to this.
2004-01-13 11:24:36 +00:00
/*
* Bus-independent attach i/f
*/
Fix the interrupt code, broken 7 months ago. The interrupt framework already supported nested PICs, but was limited to having a nested AT-PIC only. With G5 support the need for nested OpenPIC controllers needed to be added. This was done the wrong way and broke the MPC8555 eval system in the process. OFW, as well as FDT, describe the interrupt routing in terms of a controller and an interrupt pin on it. This needs to be mapped to a flat and global resource: the IRQ. The IRQ is the same as the PCI intline and as such needs to be representable in 8 bits. Secondly, ISA support pretty much dictates that IRQ 0-15 should be reserved for ISA interrupts, because of the internal workins of south bridges. Both were broken. This change reverts revision 209298 for a big part and re-implements it simpler. In particular: o The id() method of the PIC I/F is removed again. It's not needed. o The openpic_attach() function has been changed to take the OFW or FDT phandle of the controller as a second argument. All bus attachments that previously used openpic_attach() as the attach method of the device I/F now implement as bus-specific method and pass the phandle_t to the renamed openpic_attach(). o Change powerpc_register_pic() to take a few more arguments. In particular: - Pass the number of IPIs specificly. The number of IRQs carved out for a PIC is the sum of the number of int. pins and IPIs. - Pass a flag indicating whether the PIC is an AT-PIC or not. This tells the interrupt framework whether to assign IRQ 0-15 or some other range. o Until we implement proper multi-pass bus enumeration, we have to handle the case where we need to map from PIC+pin to IRQ *before* the PIC gets registered. This is done in a similar way as before, but rather than carving out 256 IRQs per PIC, we carve out 128 IRQs (124 pins + 4 IPIs). This is supposed to handle the G5 case, but should really be fixed properly using multiple passes. o Have the interrupt framework set root_pic in most cases and not put that burden in PIC drivers (for the most part). o Remove powerpc_ign_lookup() and replace it with powerpc_get_irq(). Remove IGN_SHIFT, INTR_INTLINE and INTR_IGN. Related to the above, fix the Freescale PCI controller driver, broken by the FDT code. Besides not attaching properly, bus numbers were assigned improperly and enumeration was broken in general. This prevented the AT PIC from being discovered and interrupt routing to work properly. Consequently, the ata(4) controller stopped functioning. Fix the driver, and FDT PCI support, enough to get the MPC8555CDS going again. The FDT PCI code needs a whole lot more work. No breakages are expected, but lackiong G5 hardware, it's possible that there are unpleasant side-effects. At least MPC85xx support is back to where it was 7 months ago -- it's amazing how badly support can be broken in just 7 months... Sponsored by: Juniper Networks
2011-01-29 20:58:38 +00:00
int openpic_common_attach(device_t, uint32_t);
Make the OpenPic driver bus-independent, with attachments for the MacIO chip and PSIM's IOBus. Bus-specific drivers should use the identify method to attach themselves to nexus so interrupt can be allocated before the h/w is probed. The 'early attach' routine in openpic is used for this stage of boot. When h/w is probed, the openpic can be attached properly. It will enable interrupts allocated prior to this.
2004-01-13 11:24:36 +00:00
/*
* PIC interface.
*/
powerpc: Add opaque 'private data' to interrupt vectors The XICS and XIVE need extra data beyond irq and vector. Rather than performing a separate search, it's better for the general interrupt facility to hold a private pointer, since the search already must be done anyway at that level.
2019-01-12 22:05:42 +00:00
void openpic_bind(device_t dev, u_int irq, cpuset_t cpumask, void **);
Add support for the BUS_CONFIG_INTR() method to the platform and to openpic(4). Make use of it in ocpbus(4). On the MPC85xxCDS, IRQ0:4 are active-low.
2008-03-07 22:08:43 +00:00
void openpic_config(device_t, u_int, enum intr_trigger, enum intr_polarity);
Revamp the interrupt handling in support of INTR_FILTER. This includes: o Revamp the PIC I/F to only abstract the PIC hardware. The resource handling has been moved to nexus, where it belongs. o Include EOI and MASK+EOI methods to the PIC I/F in support of INTR_FILTER. o With the allocation of interrupt resources and setup of interrupt handlers in the common platform code we can delay talking to the PIC hardware after enumeration of all devices. Introduce a call to powerpc_intr_enable() in configure_final() to achieve that and have powerpc_setup_intr() only program the PIC when !cold. o As a consequence of the above, remove all early_attach() glue from the OpenPIC and Heathrow PIC drivers and have them register themselves when they're found during enumeration. o Decouple the interrupt vector from the interrupt request line. Allocate vectors increasingly so that they can be used for the intrcnt index as well. Extend the Heathrow PIC driver to translate between IRQ and vector. The OpenPIC driver already has the support for vectors in hardware. Approved by: re (blanket)
2007-08-11 19:25:32 +00:00
void openpic_dispatch(device_t, struct trapframe *);
powerpc: Add opaque 'private data' to interrupt vectors The XICS and XIVE need extra data beyond irq and vector. Rather than performing a separate search, it's better for the general interrupt facility to hold a private pointer, since the search already must be done anyway at that level.
2019-01-12 22:05:42 +00:00
void openpic_enable(device_t, u_int, u_int, void **);
void openpic_eoi(device_t, u_int, void *);
Add PIC support for IPIs. When registering an interrupt handler, the PIC also informs the platform at which IRQ level it can start assigning IPIs, since this can depend on the number of IRQs supported for external interrupts.
2008-02-12 18:14:46 +00:00
void openpic_ipi(device_t, u_int);
powerpc: Add opaque 'private data' to interrupt vectors The XICS and XIVE need extra data beyond irq and vector. Rather than performing a separate search, it's better for the general interrupt facility to hold a private pointer, since the search already must be done anyway at that level.
2019-01-12 22:05:42 +00:00
void openpic_mask(device_t, u_int, void *);
void openpic_unmask(device_t, u_int, void *);
Make the OpenPic driver bus-independent, with attachments for the MacIO chip and PSIM's IOBus. Bus-specific drivers should use the identify method to attach themselves to nexus so interrupt can be allocated before the h/w is probed. The 'early attach' routine in openpic is used for this stage of boot. When h/w is probed, the openpic can be attached properly. It will enable interrupts allocated prior to this.
2004-01-13 11:24:36 +00:00
Add suspend/resume state saving for OpenPIC on PowerMac. It's likely this can be used on the others (cpcht and psim), but that has not been tested.
2013-12-21 04:31:54 +00:00
int openpic_suspend(device_t dev);
int openpic_resume(device_t dev);
Driver for OpenPIC compatible interrupt controllers. It's fairly PowerMac specific at the moment, but that should be fixable.
2002-07-09 11:26:10 +00:00
#endif /* _POWERPC_OPENPICVAR_H_ */
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