2015-05-30 12:17:18 +00:00
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/*
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* Copyright (c) 2014 The DragonFly Project. All rights reserved.
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*
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* This code is derived from software contributed to The DragonFly Project
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* by Matthew Dillon <dillon@backplane.com> and was subsequently ported
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* to FreeBSD by Michael Gmelin <freebsd@grem.de>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name of The DragonFly Project nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific, prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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/*
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2016-11-02 17:04:00 +00:00
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* Intel fourth generation mobile cpus integrated I2C device.
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2015-05-30 12:17:18 +00:00
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*
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* See ig4_reg.h for datasheet reference and notes.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/errno.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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2015-06-25 07:52:51 +00:00
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#include <sys/sx.h>
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2015-05-30 12:17:18 +00:00
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#include <sys/syslog.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <machine/resource.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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add iic interface to ig4 driver, move isl and cyapa to iicbus
Summary:
The hardware does not expose a classic SMBus interface.
Instead it has a lower level interface that can express a far richer
I2C protocol than what smbus offers. However, the interface does not
provide a way to explicitly generate the I2C stop and start conditions.
It's only possible to request that the stop condition is generated
after transferring the next byte in either direction. So, at least
one data byte must always be transferred.
Thus, some I2C sequences are impossible to generate, e.g., an equivalent
of smbus quick command (<start>-<slave addr>-<r/w bit>-<stop>).
At the same time isl(4) and cyapa(4) are moved to iicbus and now they use
iicbus_transfer for communication. Previously they used smbus_trans()
interface that is not defined by the SMBus protocol and was implemented
only by ig4(4). In fact, that interface was impossible to implement
for the typical SMBus controllers like intpm(4) or ichsmb(4) where
a type of the SMBus command must be programmed.
The plan is to remove smbus_trans() and all its uses.
As an aside, the smbus_trans() method deviates from the standard,
but perhaps backwards, FreeBSD convention of using 8-bit slave
addresses (shifted by 1 bit to the left). The method expects
7-bit addresses.
There is a user facing consequence of this change.
A user must now provide device hints for isl and cyapa that specify an iicbus to use
and a slave address on it.
On Chromebook hardware where isl and cyapa devices are commonly found
it is also possible to use a new chromebook_platform(4) driver that
automatically configures isl and cyapa devices. There is no need to
provide the device hints in that case,
Right now smbus(4) driver tries to discover all slaves on the bus.
That is very dangerous. Fortunately, the probing code uses smbus_trans()
to do its job, so it is really enabled for ig4 only.
The plan is to remove that auto-probing code and smbus_trans().
Tested by: grembo, Matthias Apitz <guru@unixarea.de> (w/o
chromebook_platform)
Discussed with: grembo, imp
Reviewed by: wblock (docs)
MFC after: 1 month
Relnotes: yes
Differential Revision: https://reviews.freebsd.org/D8172
2016-10-30 12:15:33 +00:00
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#include <dev/iicbus/iiconf.h>
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2015-05-30 12:17:18 +00:00
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#include <dev/ichiic/ig4_reg.h>
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#include <dev/ichiic/ig4_var.h>
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static int ig4iic_pci_detach(device_t dev);
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2020-04-26 20:16:18 +00:00
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#define PCI_CHIP_BAYTRAIL_I2C_1 0x0f418086
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#define PCI_CHIP_BAYTRAIL_I2C_2 0x0f428086
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#define PCI_CHIP_BAYTRAIL_I2C_3 0x0f438086
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#define PCI_CHIP_BAYTRAIL_I2C_4 0x0f448086
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#define PCI_CHIP_BAYTRAIL_I2C_5 0x0f458086
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#define PCI_CHIP_BAYTRAIL_I2C_6 0x0f468086
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#define PCI_CHIP_BAYTRAIL_I2C_7 0x0f478086
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2015-05-30 12:17:18 +00:00
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#define PCI_CHIP_LYNXPT_LP_I2C_1 0x9c618086
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#define PCI_CHIP_LYNXPT_LP_I2C_2 0x9c628086
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2016-12-20 22:08:36 +00:00
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#define PCI_CHIP_BRASWELL_I2C_1 0x22c18086
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#define PCI_CHIP_BRASWELL_I2C_2 0x22c28086
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#define PCI_CHIP_BRASWELL_I2C_3 0x22c38086
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#define PCI_CHIP_BRASWELL_I2C_5 0x22c58086
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#define PCI_CHIP_BRASWELL_I2C_6 0x22c68086
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#define PCI_CHIP_BRASWELL_I2C_7 0x22c78086
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2018-03-06 23:39:43 +00:00
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#define PCI_CHIP_SKYLAKE_I2C_0 0x9d608086
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#define PCI_CHIP_SKYLAKE_I2C_1 0x9d618086
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#define PCI_CHIP_SKYLAKE_I2C_2 0x9d628086
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#define PCI_CHIP_SKYLAKE_I2C_3 0x9d638086
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#define PCI_CHIP_SKYLAKE_I2C_4 0x9d648086
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#define PCI_CHIP_SKYLAKE_I2C_5 0x9d658086
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2018-09-13 17:36:55 +00:00
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#define PCI_CHIP_KABYLAKE_I2C_0 0xa1608086
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#define PCI_CHIP_KABYLAKE_I2C_1 0xa1618086
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2018-07-06 21:22:50 +00:00
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#define PCI_CHIP_APL_I2C_0 0x5aac8086
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#define PCI_CHIP_APL_I2C_1 0x5aae8086
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#define PCI_CHIP_APL_I2C_2 0x5ab08086
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#define PCI_CHIP_APL_I2C_3 0x5ab28086
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#define PCI_CHIP_APL_I2C_4 0x5ab48086
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#define PCI_CHIP_APL_I2C_5 0x5ab68086
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#define PCI_CHIP_APL_I2C_6 0x5ab88086
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#define PCI_CHIP_APL_I2C_7 0x5aba8086
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2019-11-03 21:16:06 +00:00
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#define PCI_CHIP_CANNONLAKE_LP_I2C_0 0x9dc58086
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#define PCI_CHIP_CANNONLAKE_LP_I2C_1 0x9dc68086
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#define PCI_CHIP_CANNONLAKE_LP_I2C_2 0x9de88086
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#define PCI_CHIP_CANNONLAKE_LP_I2C_3 0x9de98086
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#define PCI_CHIP_CANNONLAKE_LP_I2C_4 0x9dea8086
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#define PCI_CHIP_CANNONLAKE_LP_I2C_5 0x9deb8086
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#define PCI_CHIP_CANNONLAKE_H_I2C_0 0xa3688086
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#define PCI_CHIP_CANNONLAKE_H_I2C_1 0xa3698086
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#define PCI_CHIP_CANNONLAKE_H_I2C_2 0xa36a8086
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#define PCI_CHIP_CANNONLAKE_H_I2C_3 0xa36b8086
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2020-10-31 19:30:23 +00:00
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#define PCI_CHIP_COMETLAKE_LP_I2C_0 0x02e88086
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#define PCI_CHIP_COMETLAKE_LP_I2C_1 0x02e98086
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#define PCI_CHIP_COMETLAKE_LP_I2C_2 0x02ea8086
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#define PCI_CHIP_COMETLAKE_LP_I2C_3 0x02eb8086
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#define PCI_CHIP_COMETLAKE_LP_I2C_4 0x02c58086
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#define PCI_CHIP_COMETLAKE_LP_I2C_5 0x02c68086
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#define PCI_CHIP_COMETLAKE_H_I2C_0 0x06e88086
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#define PCI_CHIP_COMETLAKE_H_I2C_1 0x06e98086
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#define PCI_CHIP_COMETLAKE_H_I2C_2 0x06ea8086
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#define PCI_CHIP_COMETLAKE_H_I2C_3 0x06eb8086
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#define PCI_CHIP_COMETLAKE_V_I2C_0 0xa3e08086
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#define PCI_CHIP_COMETLAKE_V_I2C_1 0xa3e18086
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#define PCI_CHIP_COMETLAKE_V_I2C_2 0xa3e28086
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#define PCI_CHIP_COMETLAKE_V_I2C_3 0xa3e38086
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2023-11-27 15:25:48 +00:00
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#define PCI_CHIP_ICELAKE_LP_I2C_0 0x34e88086
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#define PCI_CHIP_ICELAKE_LP_I2C_1 0x34e98086
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#define PCI_CHIP_ICELAKE_LP_I2C_2 0x34ea8086
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#define PCI_CHIP_ICELAKE_LP_I2C_3 0x34eb8086
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#define PCI_CHIP_ICELAKE_LP_I2C_4 0x34c58086
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#define PCI_CHIP_ICELAKE_LP_I2C_5 0x34c68086
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2020-12-05 10:57:15 +00:00
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#define PCI_CHIP_TIGERLAKE_H_I2C_0 0x43d88086
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#define PCI_CHIP_TIGERLAKE_H_I2C_1 0x43e88086
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#define PCI_CHIP_TIGERLAKE_H_I2C_2 0x43e98086
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#define PCI_CHIP_TIGERLAKE_H_I2C_3 0x43ea8086
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#define PCI_CHIP_TIGERLAKE_H_I2C_4 0x43eb8086
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#define PCI_CHIP_TIGERLAKE_H_I2C_5 0x43ad8086
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#define PCI_CHIP_TIGERLAKE_H_I2C_6 0x43ae8086
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#define PCI_CHIP_TIGERLAKE_LP_I2C_0 0xa0c58086
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#define PCI_CHIP_TIGERLAKE_LP_I2C_1 0xa0c68086
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#define PCI_CHIP_TIGERLAKE_LP_I2C_2 0xa0d88086
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#define PCI_CHIP_TIGERLAKE_LP_I2C_3 0xa0d98086
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#define PCI_CHIP_TIGERLAKE_LP_I2C_4 0xa0e88086
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#define PCI_CHIP_TIGERLAKE_LP_I2C_5 0xa0e98086
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#define PCI_CHIP_TIGERLAKE_LP_I2C_6 0xa0ea8086
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#define PCI_CHIP_TIGERLAKE_LP_I2C_7 0xa0eb8086
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2021-02-23 22:20:36 +00:00
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#define PCI_CHIP_GEMINILAKE_I2C_0 0x31ac8086
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#define PCI_CHIP_GEMINILAKE_I2C_1 0x31ae8086
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#define PCI_CHIP_GEMINILAKE_I2C_2 0x31b08086
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#define PCI_CHIP_GEMINILAKE_I2C_3 0x31b28086
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#define PCI_CHIP_GEMINILAKE_I2C_4 0x31b48086
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#define PCI_CHIP_GEMINILAKE_I2C_5 0x31b68086
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#define PCI_CHIP_GEMINILAKE_I2C_6 0x31b88086
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#define PCI_CHIP_GEMINILAKE_I2C_7 0x31ba8086
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2021-11-25 01:13:38 +00:00
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#define PCI_CHIP_ALDERLAKE_P_I2C_0 0x51e88086
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#define PCI_CHIP_ALDERLAKE_P_I2C_1 0x51e98086
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#define PCI_CHIP_ALDERLAKE_P_I2C_2 0x51ea8086
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#define PCI_CHIP_ALDERLAKE_P_I2C_3 0x51eb8086
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#define PCI_CHIP_ALDERLAKE_P_I2C_4 0x51c58086
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#define PCI_CHIP_ALDERLAKE_P_I2C_5 0x51c68086
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#define PCI_CHIP_ALDERLAKE_P_I2C_6 0x51d88086
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#define PCI_CHIP_ALDERLAKE_P_I2C_7 0x51d98086
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#define PCI_CHIP_ALDERLAKE_S_I2C_0 0x7acc8086
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#define PCI_CHIP_ALDERLAKE_S_I2C_1 0x7acd8086
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#define PCI_CHIP_ALDERLAKE_S_I2C_2 0x7ace8086
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#define PCI_CHIP_ALDERLAKE_S_I2C_3 0x7acf8086
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#define PCI_CHIP_ALDERLAKE_S_I2C_4 0x7afc8086
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#define PCI_CHIP_ALDERLAKE_S_I2C_5 0x7afd8086
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#define PCI_CHIP_ALDERLAKE_M_I2C_0 0x54e88086
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#define PCI_CHIP_ALDERLAKE_M_I2C_1 0x54e98086
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#define PCI_CHIP_ALDERLAKE_M_I2C_2 0x54ea8086
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#define PCI_CHIP_ALDERLAKE_M_I2C_3 0x54eb8086
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#define PCI_CHIP_ALDERLAKE_M_I2C_4 0x54c58086
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#define PCI_CHIP_ALDERLAKE_M_I2C_5 0x54c68086
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2018-07-06 21:22:50 +00:00
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struct ig4iic_pci_device {
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uint32_t devid;
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const char *desc;
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enum ig4_vers version;
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};
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static struct ig4iic_pci_device ig4iic_pci_devices[] = {
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2020-04-26 20:16:18 +00:00
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{ PCI_CHIP_BAYTRAIL_I2C_1, "Intel BayTrail Serial I/O I2C Port 1", IG4_ATOM},
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{ PCI_CHIP_BAYTRAIL_I2C_2, "Intel BayTrail Serial I/O I2C Port 2", IG4_ATOM},
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{ PCI_CHIP_BAYTRAIL_I2C_3, "Intel BayTrail Serial I/O I2C Port 3", IG4_ATOM},
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{ PCI_CHIP_BAYTRAIL_I2C_4, "Intel BayTrail Serial I/O I2C Port 4", IG4_ATOM},
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{ PCI_CHIP_BAYTRAIL_I2C_5, "Intel BayTrail Serial I/O I2C Port 5", IG4_ATOM},
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{ PCI_CHIP_BAYTRAIL_I2C_6, "Intel BayTrail Serial I/O I2C Port 6", IG4_ATOM},
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{ PCI_CHIP_BAYTRAIL_I2C_7, "Intel BayTrail Serial I/O I2C Port 7", IG4_ATOM},
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2018-07-06 21:22:50 +00:00
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{ PCI_CHIP_LYNXPT_LP_I2C_1, "Intel Lynx Point-LP I2C Controller-1", IG4_HASWELL},
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{ PCI_CHIP_LYNXPT_LP_I2C_2, "Intel Lynx Point-LP I2C Controller-2", IG4_HASWELL},
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{ PCI_CHIP_BRASWELL_I2C_1, "Intel Braswell Serial I/O I2C Port 1", IG4_ATOM},
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{ PCI_CHIP_BRASWELL_I2C_2, "Intel Braswell Serial I/O I2C Port 2", IG4_ATOM},
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{ PCI_CHIP_BRASWELL_I2C_3, "Intel Braswell Serial I/O I2C Port 3", IG4_ATOM},
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{ PCI_CHIP_BRASWELL_I2C_5, "Intel Braswell Serial I/O I2C Port 5", IG4_ATOM},
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{ PCI_CHIP_BRASWELL_I2C_6, "Intel Braswell Serial I/O I2C Port 6", IG4_ATOM},
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{ PCI_CHIP_BRASWELL_I2C_7, "Intel Braswell Serial I/O I2C Port 7", IG4_ATOM},
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{ PCI_CHIP_SKYLAKE_I2C_0, "Intel Sunrise Point-LP I2C Controller-0", IG4_SKYLAKE},
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{ PCI_CHIP_SKYLAKE_I2C_1, "Intel Sunrise Point-LP I2C Controller-1", IG4_SKYLAKE},
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{ PCI_CHIP_SKYLAKE_I2C_2, "Intel Sunrise Point-LP I2C Controller-2", IG4_SKYLAKE},
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{ PCI_CHIP_SKYLAKE_I2C_3, "Intel Sunrise Point-LP I2C Controller-3", IG4_SKYLAKE},
|
|
|
|
|
{ PCI_CHIP_SKYLAKE_I2C_4, "Intel Sunrise Point-LP I2C Controller-4", IG4_SKYLAKE},
|
|
|
|
|
{ PCI_CHIP_SKYLAKE_I2C_5, "Intel Sunrise Point-LP I2C Controller-5", IG4_SKYLAKE},
|
2018-09-16 21:44:36 +00:00
|
|
|
{ PCI_CHIP_KABYLAKE_I2C_0, "Intel Sunrise Point-H I2C Controller-0", IG4_SKYLAKE},
|
|
|
|
|
{ PCI_CHIP_KABYLAKE_I2C_1, "Intel Sunrise Point-H I2C Controller-1", IG4_SKYLAKE},
|
2018-07-06 22:01:00 +00:00
|
|
|
{ PCI_CHIP_APL_I2C_0, "Intel Apollo Lake I2C Controller-0", IG4_APL},
|
|
|
|
|
{ PCI_CHIP_APL_I2C_1, "Intel Apollo Lake I2C Controller-1", IG4_APL},
|
|
|
|
|
{ PCI_CHIP_APL_I2C_2, "Intel Apollo Lake I2C Controller-2", IG4_APL},
|
|
|
|
|
{ PCI_CHIP_APL_I2C_3, "Intel Apollo Lake I2C Controller-3", IG4_APL},
|
|
|
|
|
{ PCI_CHIP_APL_I2C_4, "Intel Apollo Lake I2C Controller-4", IG4_APL},
|
|
|
|
|
{ PCI_CHIP_APL_I2C_5, "Intel Apollo Lake I2C Controller-5", IG4_APL},
|
|
|
|
|
{ PCI_CHIP_APL_I2C_6, "Intel Apollo Lake I2C Controller-6", IG4_APL},
|
2019-11-03 21:16:06 +00:00
|
|
|
{ PCI_CHIP_APL_I2C_7, "Intel Apollo Lake I2C Controller-7", IG4_APL},
|
|
|
|
|
{ PCI_CHIP_CANNONLAKE_LP_I2C_0, "Intel Cannon Lake-LP I2C Controller-0", IG4_CANNONLAKE},
|
|
|
|
|
{ PCI_CHIP_CANNONLAKE_LP_I2C_1, "Intel Cannon Lake-LP I2C Controller-1", IG4_CANNONLAKE},
|
|
|
|
|
{ PCI_CHIP_CANNONLAKE_LP_I2C_2, "Intel Cannon Lake-LP I2C Controller-2", IG4_CANNONLAKE},
|
|
|
|
|
{ PCI_CHIP_CANNONLAKE_LP_I2C_3, "Intel Cannon Lake-LP I2C Controller-3", IG4_CANNONLAKE},
|
|
|
|
|
{ PCI_CHIP_CANNONLAKE_LP_I2C_4, "Intel Cannon Lake-LP I2C Controller-4", IG4_CANNONLAKE},
|
|
|
|
|
{ PCI_CHIP_CANNONLAKE_LP_I2C_5, "Intel Cannon Lake-LP I2C Controller-5", IG4_CANNONLAKE},
|
|
|
|
|
{ PCI_CHIP_CANNONLAKE_H_I2C_0, "Intel Cannon Lake-H I2C Controller-0", IG4_CANNONLAKE},
|
|
|
|
|
{ PCI_CHIP_CANNONLAKE_H_I2C_1, "Intel Cannon Lake-H I2C Controller-1", IG4_CANNONLAKE},
|
|
|
|
|
{ PCI_CHIP_CANNONLAKE_H_I2C_2, "Intel Cannon Lake-H I2C Controller-2", IG4_CANNONLAKE},
|
|
|
|
|
{ PCI_CHIP_CANNONLAKE_H_I2C_3, "Intel Cannon Lake-H I2C Controller-3", IG4_CANNONLAKE},
|
2020-10-31 19:30:23 +00:00
|
|
|
{ PCI_CHIP_COMETLAKE_LP_I2C_0, "Intel Comet Lake-LP I2C Controller-0", IG4_CANNONLAKE},
|
|
|
|
|
{ PCI_CHIP_COMETLAKE_LP_I2C_1, "Intel Comet Lake-LP I2C Controller-1", IG4_CANNONLAKE},
|
|
|
|
|
{ PCI_CHIP_COMETLAKE_LP_I2C_2, "Intel Comet Lake-LP I2C Controller-2", IG4_CANNONLAKE},
|
|
|
|
|
{ PCI_CHIP_COMETLAKE_LP_I2C_3, "Intel Comet Lake-LP I2C Controller-3", IG4_CANNONLAKE},
|
|
|
|
|
{ PCI_CHIP_COMETLAKE_LP_I2C_4, "Intel Comet Lake-LP I2C Controller-4", IG4_CANNONLAKE},
|
|
|
|
|
{ PCI_CHIP_COMETLAKE_LP_I2C_5, "Intel Comet Lake-LP I2C Controller-5", IG4_CANNONLAKE},
|
|
|
|
|
{ PCI_CHIP_COMETLAKE_H_I2C_0, "Intel Comet Lake-H I2C Controller-0", IG4_CANNONLAKE},
|
|
|
|
|
{ PCI_CHIP_COMETLAKE_H_I2C_1, "Intel Comet Lake-H I2C Controller-1", IG4_CANNONLAKE},
|
|
|
|
|
{ PCI_CHIP_COMETLAKE_H_I2C_2, "Intel Comet Lake-H I2C Controller-2", IG4_CANNONLAKE},
|
|
|
|
|
{ PCI_CHIP_COMETLAKE_H_I2C_3, "Intel Comet Lake-H I2C Controller-3", IG4_CANNONLAKE},
|
|
|
|
|
{ PCI_CHIP_COMETLAKE_V_I2C_0, "Intel Comet Lake-V I2C Controller-0", IG4_CANNONLAKE},
|
|
|
|
|
{ PCI_CHIP_COMETLAKE_V_I2C_1, "Intel Comet Lake-V I2C Controller-1", IG4_CANNONLAKE},
|
|
|
|
|
{ PCI_CHIP_COMETLAKE_V_I2C_2, "Intel Comet Lake-V I2C Controller-2", IG4_CANNONLAKE},
|
|
|
|
|
{ PCI_CHIP_COMETLAKE_V_I2C_3, "Intel Comet Lake-V I2C Controller-3", IG4_CANNONLAKE},
|
2023-11-27 15:25:48 +00:00
|
|
|
{ PCI_CHIP_ICELAKE_LP_I2C_0, "Intel Ice Lake-LP I2C Controller-0", IG4_TIGERLAKE},
|
|
|
|
|
{ PCI_CHIP_ICELAKE_LP_I2C_1, "Intel Ice Lake-LP I2C Controller-1", IG4_TIGERLAKE},
|
|
|
|
|
{ PCI_CHIP_ICELAKE_LP_I2C_2, "Intel Ice Lake-LP I2C Controller-2", IG4_TIGERLAKE},
|
|
|
|
|
{ PCI_CHIP_ICELAKE_LP_I2C_3, "Intel Ice Lake-LP I2C Controller-3", IG4_TIGERLAKE},
|
|
|
|
|
{ PCI_CHIP_ICELAKE_LP_I2C_4, "Intel Ice Lake-LP I2C Controller-4", IG4_TIGERLAKE},
|
|
|
|
|
{ PCI_CHIP_ICELAKE_LP_I2C_5, "Intel Ice Lake-LP I2C Controller-5", IG4_TIGERLAKE},
|
2020-12-05 10:57:15 +00:00
|
|
|
{ PCI_CHIP_TIGERLAKE_H_I2C_0, "Intel Tiger Lake-H I2C Controller-0", IG4_TIGERLAKE},
|
|
|
|
|
{ PCI_CHIP_TIGERLAKE_H_I2C_1, "Intel Tiger Lake-H I2C Controller-1", IG4_TIGERLAKE},
|
|
|
|
|
{ PCI_CHIP_TIGERLAKE_H_I2C_2, "Intel Tiger Lake-H I2C Controller-2", IG4_TIGERLAKE},
|
|
|
|
|
{ PCI_CHIP_TIGERLAKE_H_I2C_3, "Intel Tiger Lake-H I2C Controller-3", IG4_TIGERLAKE},
|
|
|
|
|
{ PCI_CHIP_TIGERLAKE_H_I2C_4, "Intel Tiger Lake-H I2C Controller-4", IG4_TIGERLAKE},
|
|
|
|
|
{ PCI_CHIP_TIGERLAKE_H_I2C_5, "Intel Tiger Lake-H I2C Controller-5", IG4_TIGERLAKE},
|
|
|
|
|
{ PCI_CHIP_TIGERLAKE_H_I2C_6, "Intel Tiger Lake-H I2C Controller-6", IG4_TIGERLAKE},
|
|
|
|
|
{ PCI_CHIP_TIGERLAKE_LP_I2C_0, "Intel Tiger Lake-LP I2C Controller-0", IG4_SKYLAKE},
|
|
|
|
|
{ PCI_CHIP_TIGERLAKE_LP_I2C_1, "Intel Tiger Lake-LP I2C Controller-1", IG4_SKYLAKE},
|
|
|
|
|
{ PCI_CHIP_TIGERLAKE_LP_I2C_2, "Intel Tiger Lake-LP I2C Controller-2", IG4_SKYLAKE},
|
|
|
|
|
{ PCI_CHIP_TIGERLAKE_LP_I2C_3, "Intel Tiger Lake-LP I2C Controller-3", IG4_SKYLAKE},
|
|
|
|
|
{ PCI_CHIP_TIGERLAKE_LP_I2C_4, "Intel Tiger Lake-LP I2C Controller-4", IG4_SKYLAKE},
|
|
|
|
|
{ PCI_CHIP_TIGERLAKE_LP_I2C_5, "Intel Tiger Lake-LP I2C Controller-5", IG4_SKYLAKE},
|
|
|
|
|
{ PCI_CHIP_TIGERLAKE_LP_I2C_6, "Intel Tiger Lake-LP I2C Controller-6", IG4_SKYLAKE},
|
|
|
|
|
{ PCI_CHIP_TIGERLAKE_LP_I2C_7, "Intel Tiger Lake-LP I2C Controller-7", IG4_SKYLAKE},
|
2021-02-23 22:20:36 +00:00
|
|
|
{ PCI_CHIP_GEMINILAKE_I2C_0, "Intel Gemini Lake I2C Controller-0", IG4_GEMINILAKE},
|
|
|
|
|
{ PCI_CHIP_GEMINILAKE_I2C_1, "Intel Gemini Lake I2C Controller-1", IG4_GEMINILAKE},
|
|
|
|
|
{ PCI_CHIP_GEMINILAKE_I2C_2, "Intel Gemini Lake I2C Controller-2", IG4_GEMINILAKE},
|
|
|
|
|
{ PCI_CHIP_GEMINILAKE_I2C_3, "Intel Gemini Lake I2C Controller-3", IG4_GEMINILAKE},
|
|
|
|
|
{ PCI_CHIP_GEMINILAKE_I2C_4, "Intel Gemini Lake I2C Controller-4", IG4_GEMINILAKE},
|
|
|
|
|
{ PCI_CHIP_GEMINILAKE_I2C_5, "Intel Gemini Lake I2C Controller-5", IG4_GEMINILAKE},
|
|
|
|
|
{ PCI_CHIP_GEMINILAKE_I2C_6, "Intel Gemini Lake I2C Controller-6", IG4_GEMINILAKE},
|
|
|
|
|
{ PCI_CHIP_GEMINILAKE_I2C_7, "Intel Gemini Lake I2C Controller-7", IG4_GEMINILAKE},
|
2021-11-25 01:13:38 +00:00
|
|
|
{ PCI_CHIP_ALDERLAKE_P_I2C_0, "Intel Alder Lake-P I2C Controller-0", IG4_TIGERLAKE},
|
|
|
|
|
{ PCI_CHIP_ALDERLAKE_P_I2C_1, "Intel Alder Lake-P I2C Controller-1", IG4_TIGERLAKE},
|
|
|
|
|
{ PCI_CHIP_ALDERLAKE_P_I2C_2, "Intel Alder Lake-P I2C Controller-2", IG4_TIGERLAKE},
|
|
|
|
|
{ PCI_CHIP_ALDERLAKE_P_I2C_3, "Intel Alder Lake-P I2C Controller-3", IG4_TIGERLAKE},
|
|
|
|
|
{ PCI_CHIP_ALDERLAKE_P_I2C_4, "Intel Alder Lake-P I2C Controller-4", IG4_TIGERLAKE},
|
|
|
|
|
{ PCI_CHIP_ALDERLAKE_P_I2C_5, "Intel Alder Lake-P I2C Controller-5", IG4_TIGERLAKE},
|
|
|
|
|
{ PCI_CHIP_ALDERLAKE_P_I2C_6, "Intel Alder Lake-P I2C Controller-6", IG4_TIGERLAKE},
|
|
|
|
|
{ PCI_CHIP_ALDERLAKE_P_I2C_7, "Intel Alder Lake-P I2C Controller-7", IG4_TIGERLAKE},
|
|
|
|
|
{ PCI_CHIP_ALDERLAKE_S_I2C_0, "Intel Alder Lake-S I2C Controller-0", IG4_TIGERLAKE},
|
|
|
|
|
{ PCI_CHIP_ALDERLAKE_S_I2C_1, "Intel Alder Lake-S I2C Controller-1", IG4_TIGERLAKE},
|
|
|
|
|
{ PCI_CHIP_ALDERLAKE_S_I2C_2, "Intel Alder Lake-S I2C Controller-2", IG4_TIGERLAKE},
|
|
|
|
|
{ PCI_CHIP_ALDERLAKE_S_I2C_3, "Intel Alder Lake-S I2C Controller-3", IG4_TIGERLAKE},
|
|
|
|
|
{ PCI_CHIP_ALDERLAKE_S_I2C_4, "Intel Alder Lake-S I2C Controller-4", IG4_TIGERLAKE},
|
|
|
|
|
{ PCI_CHIP_ALDERLAKE_S_I2C_5, "Intel Alder Lake-S I2C Controller-5", IG4_TIGERLAKE},
|
|
|
|
|
{ PCI_CHIP_ALDERLAKE_M_I2C_0, "Intel Alder Lake-M I2C Controller-0", IG4_TIGERLAKE},
|
|
|
|
|
{ PCI_CHIP_ALDERLAKE_M_I2C_1, "Intel Alder Lake-M I2C Controller-1", IG4_TIGERLAKE},
|
|
|
|
|
{ PCI_CHIP_ALDERLAKE_M_I2C_2, "Intel Alder Lake-M I2C Controller-2", IG4_TIGERLAKE},
|
|
|
|
|
{ PCI_CHIP_ALDERLAKE_M_I2C_3, "Intel Alder Lake-M I2C Controller-3", IG4_TIGERLAKE},
|
|
|
|
|
{ PCI_CHIP_ALDERLAKE_M_I2C_4, "Intel Alder Lake-M I2C Controller-4", IG4_TIGERLAKE},
|
|
|
|
|
{ PCI_CHIP_ALDERLAKE_M_I2C_5, "Intel Alder Lake-M I2C Controller-5", IG4_TIGERLAKE},
|
2018-07-06 21:22:50 +00:00
|
|
|
};
|
2015-05-30 12:17:18 +00:00
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
ig4iic_pci_probe(device_t dev)
|
|
|
|
|
{
|
2018-03-06 23:39:43 +00:00
|
|
|
ig4iic_softc_t *sc = device_get_softc(dev);
|
2018-07-06 21:22:50 +00:00
|
|
|
uint32_t devid;
|
|
|
|
|
int i;
|
2018-03-06 23:39:43 +00:00
|
|
|
|
2018-07-06 21:22:50 +00:00
|
|
|
devid = pci_get_devid(dev);
|
2018-07-09 20:00:45 +00:00
|
|
|
for (i = 0; i < nitems(ig4iic_pci_devices); i++) {
|
2018-07-06 21:22:50 +00:00
|
|
|
if (ig4iic_pci_devices[i].devid == devid) {
|
|
|
|
|
device_set_desc(dev, ig4iic_pci_devices[i].desc);
|
|
|
|
|
sc->version = ig4iic_pci_devices[i].version;
|
|
|
|
|
return (BUS_PROBE_DEFAULT);
|
|
|
|
|
}
|
2015-05-30 12:17:18 +00:00
|
|
|
}
|
2018-07-06 21:22:50 +00:00
|
|
|
return (ENXIO);
|
2015-05-30 12:17:18 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
ig4iic_pci_attach(device_t dev)
|
|
|
|
|
{
|
|
|
|
|
ig4iic_softc_t *sc = device_get_softc(dev);
|
|
|
|
|
int error;
|
|
|
|
|
|
|
|
|
|
sc->dev = dev;
|
|
|
|
|
sc->regs_rid = PCIR_BAR(0);
|
|
|
|
|
sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
|
|
|
|
|
&sc->regs_rid, RF_ACTIVE);
|
|
|
|
|
if (sc->regs_res == NULL) {
|
|
|
|
|
device_printf(dev, "unable to map registers\n");
|
|
|
|
|
ig4iic_pci_detach(dev);
|
|
|
|
|
return (ENXIO);
|
|
|
|
|
}
|
|
|
|
|
sc->intr_rid = 0;
|
|
|
|
|
if (pci_alloc_msi(dev, &sc->intr_rid)) {
|
|
|
|
|
device_printf(dev, "Using MSI\n");
|
|
|
|
|
}
|
|
|
|
|
sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
|
|
|
|
|
&sc->intr_rid, RF_SHAREABLE | RF_ACTIVE);
|
|
|
|
|
if (sc->intr_res == NULL) {
|
|
|
|
|
device_printf(dev, "unable to map interrupt\n");
|
|
|
|
|
ig4iic_pci_detach(dev);
|
|
|
|
|
return (ENXIO);
|
|
|
|
|
}
|
2023-04-18 18:08:28 +00:00
|
|
|
sc->platform_attached = true;
|
2015-05-30 12:17:18 +00:00
|
|
|
|
|
|
|
|
error = ig4iic_attach(sc);
|
|
|
|
|
if (error)
|
|
|
|
|
ig4iic_pci_detach(dev);
|
|
|
|
|
|
|
|
|
|
return (error);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
ig4iic_pci_detach(device_t dev)
|
|
|
|
|
{
|
|
|
|
|
ig4iic_softc_t *sc = device_get_softc(dev);
|
|
|
|
|
int error;
|
|
|
|
|
|
2016-12-26 22:13:43 +00:00
|
|
|
if (sc->platform_attached) {
|
2015-05-30 12:17:18 +00:00
|
|
|
error = ig4iic_detach(sc);
|
|
|
|
|
if (error)
|
|
|
|
|
return (error);
|
2023-04-18 18:08:28 +00:00
|
|
|
sc->platform_attached = false;
|
2015-05-30 12:17:18 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (sc->intr_res) {
|
|
|
|
|
bus_release_resource(dev, SYS_RES_IRQ,
|
|
|
|
|
sc->intr_rid, sc->intr_res);
|
|
|
|
|
sc->intr_res = NULL;
|
|
|
|
|
}
|
|
|
|
|
if (sc->intr_rid != 0)
|
|
|
|
|
pci_release_msi(dev);
|
|
|
|
|
if (sc->regs_res) {
|
|
|
|
|
bus_release_resource(dev, SYS_RES_MEMORY,
|
|
|
|
|
sc->regs_rid, sc->regs_res);
|
|
|
|
|
sc->regs_res = NULL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
|
}
|
|
|
|
|
|
2019-11-03 21:00:55 +00:00
|
|
|
static int
|
|
|
|
|
ig4iic_pci_suspend(device_t dev)
|
|
|
|
|
{
|
|
|
|
|
ig4iic_softc_t *sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
|
|
return (ig4iic_suspend(sc));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
ig4iic_pci_resume(device_t dev)
|
|
|
|
|
{
|
|
|
|
|
ig4iic_softc_t *sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
|
|
return (ig4iic_resume(sc));
|
|
|
|
|
}
|
|
|
|
|
|
2015-05-30 12:17:18 +00:00
|
|
|
static device_method_t ig4iic_pci_methods[] = {
|
|
|
|
|
/* Device interface */
|
|
|
|
|
DEVMETHOD(device_probe, ig4iic_pci_probe),
|
|
|
|
|
DEVMETHOD(device_attach, ig4iic_pci_attach),
|
|
|
|
|
DEVMETHOD(device_detach, ig4iic_pci_detach),
|
2019-11-03 21:00:55 +00:00
|
|
|
DEVMETHOD(device_suspend, ig4iic_pci_suspend),
|
|
|
|
|
DEVMETHOD(device_resume, ig4iic_pci_resume),
|
2015-05-30 12:17:18 +00:00
|
|
|
|
2019-11-03 21:15:01 +00:00
|
|
|
/* Bus interface */
|
|
|
|
|
DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
|
|
|
|
|
DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
|
|
|
|
|
DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
|
|
|
|
|
DEVMETHOD(bus_release_resource, bus_generic_release_resource),
|
|
|
|
|
DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
|
|
|
|
|
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
|
|
|
|
|
DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
|
|
|
|
|
|
|
|
|
|
/* iicbus interface */
|
add iic interface to ig4 driver, move isl and cyapa to iicbus
Summary:
The hardware does not expose a classic SMBus interface.
Instead it has a lower level interface that can express a far richer
I2C protocol than what smbus offers. However, the interface does not
provide a way to explicitly generate the I2C stop and start conditions.
It's only possible to request that the stop condition is generated
after transferring the next byte in either direction. So, at least
one data byte must always be transferred.
Thus, some I2C sequences are impossible to generate, e.g., an equivalent
of smbus quick command (<start>-<slave addr>-<r/w bit>-<stop>).
At the same time isl(4) and cyapa(4) are moved to iicbus and now they use
iicbus_transfer for communication. Previously they used smbus_trans()
interface that is not defined by the SMBus protocol and was implemented
only by ig4(4). In fact, that interface was impossible to implement
for the typical SMBus controllers like intpm(4) or ichsmb(4) where
a type of the SMBus command must be programmed.
The plan is to remove smbus_trans() and all its uses.
As an aside, the smbus_trans() method deviates from the standard,
but perhaps backwards, FreeBSD convention of using 8-bit slave
addresses (shifted by 1 bit to the left). The method expects
7-bit addresses.
There is a user facing consequence of this change.
A user must now provide device hints for isl and cyapa that specify an iicbus to use
and a slave address on it.
On Chromebook hardware where isl and cyapa devices are commonly found
it is also possible to use a new chromebook_platform(4) driver that
automatically configures isl and cyapa devices. There is no need to
provide the device hints in that case,
Right now smbus(4) driver tries to discover all slaves on the bus.
That is very dangerous. Fortunately, the probing code uses smbus_trans()
to do its job, so it is really enabled for ig4 only.
The plan is to remove that auto-probing code and smbus_trans().
Tested by: grembo, Matthias Apitz <guru@unixarea.de> (w/o
chromebook_platform)
Discussed with: grembo, imp
Reviewed by: wblock (docs)
MFC after: 1 month
Relnotes: yes
Differential Revision: https://reviews.freebsd.org/D8172
2016-10-30 12:15:33 +00:00
|
|
|
DEVMETHOD(iicbus_transfer, ig4iic_transfer),
|
|
|
|
|
DEVMETHOD(iicbus_reset, ig4iic_reset),
|
2019-11-03 20:53:13 +00:00
|
|
|
DEVMETHOD(iicbus_callback, ig4iic_callback),
|
add iic interface to ig4 driver, move isl and cyapa to iicbus
Summary:
The hardware does not expose a classic SMBus interface.
Instead it has a lower level interface that can express a far richer
I2C protocol than what smbus offers. However, the interface does not
provide a way to explicitly generate the I2C stop and start conditions.
It's only possible to request that the stop condition is generated
after transferring the next byte in either direction. So, at least
one data byte must always be transferred.
Thus, some I2C sequences are impossible to generate, e.g., an equivalent
of smbus quick command (<start>-<slave addr>-<r/w bit>-<stop>).
At the same time isl(4) and cyapa(4) are moved to iicbus and now they use
iicbus_transfer for communication. Previously they used smbus_trans()
interface that is not defined by the SMBus protocol and was implemented
only by ig4(4). In fact, that interface was impossible to implement
for the typical SMBus controllers like intpm(4) or ichsmb(4) where
a type of the SMBus command must be programmed.
The plan is to remove smbus_trans() and all its uses.
As an aside, the smbus_trans() method deviates from the standard,
but perhaps backwards, FreeBSD convention of using 8-bit slave
addresses (shifted by 1 bit to the left). The method expects
7-bit addresses.
There is a user facing consequence of this change.
A user must now provide device hints for isl and cyapa that specify an iicbus to use
and a slave address on it.
On Chromebook hardware where isl and cyapa devices are commonly found
it is also possible to use a new chromebook_platform(4) driver that
automatically configures isl and cyapa devices. There is no need to
provide the device hints in that case,
Right now smbus(4) driver tries to discover all slaves on the bus.
That is very dangerous. Fortunately, the probing code uses smbus_trans()
to do its job, so it is really enabled for ig4 only.
The plan is to remove that auto-probing code and smbus_trans().
Tested by: grembo, Matthias Apitz <guru@unixarea.de> (w/o
chromebook_platform)
Discussed with: grembo, imp
Reviewed by: wblock (docs)
MFC after: 1 month
Relnotes: yes
Differential Revision: https://reviews.freebsd.org/D8172
2016-10-30 12:15:33 +00:00
|
|
|
|
2015-05-30 12:17:18 +00:00
|
|
|
DEVMETHOD_END
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static driver_t ig4iic_pci_driver = {
|
2019-11-03 20:39:46 +00:00
|
|
|
"ig4iic",
|
2015-06-25 07:52:51 +00:00
|
|
|
ig4iic_pci_methods,
|
|
|
|
|
sizeof(struct ig4iic_softc)
|
2015-05-30 12:17:18 +00:00
|
|
|
};
|
|
|
|
|
|
2022-05-09 19:22:02 +00:00
|
|
|
DRIVER_MODULE_ORDERED(ig4iic, pci, ig4iic_pci_driver, 0, 0, SI_ORDER_ANY);
|
2019-11-03 20:39:46 +00:00
|
|
|
MODULE_DEPEND(ig4iic, pci, 1, 1, 1);
|
|
|
|
|
MODULE_PNP_INFO("W32:vendor/device", pci, ig4iic, ig4iic_pci_devices,
|
2018-12-17 21:34:09 +00:00
|
|
|
nitems(ig4iic_pci_devices));
|