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Enable loongarch64 LLVM target

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This commit is contained in:
zhaixiaojuan 2022-07-07 15:46:10 +08:00 committed by wangrui
parent 10f7ba562a
commit ccf5417799
5 changed files with 18 additions and 2 deletions
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1
compiler/rustc_llvm/build.rs
View file

@ -10,6 +10,7 @@
"aarch64",
"amdgpu",
"avr",
"loongarch",
"m68k",
"mips",
"powerpc",

7
compiler/rustc_llvm/llvm-wrapper/PassWrapper.cpp
View file

@ -146,6 +146,12 @@ extern "C" void LLVMTimeTraceProfilerFinish(const char* FileName) {
#define SUBTARGET_HEXAGON
#endif
#ifdef LLVM_COMPONENT_LOONGARCH
#define SUBTARGET_LOONGARCH SUBTARGET(LoongArch)
#else
#define SUBTARGET_LOONGARCH
#endif
#define GEN_SUBTARGETS \
SUBTARGET_X86 \
SUBTARGET_ARM \
@ -159,6 +165,7 @@ extern "C" void LLVMTimeTraceProfilerFinish(const char* FileName) {
SUBTARGET_SPARC \
SUBTARGET_HEXAGON \
SUBTARGET_RISCV \
SUBTARGET_LOONGARCH \
#define SUBTARGET(x) \
namespace llvm { \

8
compiler/rustc_llvm/src/lib.rs
View file

@ -102,6 +102,14 @@ fn init() { }
LLVMInitializeM68kAsmPrinter,
LLVMInitializeM68kAsmParser
);
init_target!(
llvm_component = "loongarch",
LLVMInitializeLoongArchTargetInfo,
LLVMInitializeLoongArchTarget,
LLVMInitializeLoongArchTargetMC,
LLVMInitializeLoongArchAsmPrinter,
LLVMInitializeLoongArchAsmParser
);
init_target!(
llvm_component = "mips",
LLVMInitializeMipsTargetInfo,

2
config.example.toml
View file

@ -88,7 +88,7 @@ changelog-seen = 2
# the resulting rustc being unable to compile for the disabled architectures.
#
# To add support for new targets, see https://rustc-dev-guide.rust-lang.org/building/new-target.html.
#targets = "AArch64;ARM;BPF;Hexagon;MSP430;Mips;NVPTX;PowerPC;RISCV;Sparc;SystemZ;WebAssembly;X86"
#targets = "AArch64;ARM;BPF;Hexagon;LoongArch;MSP430;Mips;NVPTX;PowerPC;RISCV;Sparc;SystemZ;WebAssembly;X86"
# LLVM experimental targets to build support for. These targets are specified in
# the same format as above, but since these targets are experimental, they are

2
src/bootstrap/llvm.rs
View file

@ -291,7 +291,7 @@ fn run(self, builder: &Builder<'_>) -> LlvmResult {
let llvm_targets = match &builder.config.llvm_targets {
Some(s) => s,
None => {
"AArch64;ARM;BPF;Hexagon;MSP430;Mips;NVPTX;PowerPC;RISCV;\
"AArch64;ARM;BPF;Hexagon;LoongArch;MSP430;Mips;NVPTX;PowerPC;RISCV;\
Sparc;SystemZ;WebAssembly;X86"
}
};