languages/rust
languages/rust
1
0
Fork 0
mirror of https://github.com/rust-lang/rust synced 2024-10-01 22:34:35 +00:00
Code Issues Packages Projects Releases Wiki Activity

Fix typos in floating-point primitive type docs

Browse source
This commit is contained in:
beetrees 2024-08-27 05:25:34 +01:00
parent bf662eb808
commit 969f9702da
No known key found for this signature in database
GPG key ID: 8791BD754191EBD6
1 changed files with 3 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
library/core/src/primitive_docs.rs
View file

@ -1130,7 +1130,7 @@ impl<T> (T,) {}
/// A 16-bit floating point type (specifically, the "binary16" type defined in IEEE 754-2008).
///
/// This type is very similar to [`prim@f32`] but has decreased precision because it uses half as many
/// bits. Please see [the documentation for [`prim@f32`] or [Wikipedia on
/// bits. Please see [the documentation for `f32`](prim@f32) or [Wikipedia on
/// half-precision values][wikipedia] for more information.
///
/// Note that most common platforms will not support `f16` in hardware without enabling extra target
@ -1235,12 +1235,12 @@ mod prim_f64 {}
/// A 128-bit floating point type (specifically, the "binary128" type defined in IEEE 754-2008).
///
/// This type is very similar to [`prim@f32`] and [`prim@f64`], but has increased precision by using twice
/// as many bits as `f64`. Please see [the documentation for [`prim@f32`] or [Wikipedia on
/// as many bits as `f64`. Please see [the documentation for `f32`](prim@f32) or [Wikipedia on
/// quad-precision values][wikipedia] for more information.
///
/// Note that no platforms have hardware support for `f128` without enabling target specific features,
/// as for all instruction set architectures `f128` is considered an optional feature.
/// Only Power ISA ("PowerPC") and RISCV specify it, and only certain microarchitectures
/// Only Power ISA ("PowerPC") and RISC-V specify it, and only certain microarchitectures
/// actually implement it. For x86-64 and AArch64, ISA support is not even specified,
/// so it will always be a software implementation significantly slower than `f64`.
///