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cmd/{asm,compile}: add fused multiply-add support on riscv64
Add support to the assembler for F[N]M{ADD,SUB}[SD] instructions.
Argument order is:
OP RS1, RS2, RS3, RD
Also, add support for the FMA intrinsic to the compiler. Automatic
FMA matching is left to a future CL.
Change-Id: I47166c7393b2ab6bfc2e42aa8c1a8997c3a071b3
Reviewed-on: https://go-review.googlesource.com/c/go/+/293030
Trust: Michael Munday <mike.munday@lowrisc.org>
Run-TryBot: Michael Munday <mike.munday@lowrisc.org>
TryBot-Result: Go Bot <gobot@golang.org>
Reviewed-by: Joel Sing <joel@sing.id.au>
This commit is contained in:
Michael Munday
parent
711e1c8224
commit
ea51e223c2
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@ -793,6 +793,13 @@ func (p *Parser) asmInstruction(op obj.As, cond string, a []obj.Addr) {
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return
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}
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}
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if p.arch.Family == sys.RISCV64 {
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prog.From = a[0]
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prog.Reg = p.getRegister(prog, op, &a[1])
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prog.SetRestArgs([]obj.Addr{a[2]})
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prog.To = a[3]
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break
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}
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if p.arch.Family == sys.S390X {
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if a[1].Type != obj.TYPE_REG {
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p.errorf("second operand must be a register in %s instruction", op)
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8
src/cmd/asm/internal/asm/testdata/riscv64.s
vendored
8
src/cmd/asm/internal/asm/testdata/riscv64.s
vendored
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@ -214,6 +214,10 @@ start:
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FMVSX X5, F0 // 538002f0
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FMVXW F0, X5 // d30200e0
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FMVWX X5, F0 // 538002f0
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FMADDS F1, F2, F3, F4 // 43822018
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FMSUBS F1, F2, F3, F4 // 47822018
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FNMSUBS F1, F2, F3, F4 // 4b822018
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FNMADDS F1, F2, F3, F4 // 4f822018
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// 11.8: Single-Precision Floating-Point Compare Instructions
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FEQS F0, F1, X7 // d3a300a0
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@ -254,6 +258,10 @@ start:
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FSGNJXD F1, F0, F2 // 53211022
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FMVXD F0, X5 // d30200e2
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FMVDX X5, F0 // 538002f2
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FMADDD F1, F2, F3, F4 // 4382201a
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FMSUBD F1, F2, F3, F4 // 4782201a
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FNMSUBD F1, F2, F3, F4 // 4b82201a
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FNMADDD F1, F2, F3, F4 // 4f82201a
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// 12.6: Double-Precision Floating-Point Classify Instruction
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FCLASSD F0, X5 // d31200e2
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@ -317,7 +317,18 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
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p2.From.Reg = v.Reg1()
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p2.To.Type = obj.TYPE_REG
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p2.To.Reg = v.Reg1()
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case ssa.OpRISCV64FMADDD, ssa.OpRISCV64FMSUBD, ssa.OpRISCV64FNMADDD, ssa.OpRISCV64FNMSUBD:
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r := v.Reg()
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r1 := v.Args[0].Reg()
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r2 := v.Args[1].Reg()
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r3 := v.Args[2].Reg()
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = r2
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p.Reg = r1
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p.SetRestArgs([]obj.Addr{{Type: obj.TYPE_REG, Reg: r3}})
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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case ssa.OpRISCV64FSQRTS, ssa.OpRISCV64FNEGS, ssa.OpRISCV64FSQRTD, ssa.OpRISCV64FNEGD,
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ssa.OpRISCV64FMVSX, ssa.OpRISCV64FMVDX,
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ssa.OpRISCV64FCVTSW, ssa.OpRISCV64FCVTSL, ssa.OpRISCV64FCVTWS, ssa.OpRISCV64FCVTLS,
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@ -96,6 +96,8 @@
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(Sqrt ...) => (FSQRTD ...)
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(Sqrt32 ...) => (FSQRTS ...)
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(FMA ...) => (FMADDD ...)
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// Sign and zero extension.
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(SignExt8to16 ...) => (MOVBreg ...)
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@ -713,3 +715,16 @@
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// Addition of zero.
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(ADDI [0] x) => x
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// Merge negation into fused multiply-add and multiply-subtract.
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//
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// Key:
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//
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// [+ -](x * y) [+ -] z.
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// _ N A S
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// D U
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// D B
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//
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// Note: multiplication commutativity handled by rule generator.
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(F(MADD|NMADD|MSUB|NMSUB)D neg:(FNEGD x) y z) && neg.Uses == 1 => (F(NMADD|MADD|NMSUB|MSUB)D x y z)
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(F(MADD|NMADD|MSUB|NMSUB)D x y neg:(FNEGD z)) && neg.Uses == 1 => (F(MSUB|NMSUB|MADD|NMADD)D x y z)
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@ -132,6 +132,7 @@ func init() {
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fp11 = regInfo{inputs: []regMask{fpMask}, outputs: []regMask{fpMask}}
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fp21 = regInfo{inputs: []regMask{fpMask, fpMask}, outputs: []regMask{fpMask}}
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fp31 = regInfo{inputs: []regMask{fpMask, fpMask, fpMask}, outputs: []regMask{fpMask}}
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gpfp = regInfo{inputs: []regMask{gpMask}, outputs: []regMask{fpMask}}
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fpgp = regInfo{inputs: []regMask{fpMask}, outputs: []regMask{gpMask}}
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fpstore = regInfo{inputs: []regMask{gpspsbMask, fpMask, 0}}
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@ -425,6 +426,10 @@ func init() {
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{name: "FSUBD", argLength: 2, reg: fp21, asm: "FSUBD", commutative: false, typ: "Float64"}, // arg0 - arg1
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{name: "FMULD", argLength: 2, reg: fp21, asm: "FMULD", commutative: true, typ: "Float64"}, // arg0 * arg1
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{name: "FDIVD", argLength: 2, reg: fp21, asm: "FDIVD", commutative: false, typ: "Float64"}, // arg0 / arg1
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{name: "FMADDD", argLength: 3, reg: fp31, asm: "FMADDD", commutative: true, typ: "Float64"}, // (arg0 * arg1) + arg2
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{name: "FMSUBD", argLength: 3, reg: fp31, asm: "FMSUBD", commutative: true, typ: "Float64"}, // (arg0 * arg1) - arg2
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{name: "FNMADDD", argLength: 3, reg: fp31, asm: "FNMADDD", commutative: true, typ: "Float64"}, // -(arg0 * arg1) + arg2
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{name: "FNMSUBD", argLength: 3, reg: fp31, asm: "FNMSUBD", commutative: true, typ: "Float64"}, // -(arg0 * arg1) - arg2
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{name: "FSQRTD", argLength: 1, reg: fp11, asm: "FSQRTD", typ: "Float64"}, // sqrt(arg0)
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{name: "FNEGD", argLength: 1, reg: fp11, asm: "FNEGD", typ: "Float64"}, // -arg0
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{name: "FMVDX", argLength: 1, reg: gpfp, asm: "FMVDX", typ: "Float64"}, // reinterpret arg0 as float
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@ -2174,6 +2174,10 @@ const (
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OpRISCV64FSUBD
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OpRISCV64FMULD
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OpRISCV64FDIVD
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OpRISCV64FMADDD
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OpRISCV64FMSUBD
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OpRISCV64FNMADDD
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OpRISCV64FNMSUBD
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OpRISCV64FSQRTD
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OpRISCV64FNEGD
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OpRISCV64FMVDX
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@ -29054,6 +29058,70 @@ var opcodeTable = [...]opInfo{
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},
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},
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},
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{
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name: "FMADDD",
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argLen: 3,
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commutative: true,
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asm: riscv.AFMADDD,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
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{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
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{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
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},
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outputs: []outputInfo{
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{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
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},
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},
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},
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{
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name: "FMSUBD",
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argLen: 3,
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commutative: true,
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asm: riscv.AFMSUBD,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
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{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
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{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
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},
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outputs: []outputInfo{
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{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
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},
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},
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},
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{
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name: "FNMADDD",
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argLen: 3,
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commutative: true,
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asm: riscv.AFNMADDD,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
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{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
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{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
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},
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outputs: []outputInfo{
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{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
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},
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},
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},
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{
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name: "FNMSUBD",
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argLen: 3,
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commutative: true,
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asm: riscv.AFNMSUBD,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
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{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
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{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
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},
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outputs: []outputInfo{
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{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
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},
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},
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},
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{
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name: "FSQRTD",
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argLen: 1,
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@ -209,6 +209,9 @@ func rewriteValueRISCV64(v *Value) bool {
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return rewriteValueRISCV64_OpEqB(v)
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case OpEqPtr:
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return rewriteValueRISCV64_OpEqPtr(v)
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case OpFMA:
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v.Op = OpRISCV64FMADDD
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return true
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case OpGetCallerPC:
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v.Op = OpRISCV64LoweredGetCallerPC
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return true
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@ -432,6 +435,14 @@ func rewriteValueRISCV64(v *Value) bool {
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return rewriteValueRISCV64_OpRISCV64ADDI(v)
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case OpRISCV64AND:
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return rewriteValueRISCV64_OpRISCV64AND(v)
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case OpRISCV64FMADDD:
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return rewriteValueRISCV64_OpRISCV64FMADDD(v)
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case OpRISCV64FMSUBD:
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return rewriteValueRISCV64_OpRISCV64FMSUBD(v)
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case OpRISCV64FNMADDD:
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return rewriteValueRISCV64_OpRISCV64FNMADDD(v)
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case OpRISCV64FNMSUBD:
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return rewriteValueRISCV64_OpRISCV64FNMSUBD(v)
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case OpRISCV64MOVBUload:
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return rewriteValueRISCV64_OpRISCV64MOVBUload(v)
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case OpRISCV64MOVBUreg:
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@ -2829,6 +2840,186 @@ func rewriteValueRISCV64_OpRISCV64AND(v *Value) bool {
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}
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return false
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}
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func rewriteValueRISCV64_OpRISCV64FMADDD(v *Value) bool {
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v_2 := v.Args[2]
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v_1 := v.Args[1]
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v_0 := v.Args[0]
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// match: (FMADDD neg:(FNEGD x) y z)
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// cond: neg.Uses == 1
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// result: (FNMADDD x y z)
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for {
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for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
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neg := v_0
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if neg.Op != OpRISCV64FNEGD {
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continue
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}
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x := neg.Args[0]
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y := v_1
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z := v_2
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if !(neg.Uses == 1) {
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continue
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}
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v.reset(OpRISCV64FNMADDD)
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v.AddArg3(x, y, z)
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return true
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}
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break
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}
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// match: (FMADDD x y neg:(FNEGD z))
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// cond: neg.Uses == 1
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// result: (FMSUBD x y z)
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for {
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x := v_0
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y := v_1
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neg := v_2
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if neg.Op != OpRISCV64FNEGD {
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break
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}
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z := neg.Args[0]
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if !(neg.Uses == 1) {
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break
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}
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v.reset(OpRISCV64FMSUBD)
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v.AddArg3(x, y, z)
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return true
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}
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return false
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}
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func rewriteValueRISCV64_OpRISCV64FMSUBD(v *Value) bool {
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v_2 := v.Args[2]
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v_1 := v.Args[1]
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v_0 := v.Args[0]
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// match: (FMSUBD neg:(FNEGD x) y z)
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// cond: neg.Uses == 1
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// result: (FNMSUBD x y z)
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for {
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for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
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neg := v_0
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if neg.Op != OpRISCV64FNEGD {
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continue
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}
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x := neg.Args[0]
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y := v_1
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z := v_2
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if !(neg.Uses == 1) {
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continue
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}
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v.reset(OpRISCV64FNMSUBD)
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v.AddArg3(x, y, z)
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return true
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}
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break
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}
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// match: (FMSUBD x y neg:(FNEGD z))
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// cond: neg.Uses == 1
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// result: (FMADDD x y z)
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for {
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x := v_0
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y := v_1
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neg := v_2
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if neg.Op != OpRISCV64FNEGD {
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break
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}
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z := neg.Args[0]
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if !(neg.Uses == 1) {
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break
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}
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v.reset(OpRISCV64FMADDD)
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v.AddArg3(x, y, z)
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return true
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}
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return false
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}
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func rewriteValueRISCV64_OpRISCV64FNMADDD(v *Value) bool {
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v_2 := v.Args[2]
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v_1 := v.Args[1]
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v_0 := v.Args[0]
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// match: (FNMADDD neg:(FNEGD x) y z)
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// cond: neg.Uses == 1
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// result: (FMADDD x y z)
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for {
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for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
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neg := v_0
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if neg.Op != OpRISCV64FNEGD {
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continue
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}
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x := neg.Args[0]
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y := v_1
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z := v_2
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if !(neg.Uses == 1) {
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continue
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}
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v.reset(OpRISCV64FMADDD)
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v.AddArg3(x, y, z)
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return true
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}
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break
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}
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// match: (FNMADDD x y neg:(FNEGD z))
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// cond: neg.Uses == 1
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// result: (FNMSUBD x y z)
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for {
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x := v_0
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y := v_1
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neg := v_2
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if neg.Op != OpRISCV64FNEGD {
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break
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}
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z := neg.Args[0]
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if !(neg.Uses == 1) {
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break
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}
|
||||
v.reset(OpRISCV64FNMSUBD)
|
||||
v.AddArg3(x, y, z)
|
||||
return true
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValueRISCV64_OpRISCV64FNMSUBD(v *Value) bool {
|
||||
v_2 := v.Args[2]
|
||||
v_1 := v.Args[1]
|
||||
v_0 := v.Args[0]
|
||||
// match: (FNMSUBD neg:(FNEGD x) y z)
|
||||
// cond: neg.Uses == 1
|
||||
// result: (FMSUBD x y z)
|
||||
for {
|
||||
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
|
||||
neg := v_0
|
||||
if neg.Op != OpRISCV64FNEGD {
|
||||
continue
|
||||
}
|
||||
x := neg.Args[0]
|
||||
y := v_1
|
||||
z := v_2
|
||||
if !(neg.Uses == 1) {
|
||||
continue
|
||||
}
|
||||
v.reset(OpRISCV64FMSUBD)
|
||||
v.AddArg3(x, y, z)
|
||||
return true
|
||||
}
|
||||
break
|
||||
}
|
||||
// match: (FNMSUBD x y neg:(FNEGD z))
|
||||
// cond: neg.Uses == 1
|
||||
// result: (FNMADDD x y z)
|
||||
for {
|
||||
x := v_0
|
||||
y := v_1
|
||||
neg := v_2
|
||||
if neg.Op != OpRISCV64FNEGD {
|
||||
break
|
||||
}
|
||||
z := neg.Args[0]
|
||||
if !(neg.Uses == 1) {
|
||||
break
|
||||
}
|
||||
v.reset(OpRISCV64FNMADDD)
|
||||
v.AddArg3(x, y, z)
|
||||
return true
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValueRISCV64_OpRISCV64MOVBUload(v *Value) bool {
|
||||
v_1 := v.Args[1]
|
||||
v_0 := v.Args[0]
|
||||
|
|
|
|||
|
|
@ -4168,7 +4168,7 @@ func InitTables() {
|
|||
func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
|
||||
return s.newValue3(ssa.OpFMA, types.Types[types.TFLOAT64], args[0], args[1], args[2])
|
||||
},
|
||||
sys.ARM64, sys.PPC64, sys.S390X)
|
||||
sys.ARM64, sys.PPC64, sys.RISCV64, sys.S390X)
|
||||
addF("math", "FMA",
|
||||
func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
|
||||
if !s.config.UseFMA {
|
||||
|
|
|
|||
|
|
@ -1214,60 +1214,77 @@ func validateRIII(ctxt *obj.Link, ins *instruction) {
|
|||
wantIntReg(ctxt, ins.as, "rd", ins.rd)
|
||||
wantIntReg(ctxt, ins.as, "rs1", ins.rs1)
|
||||
wantIntReg(ctxt, ins.as, "rs2", ins.rs2)
|
||||
wantNoneReg(ctxt, ins.as, "rs3", ins.rs3)
|
||||
}
|
||||
|
||||
func validateRFFF(ctxt *obj.Link, ins *instruction) {
|
||||
wantFloatReg(ctxt, ins.as, "rd", ins.rd)
|
||||
wantFloatReg(ctxt, ins.as, "rs1", ins.rs1)
|
||||
wantFloatReg(ctxt, ins.as, "rs2", ins.rs2)
|
||||
wantNoneReg(ctxt, ins.as, "rs3", ins.rs3)
|
||||
}
|
||||
|
||||
func validateRFFFF(ctxt *obj.Link, ins *instruction) {
|
||||
wantFloatReg(ctxt, ins.as, "rd", ins.rd)
|
||||
wantFloatReg(ctxt, ins.as, "rs1", ins.rs1)
|
||||
wantFloatReg(ctxt, ins.as, "rs2", ins.rs2)
|
||||
wantFloatReg(ctxt, ins.as, "rs3", ins.rs3)
|
||||
}
|
||||
|
||||
func validateRFFI(ctxt *obj.Link, ins *instruction) {
|
||||
wantIntReg(ctxt, ins.as, "rd", ins.rd)
|
||||
wantFloatReg(ctxt, ins.as, "rs1", ins.rs1)
|
||||
wantFloatReg(ctxt, ins.as, "rs2", ins.rs2)
|
||||
wantNoneReg(ctxt, ins.as, "rs3", ins.rs3)
|
||||
}
|
||||
|
||||
func validateRFI(ctxt *obj.Link, ins *instruction) {
|
||||
wantIntReg(ctxt, ins.as, "rd", ins.rd)
|
||||
wantNoneReg(ctxt, ins.as, "rs1", ins.rs1)
|
||||
wantFloatReg(ctxt, ins.as, "rs2", ins.rs2)
|
||||
wantNoneReg(ctxt, ins.as, "rs3", ins.rs3)
|
||||
}
|
||||
|
||||
func validateRIF(ctxt *obj.Link, ins *instruction) {
|
||||
wantFloatReg(ctxt, ins.as, "rd", ins.rd)
|
||||
wantNoneReg(ctxt, ins.as, "rs1", ins.rs1)
|
||||
wantIntReg(ctxt, ins.as, "rs2", ins.rs2)
|
||||
wantNoneReg(ctxt, ins.as, "rs3", ins.rs3)
|
||||
}
|
||||
|
||||
func validateRFF(ctxt *obj.Link, ins *instruction) {
|
||||
wantFloatReg(ctxt, ins.as, "rd", ins.rd)
|
||||
wantNoneReg(ctxt, ins.as, "rs1", ins.rs1)
|
||||
wantFloatReg(ctxt, ins.as, "rs2", ins.rs2)
|
||||
wantNoneReg(ctxt, ins.as, "rs3", ins.rs3)
|
||||
}
|
||||
|
||||
func validateII(ctxt *obj.Link, ins *instruction) {
|
||||
wantImmI(ctxt, ins.as, ins.imm, 12)
|
||||
wantIntReg(ctxt, ins.as, "rd", ins.rd)
|
||||
wantIntReg(ctxt, ins.as, "rs1", ins.rs1)
|
||||
wantNoneReg(ctxt, ins.as, "rs3", ins.rs3)
|
||||
}
|
||||
|
||||
func validateIF(ctxt *obj.Link, ins *instruction) {
|
||||
wantImmI(ctxt, ins.as, ins.imm, 12)
|
||||
wantFloatReg(ctxt, ins.as, "rd", ins.rd)
|
||||
wantIntReg(ctxt, ins.as, "rs1", ins.rs1)
|
||||
wantNoneReg(ctxt, ins.as, "rs3", ins.rs3)
|
||||
}
|
||||
|
||||
func validateSI(ctxt *obj.Link, ins *instruction) {
|
||||
wantImmI(ctxt, ins.as, ins.imm, 12)
|
||||
wantIntReg(ctxt, ins.as, "rd", ins.rd)
|
||||
wantIntReg(ctxt, ins.as, "rs1", ins.rs1)
|
||||
wantNoneReg(ctxt, ins.as, "rs3", ins.rs3)
|
||||
}
|
||||
|
||||
func validateSF(ctxt *obj.Link, ins *instruction) {
|
||||
wantImmI(ctxt, ins.as, ins.imm, 12)
|
||||
wantIntReg(ctxt, ins.as, "rd", ins.rd)
|
||||
wantFloatReg(ctxt, ins.as, "rs1", ins.rs1)
|
||||
wantNoneReg(ctxt, ins.as, "rs3", ins.rs3)
|
||||
}
|
||||
|
||||
func validateB(ctxt *obj.Link, ins *instruction) {
|
||||
|
|
@ -1278,6 +1295,7 @@ func validateB(ctxt *obj.Link, ins *instruction) {
|
|||
wantNoneReg(ctxt, ins.as, "rd", ins.rd)
|
||||
wantIntReg(ctxt, ins.as, "rs1", ins.rs1)
|
||||
wantIntReg(ctxt, ins.as, "rs2", ins.rs2)
|
||||
wantNoneReg(ctxt, ins.as, "rs3", ins.rs3)
|
||||
}
|
||||
|
||||
func validateU(ctxt *obj.Link, ins *instruction) {
|
||||
|
|
@ -1285,6 +1303,7 @@ func validateU(ctxt *obj.Link, ins *instruction) {
|
|||
wantIntReg(ctxt, ins.as, "rd", ins.rd)
|
||||
wantNoneReg(ctxt, ins.as, "rs1", ins.rs1)
|
||||
wantNoneReg(ctxt, ins.as, "rs2", ins.rs2)
|
||||
wantNoneReg(ctxt, ins.as, "rs3", ins.rs3)
|
||||
}
|
||||
|
||||
func validateJ(ctxt *obj.Link, ins *instruction) {
|
||||
|
|
@ -1295,6 +1314,7 @@ func validateJ(ctxt *obj.Link, ins *instruction) {
|
|||
wantIntReg(ctxt, ins.as, "rd", ins.rd)
|
||||
wantNoneReg(ctxt, ins.as, "rs1", ins.rs1)
|
||||
wantNoneReg(ctxt, ins.as, "rs2", ins.rs2)
|
||||
wantNoneReg(ctxt, ins.as, "rs3", ins.rs3)
|
||||
}
|
||||
|
||||
func validateRaw(ctxt *obj.Link, ins *instruction) {
|
||||
|
|
@ -1317,6 +1337,22 @@ func encodeR(as obj.As, rs1, rs2, rd, funct3, funct7 uint32) uint32 {
|
|||
return funct7<<25 | enc.funct7<<25 | enc.rs2<<20 | rs2<<20 | rs1<<15 | enc.funct3<<12 | funct3<<12 | rd<<7 | enc.opcode
|
||||
}
|
||||
|
||||
// encodeR4 encodes an R4-type RISC-V instruction.
|
||||
func encodeR4(as obj.As, rs1, rs2, rs3, rd, funct3, funct2 uint32) uint32 {
|
||||
enc := encode(as)
|
||||
if enc == nil {
|
||||
panic("encodeR4: could not encode instruction")
|
||||
}
|
||||
if enc.rs2 != 0 {
|
||||
panic("encodeR4: instruction uses rs2")
|
||||
}
|
||||
funct2 |= enc.funct7
|
||||
if funct2&^3 != 0 {
|
||||
panic("encodeR4: funct2 requires more than 2 bits")
|
||||
}
|
||||
return rs3<<27 | funct2<<25 | rs2<<20 | rs1<<15 | enc.funct3<<12 | funct3<<12 | rd<<7 | enc.opcode
|
||||
}
|
||||
|
||||
func encodeRIII(ins *instruction) uint32 {
|
||||
return encodeR(ins.as, regI(ins.rs1), regI(ins.rs2), regI(ins.rd), ins.funct3, ins.funct7)
|
||||
}
|
||||
|
|
@ -1325,6 +1361,10 @@ func encodeRFFF(ins *instruction) uint32 {
|
|||
return encodeR(ins.as, regF(ins.rs1), regF(ins.rs2), regF(ins.rd), ins.funct3, ins.funct7)
|
||||
}
|
||||
|
||||
func encodeRFFFF(ins *instruction) uint32 {
|
||||
return encodeR4(ins.as, regF(ins.rs1), regF(ins.rs2), regF(ins.rs3), regF(ins.rd), ins.funct3, ins.funct7)
|
||||
}
|
||||
|
||||
func encodeRFFI(ins *instruction) uint32 {
|
||||
return encodeR(ins.as, regF(ins.rs1), regF(ins.rs2), regI(ins.rd), ins.funct3, ins.funct7)
|
||||
}
|
||||
|
|
@ -1462,12 +1502,13 @@ var (
|
|||
// integer register inputs and an integer register output; sFEncoding
|
||||
// indicates an S-type instruction with rs2 being a float register.
|
||||
|
||||
rIIIEncoding = encoding{encode: encodeRIII, validate: validateRIII, length: 4}
|
||||
rFFFEncoding = encoding{encode: encodeRFFF, validate: validateRFFF, length: 4}
|
||||
rFFIEncoding = encoding{encode: encodeRFFI, validate: validateRFFI, length: 4}
|
||||
rFIEncoding = encoding{encode: encodeRFI, validate: validateRFI, length: 4}
|
||||
rIFEncoding = encoding{encode: encodeRIF, validate: validateRIF, length: 4}
|
||||
rFFEncoding = encoding{encode: encodeRFF, validate: validateRFF, length: 4}
|
||||
rIIIEncoding = encoding{encode: encodeRIII, validate: validateRIII, length: 4}
|
||||
rFFFEncoding = encoding{encode: encodeRFFF, validate: validateRFFF, length: 4}
|
||||
rFFFFEncoding = encoding{encode: encodeRFFFF, validate: validateRFFFF, length: 4}
|
||||
rFFIEncoding = encoding{encode: encodeRFFI, validate: validateRFFI, length: 4}
|
||||
rFIEncoding = encoding{encode: encodeRFI, validate: validateRFI, length: 4}
|
||||
rIFEncoding = encoding{encode: encodeRIF, validate: validateRIF, length: 4}
|
||||
rFFEncoding = encoding{encode: encodeRFF, validate: validateRFF, length: 4}
|
||||
|
||||
iIEncoding = encoding{encode: encodeII, validate: validateII, length: 4}
|
||||
iFEncoding = encoding{encode: encodeIF, validate: validateIF, length: 4}
|
||||
|
|
@ -1609,13 +1650,17 @@ var encodings = [ALAST & obj.AMask]encoding{
|
|||
AFSW & obj.AMask: sFEncoding,
|
||||
|
||||
// 11.6: Single-Precision Floating-Point Computational Instructions
|
||||
AFADDS & obj.AMask: rFFFEncoding,
|
||||
AFSUBS & obj.AMask: rFFFEncoding,
|
||||
AFMULS & obj.AMask: rFFFEncoding,
|
||||
AFDIVS & obj.AMask: rFFFEncoding,
|
||||
AFMINS & obj.AMask: rFFFEncoding,
|
||||
AFMAXS & obj.AMask: rFFFEncoding,
|
||||
AFSQRTS & obj.AMask: rFFFEncoding,
|
||||
AFADDS & obj.AMask: rFFFEncoding,
|
||||
AFSUBS & obj.AMask: rFFFEncoding,
|
||||
AFMULS & obj.AMask: rFFFEncoding,
|
||||
AFDIVS & obj.AMask: rFFFEncoding,
|
||||
AFMINS & obj.AMask: rFFFEncoding,
|
||||
AFMAXS & obj.AMask: rFFFEncoding,
|
||||
AFSQRTS & obj.AMask: rFFFEncoding,
|
||||
AFMADDS & obj.AMask: rFFFFEncoding,
|
||||
AFMSUBS & obj.AMask: rFFFFEncoding,
|
||||
AFNMSUBS & obj.AMask: rFFFFEncoding,
|
||||
AFNMADDS & obj.AMask: rFFFFEncoding,
|
||||
|
||||
// 11.7: Single-Precision Floating-Point Conversion and Move Instructions
|
||||
AFCVTWS & obj.AMask: rFIEncoding,
|
||||
|
|
@ -1647,13 +1692,17 @@ var encodings = [ALAST & obj.AMask]encoding{
|
|||
AFSD & obj.AMask: sFEncoding,
|
||||
|
||||
// 12.4: Double-Precision Floating-Point Computational Instructions
|
||||
AFADDD & obj.AMask: rFFFEncoding,
|
||||
AFSUBD & obj.AMask: rFFFEncoding,
|
||||
AFMULD & obj.AMask: rFFFEncoding,
|
||||
AFDIVD & obj.AMask: rFFFEncoding,
|
||||
AFMIND & obj.AMask: rFFFEncoding,
|
||||
AFMAXD & obj.AMask: rFFFEncoding,
|
||||
AFSQRTD & obj.AMask: rFFFEncoding,
|
||||
AFADDD & obj.AMask: rFFFEncoding,
|
||||
AFSUBD & obj.AMask: rFFFEncoding,
|
||||
AFMULD & obj.AMask: rFFFEncoding,
|
||||
AFDIVD & obj.AMask: rFFFEncoding,
|
||||
AFMIND & obj.AMask: rFFFEncoding,
|
||||
AFMAXD & obj.AMask: rFFFEncoding,
|
||||
AFSQRTD & obj.AMask: rFFFEncoding,
|
||||
AFMADDD & obj.AMask: rFFFFEncoding,
|
||||
AFMSUBD & obj.AMask: rFFFFEncoding,
|
||||
AFNMSUBD & obj.AMask: rFFFFEncoding,
|
||||
AFNMADDD & obj.AMask: rFFFFEncoding,
|
||||
|
||||
// 12.5: Double-Precision Floating-Point Conversion and Move Instructions
|
||||
AFCVTWD & obj.AMask: rFIEncoding,
|
||||
|
|
@ -1719,9 +1768,10 @@ type instruction struct {
|
|||
rd uint32 // Destination register
|
||||
rs1 uint32 // Source register 1
|
||||
rs2 uint32 // Source register 2
|
||||
rs3 uint32 // Source register 3
|
||||
imm int64 // Immediate
|
||||
funct3 uint32 // Function 3
|
||||
funct7 uint32 // Function 7
|
||||
funct7 uint32 // Function 7 (or Function 2)
|
||||
}
|
||||
|
||||
func (ins *instruction) encode() (uint32, error) {
|
||||
|
|
@ -1762,6 +1812,12 @@ func instructionsForProg(p *obj.Prog) []*instruction {
|
|||
imm: p.From.Offset,
|
||||
}
|
||||
|
||||
if len(p.RestArgs) == 1 {
|
||||
ins.rs3 = uint32(p.RestArgs[0].Reg)
|
||||
} else if len(p.RestArgs) > 0 {
|
||||
p.Ctxt.Diag("too many source registers")
|
||||
}
|
||||
|
||||
inss := []*instruction{ins}
|
||||
switch ins.as {
|
||||
case AJAL, AJALR:
|
||||
|
|
@ -1899,6 +1955,12 @@ func instructionsForProg(p *obj.Prog) []*instruction {
|
|||
ins.rs1 = uint32(p.From.Reg)
|
||||
ins.rs2 = REG_F0
|
||||
|
||||
case AFMADDS, AFMSUBS, AFNMADDS, AFNMSUBS,
|
||||
AFMADDD, AFMSUBD, AFNMADDD, AFNMSUBD:
|
||||
// Swap the first two operands so that the operands are in the same
|
||||
// order as they are in the specification: RS1, RS2, RS3, RD.
|
||||
ins.rs1, ins.rs2 = ins.rs2, ins.rs1
|
||||
|
||||
case ANEG, ANEGW:
|
||||
// NEG rs, rd -> SUB rs, X0, rd
|
||||
ins.as = ASUB
|
||||
|
|
|
|||
|
|
@ -125,9 +125,25 @@ func fma(x, y, z float64) float64 {
|
|||
// s390x:"FMADD"
|
||||
// ppc64:"FMADD"
|
||||
// ppc64le:"FMADD"
|
||||
// riscv64:"FMADDD"
|
||||
return math.FMA(x, y, z)
|
||||
}
|
||||
|
||||
func fms(x, y, z float64) float64 {
|
||||
// riscv64:"FMSUBD"
|
||||
return math.FMA(x, y, -z)
|
||||
}
|
||||
|
||||
func fnma(x, y, z float64) float64 {
|
||||
// riscv64:"FNMADDD"
|
||||
return math.FMA(-x, y, z)
|
||||
}
|
||||
|
||||
func fnms(x, y, z float64) float64 {
|
||||
// riscv64:"FNMSUBD"
|
||||
return math.FMA(x, -y, -z)
|
||||
}
|
||||
|
||||
func fromFloat64(f64 float64) uint64 {
|
||||
// amd64:"MOVQ\tX.*, [^X].*"
|
||||
// arm64:"FMOVD\tF.*, R.*"
|
||||
|
|
|
|||
Loading…
Reference in a new issue