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cmd/compile: intrinsify RotateLeft{32,64} on loong64
Benchmark on crypto/sha256 (provided by Xiaodong Liu): name old time/op new time/op delta Hash8Bytes/New 1.19µs ± 0% 0.97µs ± 0% -18.75% (p=0.000 n=9+9) Hash8Bytes/Sum224 1.21µs ± 0% 0.97µs ± 0% -20.04% (p=0.000 n=9+10) Hash8Bytes/Sum256 1.21µs ± 0% 0.98µs ± 0% -19.16% (p=0.000 n=10+7) Hash1K/New 15.9µs ± 0% 12.4µs ± 0% -22.10% (p=0.000 n=10+10) Hash1K/Sum224 15.9µs ± 0% 12.4µs ± 0% -22.18% (p=0.000 n=8+10) Hash1K/Sum256 15.9µs ± 0% 12.4µs ± 0% -22.15% (p=0.000 n=10+9) Hash8K/New 119µs ± 0% 92µs ± 0% -22.40% (p=0.000 n=10+9) Hash8K/Sum224 119µs ± 0% 92µs ± 0% -22.41% (p=0.000 n=9+10) Hash8K/Sum256 119µs ± 0% 92µs ± 0% -22.40% (p=0.000 n=9+9) name old speed new speed delta Hash8Bytes/New 6.70MB/s ± 0% 8.25MB/s ± 0% +23.13% (p=0.000 n=10+10) Hash8Bytes/Sum224 6.60MB/s ± 0% 8.26MB/s ± 0% +25.06% (p=0.000 n=10+10) Hash8Bytes/Sum256 6.59MB/s ± 0% 8.15MB/s ± 0% +23.67% (p=0.000 n=10+7) Hash1K/New 64.3MB/s ± 0% 82.5MB/s ± 0% +28.36% (p=0.000 n=10+10) Hash1K/Sum224 64.3MB/s ± 0% 82.6MB/s ± 0% +28.51% (p=0.000 n=10+10) Hash1K/Sum256 64.3MB/s ± 0% 82.6MB/s ± 0% +28.46% (p=0.000 n=9+9) Hash8K/New 69.0MB/s ± 0% 89.0MB/s ± 0% +28.87% (p=0.000 n=10+8) Hash8K/Sum224 69.0MB/s ± 0% 89.0MB/s ± 0% +28.88% (p=0.000 n=9+10) Hash8K/Sum256 69.0MB/s ± 0% 88.9MB/s ± 0% +28.87% (p=0.000 n=8+9) Benchmark on crypto/sha512 (provided by Xiaodong Liu): name old time/op new time/op delta Hash8Bytes/New 1.55µs ± 0% 1.31µs ± 0% -15.67% (p=0.000 n=10+10) Hash8Bytes/Sum384 1.59µs ± 0% 1.35µs ± 0% -14.97% (p=0.000 n=10+10) Hash8Bytes/Sum512 1.62µs ± 0% 1.39µs ± 0% -14.02% (p=0.000 n=10+10) Hash1K/New 10.7µs ± 0% 8.6µs ± 0% -19.60% (p=0.000 n=8+8) Hash1K/Sum384 10.8µs ± 0% 8.7µs ± 0% -19.40% (p=0.000 n=9+9) Hash1K/Sum512 10.8µs ± 0% 8.7µs ± 0% -19.35% (p=0.000 n=9+10) Hash8K/New 74.6µs ± 0% 59.6µs ± 0% -20.08% (p=0.000 n=10+9) Hash8K/Sum384 74.7µs ± 0% 59.7µs ± 0% -20.04% (p=0.000 n=9+8) Hash8K/Sum512 74.7µs ± 0% 59.7µs ± 0% -20.01% (p=0.000 n=10+10) name old speed new speed delta Hash8Bytes/New 5.16MB/s ± 0% 6.12MB/s ± 0% +18.60% (p=0.000 n=10+8) Hash8Bytes/Sum384 5.02MB/s ± 0% 5.90MB/s ± 0% +17.56% (p=0.000 n=10+10) Hash8Bytes/Sum512 4.94MB/s ± 0% 5.74MB/s ± 0% +16.29% (p=0.000 n=10+9) Hash1K/New 95.4MB/s ± 0% 118.6MB/s ± 0% +24.38% (p=0.000 n=10+10) Hash1K/Sum384 95.0MB/s ± 0% 117.9MB/s ± 0% +24.06% (p=0.000 n=8+9) Hash1K/Sum512 94.8MB/s ± 0% 117.5MB/s ± 0% +23.99% (p=0.000 n=8+9) Hash8K/New 110MB/s ± 0% 137MB/s ± 0% +25.11% (p=0.000 n=9+6) Hash8K/Sum384 110MB/s ± 0% 137MB/s ± 0% +25.07% (p=0.000 n=9+8) Hash8K/Sum512 110MB/s ± 0% 137MB/s ± 0% +25.01% (p=0.000 n=10+10) Change-Id: I28ccfce634659305a336c8e0a3f8589f7361d661 Reviewed-on: https://go-review.googlesource.com/c/go/+/422317 Reviewed-by: Keith Randall <khr@golang.org> Run-TryBot: Wayne Zuo <wdvxdr@golangcn.org> Reviewed-by: Ian Lance Taylor <iant@google.com> Reviewed-by: David Chase <drchase@google.com>
This commit is contained in:
Wayne Zuo
David Chase
parent
7d574466a9
commit
e8f0340fa4
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@ -134,6 +134,8 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
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ssa.OpLOONG64SLLV,
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ssa.OpLOONG64SRLV,
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ssa.OpLOONG64SRAV,
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ssa.OpLOONG64ROTR,
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ssa.OpLOONG64ROTRV,
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ssa.OpLOONG64ADDF,
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ssa.OpLOONG64ADDD,
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ssa.OpLOONG64SUBF,
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@ -165,6 +167,8 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
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ssa.OpLOONG64SLLVconst,
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ssa.OpLOONG64SRLVconst,
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ssa.OpLOONG64SRAVconst,
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ssa.OpLOONG64ROTRconst,
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ssa.OpLOONG64ROTRVconst,
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ssa.OpLOONG64SGTconst,
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ssa.OpLOONG64SGTUconst:
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p := s.Prog(v.Op.Asm())
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@ -111,8 +111,8 @@
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// rotates
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(RotateLeft8 <t> x (MOVVconst [c])) => (Or8 (Lsh8x64 <t> x (MOVVconst [c&7])) (Rsh8Ux64 <t> x (MOVVconst [-c&7])))
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(RotateLeft16 <t> x (MOVVconst [c])) => (Or16 (Lsh16x64 <t> x (MOVVconst [c&15])) (Rsh16Ux64 <t> x (MOVVconst [-c&15])))
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(RotateLeft32 <t> x (MOVVconst [c])) => (Or32 (Lsh32x64 <t> x (MOVVconst [c&31])) (Rsh32Ux64 <t> x (MOVVconst [-c&31])))
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(RotateLeft64 <t> x (MOVVconst [c])) => (Or64 (Lsh64x64 <t> x (MOVVconst [c&63])) (Rsh64Ux64 <t> x (MOVVconst [-c&63])))
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(RotateLeft32 x y) => (ROTR x (NEGV <y.Type> y))
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(RotateLeft64 x y) => (ROTRV x (NEGV <y.Type> y))
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// unary ops
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(Neg(64|32|16|8) ...) => (NEGV ...)
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@ -572,6 +572,8 @@
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(SLLV x (MOVVconst [c])) => (SLLVconst x [c])
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(SRLV x (MOVVconst [c])) => (SRLVconst x [c])
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(SRAV x (MOVVconst [c])) => (SRAVconst x [c])
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(ROTR x (MOVVconst [c])) => (ROTRconst x [c&31])
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(ROTRV x (MOVVconst [c])) => (ROTRVconst x [c&63])
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(SGT (MOVVconst [c]) x) && is32Bit(c) => (SGTconst [c] x)
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(SGTU (MOVVconst [c]) x) && is32Bit(c) => (SGTUconst [c] x)
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@ -196,12 +196,16 @@ func init() {
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{name: "SQRTF", argLength: 1, reg: fp11, asm: "SQRTF"}, // sqrt(arg0), float32
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// shifts
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{name: "SLLV", argLength: 2, reg: gp21, asm: "SLLV"}, // arg0 << arg1, shift amount is mod 64
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{name: "SLLVconst", argLength: 1, reg: gp11, asm: "SLLV", aux: "Int64"}, // arg0 << auxInt
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{name: "SRLV", argLength: 2, reg: gp21, asm: "SRLV"}, // arg0 >> arg1, unsigned, shift amount is mod 64
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{name: "SRLVconst", argLength: 1, reg: gp11, asm: "SRLV", aux: "Int64"}, // arg0 >> auxInt, unsigned
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{name: "SRAV", argLength: 2, reg: gp21, asm: "SRAV"}, // arg0 >> arg1, signed, shift amount is mod 64
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{name: "SRAVconst", argLength: 1, reg: gp11, asm: "SRAV", aux: "Int64"}, // arg0 >> auxInt, signed
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{name: "SLLV", argLength: 2, reg: gp21, asm: "SLLV"}, // arg0 << arg1, shift amount is mod 64
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{name: "SLLVconst", argLength: 1, reg: gp11, asm: "SLLV", aux: "Int64"}, // arg0 << auxInt
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{name: "SRLV", argLength: 2, reg: gp21, asm: "SRLV"}, // arg0 >> arg1, unsigned, shift amount is mod 64
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{name: "SRLVconst", argLength: 1, reg: gp11, asm: "SRLV", aux: "Int64"}, // arg0 >> auxInt, unsigned
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{name: "SRAV", argLength: 2, reg: gp21, asm: "SRAV"}, // arg0 >> arg1, signed, shift amount is mod 64
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{name: "SRAVconst", argLength: 1, reg: gp11, asm: "SRAV", aux: "Int64"}, // arg0 >> auxInt, signed
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{name: "ROTR", argLength: 2, reg: gp21, asm: "ROTR"}, // arg0 right rotate by (arg1 mod 32) bits
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{name: "ROTRV", argLength: 2, reg: gp21, asm: "ROTRV"}, // arg0 right rotate by (arg1 mod 64) bits
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{name: "ROTRconst", argLength: 1, reg: gp11, asm: "ROTR", aux: "Int64"}, // uint32(arg0) right rotate by auxInt bits, auxInt should be in the range 0 to 31.
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{name: "ROTRVconst", argLength: 1, reg: gp11, asm: "ROTRV", aux: "Int64"}, // arg0 right rotate by auxInt bits, auxInt should be in the range 0 to 63.
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// comparisons
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{name: "SGT", argLength: 2, reg: gp21, asm: "SGT", typ: "Bool"}, // 1 if arg0 > arg1 (signed), 0 otherwise
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@ -1746,6 +1746,10 @@ const (
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OpLOONG64SRLVconst
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OpLOONG64SRAV
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OpLOONG64SRAVconst
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OpLOONG64ROTR
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OpLOONG64ROTRV
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OpLOONG64ROTRconst
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OpLOONG64ROTRVconst
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OpLOONG64SGT
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OpLOONG64SGTconst
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OpLOONG64SGTU
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@ -23344,6 +23348,62 @@ var opcodeTable = [...]opInfo{
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},
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},
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},
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{
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name: "ROTR",
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argLen: 2,
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asm: loong64.AROTR,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
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{1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
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},
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outputs: []outputInfo{
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{0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
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},
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},
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},
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{
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name: "ROTRV",
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argLen: 2,
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asm: loong64.AROTRV,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
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{1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
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},
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outputs: []outputInfo{
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{0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
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},
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},
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},
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{
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name: "ROTRconst",
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auxType: auxInt64,
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argLen: 1,
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asm: loong64.AROTR,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
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},
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outputs: []outputInfo{
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{0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
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},
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},
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},
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{
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name: "ROTRVconst",
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auxType: auxInt64,
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argLen: 1,
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asm: loong64.AROTRV,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
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},
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outputs: []outputInfo{
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{0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
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},
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},
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},
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{
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name: "SGT",
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argLen: 2,
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@ -1988,7 +1988,7 @@ func canRotate(c *Config, bits int64) bool {
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switch c.arch {
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case "386", "amd64":
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return true
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case "arm", "arm64", "s390x", "ppc64", "ppc64le", "wasm":
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case "arm", "arm64", "s390x", "ppc64", "ppc64le", "wasm", "loong64":
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return bits >= 32
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default:
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return false
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@ -291,6 +291,10 @@ func rewriteValueLOONG64(v *Value) bool {
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return rewriteValueLOONG64_OpLOONG64OR(v)
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case OpLOONG64ORconst:
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return rewriteValueLOONG64_OpLOONG64ORconst(v)
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case OpLOONG64ROTR:
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return rewriteValueLOONG64_OpLOONG64ROTR(v)
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case OpLOONG64ROTRV:
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return rewriteValueLOONG64_OpLOONG64ROTRV(v)
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case OpLOONG64SGT:
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return rewriteValueLOONG64_OpLOONG64SGT(v)
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case OpLOONG64SGTU:
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@ -3307,6 +3311,42 @@ func rewriteValueLOONG64_OpLOONG64ORconst(v *Value) bool {
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}
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return false
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}
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func rewriteValueLOONG64_OpLOONG64ROTR(v *Value) bool {
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v_1 := v.Args[1]
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v_0 := v.Args[0]
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// match: (ROTR x (MOVVconst [c]))
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// result: (ROTRconst x [c&31])
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for {
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x := v_0
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if v_1.Op != OpLOONG64MOVVconst {
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break
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}
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c := auxIntToInt64(v_1.AuxInt)
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v.reset(OpLOONG64ROTRconst)
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v.AuxInt = int64ToAuxInt(c & 31)
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v.AddArg(x)
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return true
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}
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return false
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}
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func rewriteValueLOONG64_OpLOONG64ROTRV(v *Value) bool {
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v_1 := v.Args[1]
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v_0 := v.Args[0]
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// match: (ROTRV x (MOVVconst [c]))
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// result: (ROTRVconst x [c&63])
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for {
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x := v_0
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if v_1.Op != OpLOONG64MOVVconst {
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break
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}
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c := auxIntToInt64(v_1.AuxInt)
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v.reset(OpLOONG64ROTRVconst)
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v.AuxInt = int64ToAuxInt(c & 63)
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v.AddArg(x)
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return true
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}
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return false
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}
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func rewriteValueLOONG64_OpLOONG64SGT(v *Value) bool {
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v_1 := v.Args[1]
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v_0 := v.Args[0]
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@ -5827,57 +5867,33 @@ func rewriteValueLOONG64_OpRotateLeft32(v *Value) bool {
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v_1 := v.Args[1]
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v_0 := v.Args[0]
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b := v.Block
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typ := &b.Func.Config.Types
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// match: (RotateLeft32 <t> x (MOVVconst [c]))
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// result: (Or32 (Lsh32x64 <t> x (MOVVconst [c&31])) (Rsh32Ux64 <t> x (MOVVconst [-c&31])))
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// match: (RotateLeft32 x y)
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// result: (ROTR x (NEGV <y.Type> y))
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for {
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t := v.Type
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x := v_0
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if v_1.Op != OpLOONG64MOVVconst {
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break
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}
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c := auxIntToInt64(v_1.AuxInt)
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v.reset(OpOr32)
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v0 := b.NewValue0(v.Pos, OpLsh32x64, t)
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v1 := b.NewValue0(v.Pos, OpLOONG64MOVVconst, typ.UInt64)
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v1.AuxInt = int64ToAuxInt(c & 31)
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v0.AddArg2(x, v1)
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v2 := b.NewValue0(v.Pos, OpRsh32Ux64, t)
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v3 := b.NewValue0(v.Pos, OpLOONG64MOVVconst, typ.UInt64)
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v3.AuxInt = int64ToAuxInt(-c & 31)
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v2.AddArg2(x, v3)
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v.AddArg2(v0, v2)
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y := v_1
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v.reset(OpLOONG64ROTR)
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v0 := b.NewValue0(v.Pos, OpLOONG64NEGV, y.Type)
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v0.AddArg(y)
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v.AddArg2(x, v0)
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return true
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}
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return false
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}
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func rewriteValueLOONG64_OpRotateLeft64(v *Value) bool {
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v_1 := v.Args[1]
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v_0 := v.Args[0]
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b := v.Block
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typ := &b.Func.Config.Types
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// match: (RotateLeft64 <t> x (MOVVconst [c]))
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// result: (Or64 (Lsh64x64 <t> x (MOVVconst [c&63])) (Rsh64Ux64 <t> x (MOVVconst [-c&63])))
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// match: (RotateLeft64 x y)
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// result: (ROTRV x (NEGV <y.Type> y))
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for {
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t := v.Type
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x := v_0
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if v_1.Op != OpLOONG64MOVVconst {
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break
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}
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c := auxIntToInt64(v_1.AuxInt)
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v.reset(OpOr64)
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v0 := b.NewValue0(v.Pos, OpLsh64x64, t)
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v1 := b.NewValue0(v.Pos, OpLOONG64MOVVconst, typ.UInt64)
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v1.AuxInt = int64ToAuxInt(c & 63)
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v0.AddArg2(x, v1)
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v2 := b.NewValue0(v.Pos, OpRsh64Ux64, t)
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v3 := b.NewValue0(v.Pos, OpLOONG64MOVVconst, typ.UInt64)
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v3.AuxInt = int64ToAuxInt(-c & 63)
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v2.AddArg2(x, v3)
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v.AddArg2(v0, v2)
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y := v_1
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v.reset(OpLOONG64ROTRV)
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v0 := b.NewValue0(v.Pos, OpLOONG64NEGV, y.Type)
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v0.AddArg(y)
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v.AddArg2(x, v0)
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return true
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}
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return false
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}
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func rewriteValueLOONG64_OpRotateLeft8(v *Value) bool {
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v_1 := v.Args[1]
|
||||
|
|
|
|||
|
|
@ -4643,12 +4643,12 @@ func InitTables() {
|
|||
func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
|
||||
return s.newValue2(ssa.OpRotateLeft32, types.Types[types.TUINT32], args[0], args[1])
|
||||
},
|
||||
sys.AMD64, sys.ARM, sys.ARM64, sys.S390X, sys.PPC64, sys.Wasm)
|
||||
sys.AMD64, sys.ARM, sys.ARM64, sys.S390X, sys.PPC64, sys.Wasm, sys.Loong64)
|
||||
addF("math/bits", "RotateLeft64",
|
||||
func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
|
||||
return s.newValue2(ssa.OpRotateLeft64, types.Types[types.TUINT64], args[0], args[1])
|
||||
},
|
||||
sys.AMD64, sys.ARM64, sys.S390X, sys.PPC64, sys.Wasm)
|
||||
sys.AMD64, sys.ARM64, sys.S390X, sys.PPC64, sys.Wasm, sys.Loong64)
|
||||
alias("math/bits", "RotateLeft", "math/bits", "RotateLeft64", p8...)
|
||||
|
||||
makeOnesCountAMD64 := func(op ssa.Op) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@ func rot64(x uint64) uint64 {
|
|||
// amd64:"ROLQ\t[$]7"
|
||||
// ppc64:"ROTL\t[$]7"
|
||||
// ppc64le:"ROTL\t[$]7"
|
||||
// loong64: "ROTRV\t[$]57"
|
||||
a += x<<7 | x>>57
|
||||
|
||||
// amd64:"ROLQ\t[$]8"
|
||||
|
|
@ -25,6 +26,7 @@ func rot64(x uint64) uint64 {
|
|||
// s390x:"RISBGZ\t[$]0, [$]63, [$]8, "
|
||||
// ppc64:"ROTL\t[$]8"
|
||||
// ppc64le:"ROTL\t[$]8"
|
||||
// loong64: "ROTRV\t[$]56"
|
||||
a += x<<8 + x>>56
|
||||
|
||||
// amd64:"ROLQ\t[$]9"
|
||||
|
|
@ -32,6 +34,7 @@ func rot64(x uint64) uint64 {
|
|||
// s390x:"RISBGZ\t[$]0, [$]63, [$]9, "
|
||||
// ppc64:"ROTL\t[$]9"
|
||||
// ppc64le:"ROTL\t[$]9"
|
||||
// loong64: "ROTRV\t[$]55"
|
||||
a += x<<9 ^ x>>55
|
||||
|
||||
// amd64:"ROLQ\t[$]10"
|
||||
|
|
@ -41,6 +44,7 @@ func rot64(x uint64) uint64 {
|
|||
// ppc64le:"ROTL\t[$]10"
|
||||
// arm64:"ROR\t[$]54"
|
||||
// s390x:"RISBGZ\t[$]0, [$]63, [$]10, "
|
||||
// loong64: "ROTRV\t[$]54"
|
||||
a += bits.RotateLeft64(x, 10)
|
||||
|
||||
return a
|
||||
|
|
@ -53,6 +57,7 @@ func rot32(x uint32) uint32 {
|
|||
// arm:"MOVW\tR\\d+@>25"
|
||||
// ppc64:"ROTLW\t[$]7"
|
||||
// ppc64le:"ROTLW\t[$]7"
|
||||
// loong64: "ROTR\t[$]25"
|
||||
a += x<<7 | x>>25
|
||||
|
||||
// amd64:`ROLL\t[$]8`
|
||||
|
|
@ -61,6 +66,7 @@ func rot32(x uint32) uint32 {
|
|||
// s390x:"RLL\t[$]8"
|
||||
// ppc64:"ROTLW\t[$]8"
|
||||
// ppc64le:"ROTLW\t[$]8"
|
||||
// loong64: "ROTR\t[$]24"
|
||||
a += x<<8 + x>>24
|
||||
|
||||
// amd64:"ROLL\t[$]9"
|
||||
|
|
@ -69,6 +75,7 @@ func rot32(x uint32) uint32 {
|
|||
// s390x:"RLL\t[$]9"
|
||||
// ppc64:"ROTLW\t[$]9"
|
||||
// ppc64le:"ROTLW\t[$]9"
|
||||
// loong64: "ROTR\t[$]23"
|
||||
a += x<<9 ^ x>>23
|
||||
|
||||
// amd64:"ROLL\t[$]10"
|
||||
|
|
@ -79,6 +86,7 @@ func rot32(x uint32) uint32 {
|
|||
// ppc64le:"ROTLW\t[$]10"
|
||||
// arm64:"RORW\t[$]22"
|
||||
// s390x:"RLL\t[$]10"
|
||||
// loong64: "ROTR\t[$]22"
|
||||
a += bits.RotateLeft32(x, 10)
|
||||
|
||||
return a
|
||||
|
|
@ -127,12 +135,14 @@ func rot64nc(x uint64, z uint) uint64 {
|
|||
// arm64:"ROR","NEG",-"AND"
|
||||
// ppc64:"ROTL",-"NEG",-"AND"
|
||||
// ppc64le:"ROTL",-"NEG",-"AND"
|
||||
// loong64: "ROTRV", -"AND"
|
||||
a += x<<z | x>>(64-z)
|
||||
|
||||
// amd64:"RORQ",-"AND"
|
||||
// arm64:"ROR",-"NEG",-"AND"
|
||||
// ppc64:"ROTL","NEG",-"AND"
|
||||
// ppc64le:"ROTL","NEG",-"AND"
|
||||
// loong64: "ROTRV", -"AND"
|
||||
a += x>>z | x<<(64-z)
|
||||
|
||||
return a
|
||||
|
|
@ -147,12 +157,14 @@ func rot32nc(x uint32, z uint) uint32 {
|
|||
// arm64:"ROR","NEG",-"AND"
|
||||
// ppc64:"ROTLW",-"NEG",-"AND"
|
||||
// ppc64le:"ROTLW",-"NEG",-"AND"
|
||||
// loong64: "ROTR", -"AND"
|
||||
a += x<<z | x>>(32-z)
|
||||
|
||||
// amd64:"RORL",-"AND"
|
||||
// arm64:"ROR",-"NEG",-"AND"
|
||||
// ppc64:"ROTLW","NEG",-"AND"
|
||||
// ppc64le:"ROTLW","NEG",-"AND"
|
||||
// loong64: "ROTR", -"AND"
|
||||
a += x>>z | x<<(32-z)
|
||||
|
||||
return a
|
||||
|
|
|
|||
Loading…
Reference in a new issue