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internal/cpu: fix cpu cacheLineSize for arm64 darwin(a.k.a. M1)

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The existing value for M1 is 64, which is the same as other arm64 cpus.
But the correct cacheLineSize for M1 should be 128, which can be
verified using the following command:

$ sysctl -a hw | grep cachelinesize
hw.cachelinesize: 128

Fixes #53075
This commit is contained in:
Pure White 2022-05-26 00:13:59 +08:00
parent 0ab71cc065
commit df87eb9c50
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GPG key ID: 27B52F0C6D97F3FD
1 changed files with 4 additions and 1 deletions
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5
src/internal/cpu/cpu_arm64.go
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@ -4,7 +4,10 @@
package cpu
const CacheLinePadSize = 64
// CacheLinePadSize is used to prevent false sharing of cache lines.
// We choose 128 because Apple Silicon, a.k.a. M1, has 128-byte cache line size.
// It doesn't cost much and is much more future-proof.
const CacheLinePadSize = 128
func doinit() {
options = []option{