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cmd/compile: fix plan9-amd64 build
The previous rules to combine indexed loads produced addresses like:
From: obj.Addr{
Type: TYPE_MEM,
Reg: REG_CX,
Name: NAME_AUTO,
Offset: 121,
...
}
which are erroneous because NAME_AUTO implies a base register of
REG_SP, and cmd/internal/obj/x86 makes many assumptions to this
effect. Note that previously we were also producing an extra "ADDQ
SP, CX" instruction, so indexing off of SP was already handled.
The approach taken by this CL to address the problem is to instead
produce addresses like:
From: obj.Addr{
Type: TYPE_MEM,
Reg: REG_SP,
Name: NAME_AUTO,
Offset: 121,
Index: REG_CX,
Scale: 1,
}
and to omit the "ADDQ SP, CX" instruction.
Downside to this approach is it requires adding a lot of new
MOV[WLQ]loadidx1 instructions that nearly duplicate functionality of
the existing MOV[WLQ]loadidx[248] instructions, but with a different
Scale.
Fixes #15001.
Change-Id: Iad9a1a41e5e2552f8d22e3ba975e4ea0862dffd2
Reviewed-on: https://go-review.googlesource.com/21245
Run-TryBot: Matthew Dempsky <mdempsky@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Keith Randall <khr@golang.org>
This commit is contained in:
Matthew Dempsky
parent
859b63cc09
commit
da19a0cff4
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@ -694,6 +694,15 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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gc.AddAux(&p.From, v)
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p.To.Type = obj.TYPE_REG
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p.To.Reg = gc.SSARegNum(v)
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case ssa.OpAMD64MOVQloadidx1:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_MEM
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p.From.Reg = gc.SSARegNum(v.Args[0])
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gc.AddAux(&p.From, v)
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p.From.Scale = 1
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p.From.Index = gc.SSARegNum(v.Args[1])
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p.To.Type = obj.TYPE_REG
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p.To.Reg = gc.SSARegNum(v)
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case ssa.OpAMD64MOVQloadidx8, ssa.OpAMD64MOVSDloadidx8:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_MEM
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@ -703,6 +712,15 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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p.From.Index = gc.SSARegNum(v.Args[1])
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p.To.Type = obj.TYPE_REG
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p.To.Reg = gc.SSARegNum(v)
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case ssa.OpAMD64MOVLloadidx1:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_MEM
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p.From.Reg = gc.SSARegNum(v.Args[0])
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gc.AddAux(&p.From, v)
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p.From.Scale = 1
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p.From.Index = gc.SSARegNum(v.Args[1])
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p.To.Type = obj.TYPE_REG
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p.To.Reg = gc.SSARegNum(v)
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case ssa.OpAMD64MOVLloadidx4, ssa.OpAMD64MOVSSloadidx4:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_MEM
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@ -712,6 +730,15 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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p.From.Index = gc.SSARegNum(v.Args[1])
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p.To.Type = obj.TYPE_REG
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p.To.Reg = gc.SSARegNum(v)
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case ssa.OpAMD64MOVWloadidx1:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_MEM
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p.From.Reg = gc.SSARegNum(v.Args[0])
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gc.AddAux(&p.From, v)
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p.From.Scale = 1
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p.From.Index = gc.SSARegNum(v.Args[1])
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p.To.Type = obj.TYPE_REG
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p.To.Reg = gc.SSARegNum(v)
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case ssa.OpAMD64MOVWloadidx2:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_MEM
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@ -1262,13 +1262,13 @@
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(SHLQconst [56] (MOVBload [i+7] {s} p mem))) -> @x.Block (MOVQload [i] {s} p mem)
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(ORW x:(MOVBloadidx1 [i] {s} p idx mem)
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(SHLWconst [8] (MOVBloadidx1 [i+1] {s} p idx mem))) -> @x.Block (MOVWload [i] {s} (ADDQ <p.Type> p idx) mem)
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(SHLWconst [8] (MOVBloadidx1 [i+1] {s} p idx mem))) -> @x.Block (MOVWloadidx1 <v.Type> [i] {s} p idx mem)
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(ORL (ORL (ORL
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x:(MOVBloadidx1 [i] {s} p idx mem)
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(SHLLconst [8] (MOVBloadidx1 [i+1] {s} p idx mem)))
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(SHLLconst [16] (MOVBloadidx1 [i+2] {s} p idx mem)))
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(SHLLconst [24] (MOVBloadidx1 [i+3] {s} p idx mem))) -> @x.Block (MOVLload [i] {s} (ADDQ <p.Type> p idx) mem)
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(SHLLconst [24] (MOVBloadidx1 [i+3] {s} p idx mem))) -> @x.Block (MOVLloadidx1 <v.Type> [i] {s} p idx mem)
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(ORQ (ORQ (ORQ (ORQ (ORQ (ORQ (ORQ
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x:(MOVBloadidx1 [i] {s} p idx mem)
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@ -1278,4 +1278,4 @@
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(SHLQconst [32] (MOVBloadidx1 [i+4] {s} p idx mem)))
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(SHLQconst [40] (MOVBloadidx1 [i+5] {s} p idx mem)))
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(SHLQconst [48] (MOVBloadidx1 [i+6] {s} p idx mem)))
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(SHLQconst [56] (MOVBloadidx1 [i+7] {s} p idx mem))) -> @x.Block (MOVQload [i] {s} (ADDQ <p.Type> p idx) mem)
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(SHLQconst [56] (MOVBloadidx1 [i+7] {s} p idx mem))) -> @x.Block (MOVQloadidx1 <v.Type> [i] {s} p idx mem)
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@ -406,8 +406,11 @@ func init() {
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// indexed loads/stores
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{name: "MOVBloadidx1", argLength: 3, reg: gploadidx, asm: "MOVBLZX", aux: "SymOff"}, // load a byte from arg0+arg1+auxint+aux. arg2=mem
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{name: "MOVWloadidx1", argLength: 3, reg: gploadidx, asm: "MOVWLZX", aux: "SymOff"}, // load 2 bytes from arg0+arg1+auxint+aux. arg2=mem
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{name: "MOVWloadidx2", argLength: 3, reg: gploadidx, asm: "MOVWLZX", aux: "SymOff"}, // load 2 bytes from arg0+2*arg1+auxint+aux. arg2=mem
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{name: "MOVLloadidx1", argLength: 3, reg: gploadidx, asm: "MOVL", aux: "SymOff"}, // load 4 bytes from arg0+arg1+auxint+aux. arg2=mem
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{name: "MOVLloadidx4", argLength: 3, reg: gploadidx, asm: "MOVL", aux: "SymOff"}, // load 4 bytes from arg0+4*arg1+auxint+aux. arg2=mem
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{name: "MOVQloadidx1", argLength: 3, reg: gploadidx, asm: "MOVQ", aux: "SymOff"}, // load 8 bytes from arg0+arg1+auxint+aux. arg2=mem
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{name: "MOVQloadidx8", argLength: 3, reg: gploadidx, asm: "MOVQ", aux: "SymOff"}, // load 8 bytes from arg0+8*arg1+auxint+aux. arg2=mem
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// TODO: sign-extending indexed loads
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{name: "MOVBstoreidx1", argLength: 4, reg: gpstoreidx, asm: "MOVB", aux: "SymOff"}, // store byte in arg2 to arg0+arg1+auxint+aux. arg3=mem
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@ -310,8 +310,11 @@ const (
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OpAMD64MOVOload
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OpAMD64MOVOstore
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OpAMD64MOVBloadidx1
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OpAMD64MOVWloadidx1
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OpAMD64MOVWloadidx2
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OpAMD64MOVLloadidx1
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OpAMD64MOVLloadidx4
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OpAMD64MOVQloadidx1
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OpAMD64MOVQloadidx8
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OpAMD64MOVBstoreidx1
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OpAMD64MOVWstoreidx2
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@ -3819,6 +3822,21 @@ var opcodeTable = [...]opInfo{
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},
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},
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},
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{
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name: "MOVWloadidx1",
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auxType: auxSymOff,
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argLen: 3,
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asm: x86.AMOVWLZX,
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reg: regInfo{
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inputs: []inputInfo{
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{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
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},
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outputs: []regMask{
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65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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},
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},
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},
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{
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name: "MOVWloadidx2",
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auxType: auxSymOff,
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@ -3834,6 +3852,21 @@ var opcodeTable = [...]opInfo{
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},
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},
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},
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{
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name: "MOVLloadidx1",
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auxType: auxSymOff,
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argLen: 3,
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asm: x86.AMOVL,
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reg: regInfo{
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inputs: []inputInfo{
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{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
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},
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outputs: []regMask{
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65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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},
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},
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},
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{
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name: "MOVLloadidx4",
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auxType: auxSymOff,
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@ -3849,6 +3882,21 @@ var opcodeTable = [...]opInfo{
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},
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},
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},
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{
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name: "MOVQloadidx1",
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auxType: auxSymOff,
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argLen: 3,
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asm: x86.AMOVQ,
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reg: regInfo{
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inputs: []inputInfo{
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{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
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},
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outputs: []regMask{
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65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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},
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},
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},
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{
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name: "MOVQloadidx8",
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auxType: auxSymOff,
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@ -10670,7 +10670,7 @@ func rewriteValueAMD64_OpAMD64ORL(v *Value, config *Config) bool {
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}
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// match: (ORL (ORL (ORL x:(MOVBloadidx1 [i] {s} p idx mem) (SHLLconst [8] (MOVBloadidx1 [i+1] {s} p idx mem))) (SHLLconst [16] (MOVBloadidx1 [i+2] {s} p idx mem))) (SHLLconst [24] (MOVBloadidx1 [i+3] {s} p idx mem)))
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// cond:
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// result: @x.Block (MOVLload [i] {s} (ADDQ <p.Type> p idx) mem)
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// result: @x.Block (MOVLloadidx1 <v.Type> [i] {s} p idx mem)
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for {
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v_0 := v.Args[0]
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if v_0.Op != OpAMD64ORL {
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@ -10768,15 +10768,13 @@ func rewriteValueAMD64_OpAMD64ORL(v *Value, config *Config) bool {
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break
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}
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b = x.Block
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v0 := b.NewValue0(v.Line, OpAMD64MOVLload, config.fe.TypeUInt32())
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v0 := b.NewValue0(v.Line, OpAMD64MOVLloadidx1, v.Type)
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v.reset(OpCopy)
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v.AddArg(v0)
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v0.AuxInt = i
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v0.Aux = s
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v1 := b.NewValue0(v.Line, OpAMD64ADDQ, p.Type)
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v1.AddArg(p)
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v1.AddArg(idx)
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v0.AddArg(v1)
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v0.AddArg(p)
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v0.AddArg(idx)
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v0.AddArg(mem)
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return true
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}
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@ -11088,7 +11086,7 @@ func rewriteValueAMD64_OpAMD64ORQ(v *Value, config *Config) bool {
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}
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// match: (ORQ (ORQ (ORQ (ORQ (ORQ (ORQ (ORQ x:(MOVBloadidx1 [i] {s} p idx mem) (SHLQconst [8] (MOVBloadidx1 [i+1] {s} p idx mem))) (SHLQconst [16] (MOVBloadidx1 [i+2] {s} p idx mem))) (SHLQconst [24] (MOVBloadidx1 [i+3] {s} p idx mem))) (SHLQconst [32] (MOVBloadidx1 [i+4] {s} p idx mem))) (SHLQconst [40] (MOVBloadidx1 [i+5] {s} p idx mem))) (SHLQconst [48] (MOVBloadidx1 [i+6] {s} p idx mem))) (SHLQconst [56] (MOVBloadidx1 [i+7] {s} p idx mem)))
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// cond:
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// result: @x.Block (MOVQload [i] {s} (ADDQ <p.Type> p idx) mem)
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// result: @x.Block (MOVQloadidx1 <v.Type> [i] {s} p idx mem)
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for {
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v_0 := v.Args[0]
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if v_0.Op != OpAMD64ORQ {
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@ -11306,15 +11304,13 @@ func rewriteValueAMD64_OpAMD64ORQ(v *Value, config *Config) bool {
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break
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}
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b = x.Block
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v0 := b.NewValue0(v.Line, OpAMD64MOVQload, config.fe.TypeUInt64())
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v0 := b.NewValue0(v.Line, OpAMD64MOVQloadidx1, v.Type)
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v.reset(OpCopy)
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v.AddArg(v0)
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v0.AuxInt = i
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v0.Aux = s
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v1 := b.NewValue0(v.Line, OpAMD64ADDQ, p.Type)
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v1.AddArg(p)
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v1.AddArg(idx)
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v0.AddArg(v1)
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v0.AddArg(p)
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v0.AddArg(idx)
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v0.AddArg(mem)
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return true
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}
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@ -11456,7 +11452,7 @@ func rewriteValueAMD64_OpAMD64ORW(v *Value, config *Config) bool {
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}
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// match: (ORW x:(MOVBloadidx1 [i] {s} p idx mem) (SHLWconst [8] (MOVBloadidx1 [i+1] {s} p idx mem)))
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// cond:
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// result: @x.Block (MOVWload [i] {s} (ADDQ <p.Type> p idx) mem)
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// result: @x.Block (MOVWloadidx1 <v.Type> [i] {s} p idx mem)
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for {
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x := v.Args[0]
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if x.Op != OpAMD64MOVBloadidx1 {
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@ -11494,15 +11490,13 @@ func rewriteValueAMD64_OpAMD64ORW(v *Value, config *Config) bool {
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break
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}
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b = x.Block
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v0 := b.NewValue0(v.Line, OpAMD64MOVWload, config.fe.TypeUInt16())
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v0 := b.NewValue0(v.Line, OpAMD64MOVWloadidx1, v.Type)
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v.reset(OpCopy)
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v.AddArg(v0)
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v0.AuxInt = i
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v0.Aux = s
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v1 := b.NewValue0(v.Line, OpAMD64ADDQ, p.Type)
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v1.AddArg(p)
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v1.AddArg(idx)
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v0.AddArg(v1)
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v0.AddArg(p)
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v0.AddArg(idx)
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v0.AddArg(mem)
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return true
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}
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