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cmd/compile: fix unaligned loads/stores to global variables on s390x
Load/store-merging and move optimizations can result in unaligned memory accesses. This is fine so long as the load/store instruction used does not take a relative offset. In the SSA rules this means we must not merge (MOVDaddr (SB)) ops into loads/stores unless we can guarantee the alignment of the target. Fixes #21048. Change-Id: I70f13a62a148d5f0a56e704e8f76e36b4a4226d9 Reviewed-on: https://go-review.googlesource.com/49250 Run-TryBot: Michael Munday <mike.munday@ibm.com> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: Cherry Zhang <cherryyz@google.com>
This commit is contained in:
parent
83fb9c8d9f
commit
93b7eb973f
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@ -737,13 +737,15 @@
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(MOVBstoreconst [sc] {s} (ADDconst [off] ptr) mem) && is20Bit(ValAndOff(sc).Off()+off) ->
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(MOVBstoreconst [ValAndOff(sc).add(off)] {s} ptr mem)
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// We need to fold MOVDaddr into the MOVx ops so that the live variable analysis knows
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// what variables are being read/written by the ops.
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(MOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
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// Merge address calculations into loads and stores.
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// Offsets from SB must not be merged into unaligned memory accesses because
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// loads/stores using PC-relative addressing directly must be aligned to the
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// size of the target.
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(MOVDload [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.ElemType().Alignment()%8 == 0 && (off1+off2)%8 == 0)) ->
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(MOVDload [off1+off2] {mergeSym(sym1,sym2)} base mem)
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(MOVWZload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
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(MOVWZload [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.ElemType().Alignment()%4 == 0 && (off1+off2)%4 == 0)) ->
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(MOVWZload [off1+off2] {mergeSym(sym1,sym2)} base mem)
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(MOVHZload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
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(MOVHZload [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.ElemType().Alignment()%2 == 0 && (off1+off2)%2 == 0)) ->
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(MOVHZload [off1+off2] {mergeSym(sym1,sym2)} base mem)
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(MOVBZload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
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(MOVBZload [off1+off2] {mergeSym(sym1,sym2)} base mem)
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@ -752,18 +754,18 @@
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(FMOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
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(FMOVDload [off1+off2] {mergeSym(sym1,sym2)} base mem)
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(MOVWload [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.ElemType().Alignment()%4 == 0 && (off1+off2)%4 == 0)) ->
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(MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem)
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(MOVHload [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.ElemType().Alignment()%2 == 0 && (off1+off2)%2 == 0)) ->
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(MOVHload [off1+off2] {mergeSym(sym1,sym2)} base mem)
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(MOVBload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
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(MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem)
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(MOVHload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
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(MOVHload [off1+off2] {mergeSym(sym1,sym2)} base mem)
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(MOVWload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
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(MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem)
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(MOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
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(MOVDstore [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.ElemType().Alignment()%8 == 0 && (off1+off2)%8 == 0)) ->
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(MOVDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem)
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(MOVWstore [off1] {sym1} (MOVDaddr [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
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(MOVWstore [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.ElemType().Alignment()%4 == 0 && (off1+off2)%4 == 0)) ->
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(MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem)
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(MOVHstore [off1] {sym1} (MOVDaddr [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
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(MOVHstore [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.ElemType().Alignment()%2 == 0 && (off1+off2)%2 == 0)) ->
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(MOVHstore [off1+off2] {mergeSym(sym1,sym2)} base val mem)
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(MOVBstore [off1] {sym1} (MOVDaddr [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
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(MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem)
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@ -12377,8 +12377,8 @@ func rewriteValueS390X_OpS390XMOVDload_0(v *Value) bool {
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v.AddArg(mem)
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return true
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}
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// match: (MOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem)
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// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
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// match: (MOVDload [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) mem)
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// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.ElemType().Alignment()%8 == 0 && (off1+off2)%8 == 0))
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// result: (MOVDload [off1+off2] {mergeSym(sym1,sym2)} base mem)
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for {
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off1 := v.AuxInt
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@ -12388,11 +12388,12 @@ func rewriteValueS390X_OpS390XMOVDload_0(v *Value) bool {
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if v_0.Op != OpS390XMOVDaddr {
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break
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}
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t := v_0.Type
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off2 := v_0.AuxInt
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sym2 := v_0.Aux
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base := v_0.Args[0]
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mem := v.Args[1]
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if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
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if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.ElemType().Alignment()%8 == 0 && (off1+off2)%8 == 0))) {
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break
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}
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v.reset(OpS390XMOVDload)
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@ -13300,8 +13301,8 @@ func rewriteValueS390X_OpS390XMOVDstore_0(v *Value) bool {
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v.AddArg(mem)
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return true
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}
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// match: (MOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} base) val mem)
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// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
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// match: (MOVDstore [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) val mem)
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// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.ElemType().Alignment()%8 == 0 && (off1+off2)%8 == 0))
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// result: (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem)
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for {
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off1 := v.AuxInt
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@ -13311,12 +13312,13 @@ func rewriteValueS390X_OpS390XMOVDstore_0(v *Value) bool {
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if v_0.Op != OpS390XMOVDaddr {
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break
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}
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t := v_0.Type
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off2 := v_0.AuxInt
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sym2 := v_0.Aux
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base := v_0.Args[0]
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val := v.Args[1]
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mem := v.Args[2]
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if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
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if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.ElemType().Alignment()%8 == 0 && (off1+off2)%8 == 0))) {
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break
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}
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v.reset(OpS390XMOVDstore)
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@ -14747,8 +14749,8 @@ func rewriteValueS390X_OpS390XMOVHZload_0(v *Value) bool {
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v.AddArg(mem)
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return true
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}
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// match: (MOVHZload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem)
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// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
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// match: (MOVHZload [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) mem)
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// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.ElemType().Alignment()%2 == 0 && (off1+off2)%2 == 0))
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// result: (MOVHZload [off1+off2] {mergeSym(sym1,sym2)} base mem)
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for {
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off1 := v.AuxInt
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@ -14758,11 +14760,12 @@ func rewriteValueS390X_OpS390XMOVHZload_0(v *Value) bool {
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if v_0.Op != OpS390XMOVDaddr {
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break
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}
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t := v_0.Type
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off2 := v_0.AuxInt
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sym2 := v_0.Aux
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base := v_0.Args[0]
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mem := v.Args[1]
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if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
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if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.ElemType().Alignment()%2 == 0 && (off1+off2)%2 == 0))) {
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break
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}
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v.reset(OpS390XMOVHZload)
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@ -15086,8 +15089,8 @@ func rewriteValueS390X_OpS390XMOVHload_0(v *Value) bool {
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v.AddArg(mem)
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return true
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}
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// match: (MOVHload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem)
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// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
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// match: (MOVHload [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) mem)
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// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.ElemType().Alignment()%2 == 0 && (off1+off2)%2 == 0))
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// result: (MOVHload [off1+off2] {mergeSym(sym1,sym2)} base mem)
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for {
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off1 := v.AuxInt
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@ -15097,11 +15100,12 @@ func rewriteValueS390X_OpS390XMOVHload_0(v *Value) bool {
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if v_0.Op != OpS390XMOVDaddr {
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break
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}
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t := v_0.Type
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off2 := v_0.AuxInt
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sym2 := v_0.Aux
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base := v_0.Args[0]
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mem := v.Args[1]
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if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
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if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.ElemType().Alignment()%2 == 0 && (off1+off2)%2 == 0))) {
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break
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}
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v.reset(OpS390XMOVHload)
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@ -15343,8 +15347,8 @@ func rewriteValueS390X_OpS390XMOVHstore_0(v *Value) bool {
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v.AddArg(mem)
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return true
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}
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// match: (MOVHstore [off1] {sym1} (MOVDaddr [off2] {sym2} base) val mem)
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// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
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// match: (MOVHstore [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) val mem)
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// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.ElemType().Alignment()%2 == 0 && (off1+off2)%2 == 0))
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// result: (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} base val mem)
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for {
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off1 := v.AuxInt
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@ -15354,12 +15358,13 @@ func rewriteValueS390X_OpS390XMOVHstore_0(v *Value) bool {
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if v_0.Op != OpS390XMOVDaddr {
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break
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}
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t := v_0.Type
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off2 := v_0.AuxInt
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sym2 := v_0.Aux
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base := v_0.Args[0]
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val := v.Args[1]
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mem := v.Args[2]
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if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
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if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.ElemType().Alignment()%2 == 0 && (off1+off2)%2 == 0))) {
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break
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}
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v.reset(OpS390XMOVHstore)
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@ -17229,8 +17234,8 @@ func rewriteValueS390X_OpS390XMOVWZload_0(v *Value) bool {
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v.AddArg(mem)
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return true
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}
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// match: (MOVWZload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem)
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// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
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// match: (MOVWZload [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) mem)
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// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.ElemType().Alignment()%4 == 0 && (off1+off2)%4 == 0))
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// result: (MOVWZload [off1+off2] {mergeSym(sym1,sym2)} base mem)
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for {
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off1 := v.AuxInt
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@ -17240,11 +17245,12 @@ func rewriteValueS390X_OpS390XMOVWZload_0(v *Value) bool {
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if v_0.Op != OpS390XMOVDaddr {
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break
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}
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t := v_0.Type
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off2 := v_0.AuxInt
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sym2 := v_0.Aux
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base := v_0.Args[0]
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mem := v.Args[1]
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if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
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if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.ElemType().Alignment()%4 == 0 && (off1+off2)%4 == 0))) {
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break
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}
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v.reset(OpS390XMOVWZload)
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@ -17593,8 +17599,8 @@ func rewriteValueS390X_OpS390XMOVWload_0(v *Value) bool {
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v.AddArg(mem)
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return true
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}
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// match: (MOVWload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem)
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// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
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// match: (MOVWload [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) mem)
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// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.ElemType().Alignment()%4 == 0 && (off1+off2)%4 == 0))
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// result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem)
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for {
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off1 := v.AuxInt
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@ -17604,11 +17610,12 @@ func rewriteValueS390X_OpS390XMOVWload_0(v *Value) bool {
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if v_0.Op != OpS390XMOVDaddr {
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break
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}
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t := v_0.Type
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off2 := v_0.AuxInt
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sym2 := v_0.Aux
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base := v_0.Args[0]
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mem := v.Args[1]
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if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
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if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.ElemType().Alignment()%4 == 0 && (off1+off2)%4 == 0))) {
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break
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}
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v.reset(OpS390XMOVWload)
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@ -17903,8 +17910,8 @@ func rewriteValueS390X_OpS390XMOVWstore_0(v *Value) bool {
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v.AddArg(mem)
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return true
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}
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// match: (MOVWstore [off1] {sym1} (MOVDaddr [off2] {sym2} base) val mem)
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// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
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// match: (MOVWstore [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) val mem)
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// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.ElemType().Alignment()%4 == 0 && (off1+off2)%4 == 0))
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// result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem)
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for {
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off1 := v.AuxInt
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@ -17914,12 +17921,13 @@ func rewriteValueS390X_OpS390XMOVWstore_0(v *Value) bool {
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if v_0.Op != OpS390XMOVDaddr {
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break
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}
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t := v_0.Type
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off2 := v_0.AuxInt
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sym2 := v_0.Aux
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base := v_0.Args[0]
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val := v.Args[1]
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mem := v.Args[2]
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if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
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if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.ElemType().Alignment()%4 == 0 && (off1+off2)%4 == 0))) {
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break
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}
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v.reset(OpS390XMOVWstore)
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72
test/fixedbugs/issue21048.go
Normal file
72
test/fixedbugs/issue21048.go
Normal file
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@ -0,0 +1,72 @@
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// run
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// Copyright 2017 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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// Issue 21048: s390x merged address generation into stores
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// to unaligned global variables. This resulted in an illegal
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// instruction.
|
||||
|
||||
package main
|
||||
|
||||
type T struct {
|
||||
_ [1]byte
|
||||
a [2]byte // offset: 1
|
||||
_ [3]byte
|
||||
b [2]uint16 // offset: 6
|
||||
_ [2]byte
|
||||
c [2]uint32 // offset: 12
|
||||
_ [2]byte
|
||||
d [2]int16 // offset: 22
|
||||
_ [2]byte
|
||||
e [2]int32 // offset: 28
|
||||
}
|
||||
|
||||
var Source, Sink T
|
||||
|
||||
func newT() T {
|
||||
return T{
|
||||
a: [2]byte{1, 2},
|
||||
b: [2]uint16{1, 2},
|
||||
c: [2]uint32{1, 2},
|
||||
d: [2]int16{1, 2},
|
||||
e: [2]int32{1, 2},
|
||||
}
|
||||
}
|
||||
|
||||
//go:noinline
|
||||
func moves() {
|
||||
Sink.a = Source.a
|
||||
Sink.b = Source.b
|
||||
Sink.c = Source.c
|
||||
Sink.d = Source.d
|
||||
Sink.e = Source.e
|
||||
}
|
||||
|
||||
//go:noinline
|
||||
func loads() *T {
|
||||
t := newT()
|
||||
t.a = Source.a
|
||||
t.b = Source.b
|
||||
t.c = Source.c
|
||||
t.d = Source.d
|
||||
t.e = Source.e
|
||||
return &t
|
||||
}
|
||||
|
||||
//go:noinline
|
||||
func stores() {
|
||||
t := newT()
|
||||
Sink.a = t.a
|
||||
Sink.b = t.b
|
||||
Sink.c = t.c
|
||||
Sink.d = t.d
|
||||
Sink.e = t.e
|
||||
}
|
||||
|
||||
func main() {
|
||||
moves()
|
||||
loads()
|
||||
stores()
|
||||
}
|
Loading…
Reference in a new issue