|
|
|
@ -436,3 +436,271 @@
|
|
|
|
|
// Absorb boolean tests into block
|
|
|
|
|
(NE (FPFlagTrue cmp) yes no) -> (FPT cmp yes no)
|
|
|
|
|
(NE (FPFlagFalse cmp) yes no) -> (FPF cmp yes no)
|
|
|
|
|
(EQ (FPFlagTrue cmp) yes no) -> (FPF cmp yes no)
|
|
|
|
|
(EQ (FPFlagFalse cmp) yes no) -> (FPT cmp yes no)
|
|
|
|
|
(NE (XORconst [1] cmp:(SGT _ _)) yes no) -> (EQ cmp yes no)
|
|
|
|
|
(NE (XORconst [1] cmp:(SGTU _ _)) yes no) -> (EQ cmp yes no)
|
|
|
|
|
(NE (XORconst [1] cmp:(SGTconst _)) yes no) -> (EQ cmp yes no)
|
|
|
|
|
(NE (XORconst [1] cmp:(SGTUconst _)) yes no) -> (EQ cmp yes no)
|
|
|
|
|
(EQ (XORconst [1] cmp:(SGT _ _)) yes no) -> (NE cmp yes no)
|
|
|
|
|
(EQ (XORconst [1] cmp:(SGTU _ _)) yes no) -> (NE cmp yes no)
|
|
|
|
|
(EQ (XORconst [1] cmp:(SGTconst _)) yes no) -> (NE cmp yes no)
|
|
|
|
|
(EQ (XORconst [1] cmp:(SGTUconst _)) yes no) -> (NE cmp yes no)
|
|
|
|
|
(NE (SGTUconst [1] x) yes no) -> (EQ x yes no)
|
|
|
|
|
(EQ (SGTUconst [1] x) yes no) -> (NE x yes no)
|
|
|
|
|
(NE (SGTU x (MOVVconst [0])) yes no) -> (NE x yes no)
|
|
|
|
|
(EQ (SGTU x (MOVVconst [0])) yes no) -> (EQ x yes no)
|
|
|
|
|
(NE (SGTconst [0] x) yes no) -> (LTZ x yes no)
|
|
|
|
|
(EQ (SGTconst [0] x) yes no) -> (GEZ x yes no)
|
|
|
|
|
(NE (SGT x (MOVVconst [0])) yes no) -> (GTZ x yes no)
|
|
|
|
|
(EQ (SGT x (MOVVconst [0])) yes no) -> (LEZ x yes no)
|
|
|
|
|
|
|
|
|
|
// fold offset into address
|
|
|
|
|
(ADDVconst [off1] (MOVVaddr [off2] {sym} ptr)) -> (MOVVaddr [off1+off2] {sym} ptr)
|
|
|
|
|
|
|
|
|
|
// fold address into load/store
|
|
|
|
|
(MOVBload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVBload [off1+off2] {sym} ptr mem)
|
|
|
|
|
(MOVBUload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVBUload [off1+off2] {sym} ptr mem)
|
|
|
|
|
(MOVHload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVHload [off1+off2] {sym} ptr mem)
|
|
|
|
|
(MOVHUload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVHUload [off1+off2] {sym} ptr mem)
|
|
|
|
|
(MOVWload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVWload [off1+off2] {sym} ptr mem)
|
|
|
|
|
(MOVWUload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVWUload [off1+off2] {sym} ptr mem)
|
|
|
|
|
(MOVVload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVVload [off1+off2] {sym} ptr mem)
|
|
|
|
|
(MOVFload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVFload [off1+off2] {sym} ptr mem)
|
|
|
|
|
(MOVDload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVDload [off1+off2] {sym} ptr mem)
|
|
|
|
|
|
|
|
|
|
(MOVBstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVBstore [off1+off2] {sym} ptr val mem)
|
|
|
|
|
(MOVHstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVHstore [off1+off2] {sym} ptr val mem)
|
|
|
|
|
(MOVWstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVWstore [off1+off2] {sym} ptr val mem)
|
|
|
|
|
(MOVVstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVVstore [off1+off2] {sym} ptr val mem)
|
|
|
|
|
(MOVFstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVFstore [off1+off2] {sym} ptr val mem)
|
|
|
|
|
(MOVDstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVDstore [off1+off2] {sym} ptr val mem)
|
|
|
|
|
(MOVBstorezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVBstorezero [off1+off2] {sym} ptr mem)
|
|
|
|
|
(MOVHstorezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVHstorezero [off1+off2] {sym} ptr mem)
|
|
|
|
|
(MOVWstorezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVWstorezero [off1+off2] {sym} ptr mem)
|
|
|
|
|
(MOVVstorezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVVstorezero [off1+off2] {sym} ptr mem)
|
|
|
|
|
|
|
|
|
|
(MOVBload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
|
|
|
|
|
(MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
|
|
|
|
|
(MOVBUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
|
|
|
|
|
(MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
|
|
|
|
|
(MOVHload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
|
|
|
|
|
(MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
|
|
|
|
|
(MOVHUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
|
|
|
|
|
(MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
|
|
|
|
|
(MOVWload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
|
|
|
|
|
(MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
|
|
|
|
|
(MOVWUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
|
|
|
|
|
(MOVWUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
|
|
|
|
|
(MOVVload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
|
|
|
|
|
(MOVVload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
|
|
|
|
|
(MOVFload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
|
|
|
|
|
(MOVFload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
|
|
|
|
|
(MOVDload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
|
|
|
|
|
(MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
|
|
|
|
|
|
|
|
|
|
(MOVBstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
|
|
|
|
|
(MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
|
|
|
|
|
(MOVHstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
|
|
|
|
|
(MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
|
|
|
|
|
(MOVWstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
|
|
|
|
|
(MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
|
|
|
|
|
(MOVVstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
|
|
|
|
|
(MOVVstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
|
|
|
|
|
(MOVFstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
|
|
|
|
|
(MOVFstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
|
|
|
|
|
(MOVDstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
|
|
|
|
|
(MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
|
|
|
|
|
(MOVBstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
|
|
|
|
|
(MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
|
|
|
|
|
(MOVHstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
|
|
|
|
|
(MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
|
|
|
|
|
(MOVWstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
|
|
|
|
|
(MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
|
|
|
|
|
(MOVVstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) ->
|
|
|
|
|
(MOVVstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
|
|
|
|
|
|
|
|
|
|
// store zero
|
|
|
|
|
(MOVBstore [off] {sym} ptr (MOVVconst [0]) mem) -> (MOVBstorezero [off] {sym} ptr mem)
|
|
|
|
|
(MOVHstore [off] {sym} ptr (MOVVconst [0]) mem) -> (MOVHstorezero [off] {sym} ptr mem)
|
|
|
|
|
(MOVWstore [off] {sym} ptr (MOVVconst [0]) mem) -> (MOVWstorezero [off] {sym} ptr mem)
|
|
|
|
|
(MOVVstore [off] {sym} ptr (MOVVconst [0]) mem) -> (MOVVstorezero [off] {sym} ptr mem)
|
|
|
|
|
|
|
|
|
|
// don't extend after proper load
|
|
|
|
|
(MOVBreg x:(MOVBload _ _)) -> (MOVVreg x)
|
|
|
|
|
(MOVBUreg x:(MOVBUload _ _)) -> (MOVVreg x)
|
|
|
|
|
(MOVHreg x:(MOVBload _ _)) -> (MOVVreg x)
|
|
|
|
|
(MOVHreg x:(MOVBUload _ _)) -> (MOVVreg x)
|
|
|
|
|
(MOVHreg x:(MOVHload _ _)) -> (MOVVreg x)
|
|
|
|
|
(MOVHUreg x:(MOVBUload _ _)) -> (MOVVreg x)
|
|
|
|
|
(MOVHUreg x:(MOVHUload _ _)) -> (MOVVreg x)
|
|
|
|
|
(MOVWreg x:(MOVBload _ _)) -> (MOVVreg x)
|
|
|
|
|
(MOVWreg x:(MOVBUload _ _)) -> (MOVVreg x)
|
|
|
|
|
(MOVWreg x:(MOVHload _ _)) -> (MOVVreg x)
|
|
|
|
|
(MOVWreg x:(MOVHUload _ _)) -> (MOVVreg x)
|
|
|
|
|
(MOVWreg x:(MOVWload _ _)) -> (MOVVreg x)
|
|
|
|
|
(MOVWUreg x:(MOVBUload _ _)) -> (MOVVreg x)
|
|
|
|
|
(MOVWUreg x:(MOVHUload _ _)) -> (MOVVreg x)
|
|
|
|
|
(MOVWUreg x:(MOVWUload _ _)) -> (MOVVreg x)
|
|
|
|
|
|
|
|
|
|
// fold double extensions
|
|
|
|
|
(MOVBreg x:(MOVBreg _)) -> (MOVVreg x)
|
|
|
|
|
(MOVBUreg x:(MOVBUreg _)) -> (MOVVreg x)
|
|
|
|
|
(MOVHreg x:(MOVBreg _)) -> (MOVVreg x)
|
|
|
|
|
(MOVHreg x:(MOVBUreg _)) -> (MOVVreg x)
|
|
|
|
|
(MOVHreg x:(MOVHreg _)) -> (MOVVreg x)
|
|
|
|
|
(MOVHUreg x:(MOVBUreg _)) -> (MOVVreg x)
|
|
|
|
|
(MOVHUreg x:(MOVHUreg _)) -> (MOVVreg x)
|
|
|
|
|
(MOVWreg x:(MOVBreg _)) -> (MOVVreg x)
|
|
|
|
|
(MOVWreg x:(MOVBUreg _)) -> (MOVVreg x)
|
|
|
|
|
(MOVWreg x:(MOVHreg _)) -> (MOVVreg x)
|
|
|
|
|
(MOVWreg x:(MOVHreg _)) -> (MOVVreg x)
|
|
|
|
|
(MOVWreg x:(MOVWreg _)) -> (MOVVreg x)
|
|
|
|
|
(MOVWUreg x:(MOVBUreg _)) -> (MOVVreg x)
|
|
|
|
|
(MOVWUreg x:(MOVHUreg _)) -> (MOVVreg x)
|
|
|
|
|
(MOVWUreg x:(MOVWUreg _)) -> (MOVVreg x)
|
|
|
|
|
|
|
|
|
|
// don't extend before store
|
|
|
|
|
(MOVBstore [off] {sym} ptr (MOVBreg x) mem) -> (MOVBstore [off] {sym} ptr x mem)
|
|
|
|
|
(MOVBstore [off] {sym} ptr (MOVBUreg x) mem) -> (MOVBstore [off] {sym} ptr x mem)
|
|
|
|
|
(MOVBstore [off] {sym} ptr (MOVHreg x) mem) -> (MOVBstore [off] {sym} ptr x mem)
|
|
|
|
|
(MOVBstore [off] {sym} ptr (MOVHUreg x) mem) -> (MOVBstore [off] {sym} ptr x mem)
|
|
|
|
|
(MOVBstore [off] {sym} ptr (MOVWreg x) mem) -> (MOVBstore [off] {sym} ptr x mem)
|
|
|
|
|
(MOVBstore [off] {sym} ptr (MOVWUreg x) mem) -> (MOVBstore [off] {sym} ptr x mem)
|
|
|
|
|
(MOVHstore [off] {sym} ptr (MOVHreg x) mem) -> (MOVHstore [off] {sym} ptr x mem)
|
|
|
|
|
(MOVHstore [off] {sym} ptr (MOVHUreg x) mem) -> (MOVHstore [off] {sym} ptr x mem)
|
|
|
|
|
(MOVHstore [off] {sym} ptr (MOVWreg x) mem) -> (MOVHstore [off] {sym} ptr x mem)
|
|
|
|
|
(MOVHstore [off] {sym} ptr (MOVWUreg x) mem) -> (MOVHstore [off] {sym} ptr x mem)
|
|
|
|
|
(MOVWstore [off] {sym} ptr (MOVWreg x) mem) -> (MOVWstore [off] {sym} ptr x mem)
|
|
|
|
|
(MOVWstore [off] {sym} ptr (MOVWUreg x) mem) -> (MOVWstore [off] {sym} ptr x mem)
|
|
|
|
|
|
|
|
|
|
// if a register move has only 1 use, just use the same register without emitting instruction
|
|
|
|
|
// MOVVnop doesn't emit instruction, only for ensuring the type.
|
|
|
|
|
(MOVVreg x) && x.Uses == 1 -> (MOVVnop x)
|
|
|
|
|
|
|
|
|
|
// fold constant into arithmatic ops
|
|
|
|
|
(ADDV (MOVVconst [c]) x) && is32Bit(c) -> (ADDVconst [c] x)
|
|
|
|
|
(ADDV x (MOVVconst [c])) && is32Bit(c) -> (ADDVconst [c] x)
|
|
|
|
|
(SUBV x (MOVVconst [c])) && is32Bit(c) -> (SUBVconst [c] x)
|
|
|
|
|
(AND (MOVVconst [c]) x) && is32Bit(c) -> (ANDconst [c] x)
|
|
|
|
|
(AND x (MOVVconst [c])) && is32Bit(c) -> (ANDconst [c] x)
|
|
|
|
|
(OR (MOVVconst [c]) x) && is32Bit(c) -> (ORconst [c] x)
|
|
|
|
|
(OR x (MOVVconst [c])) && is32Bit(c) -> (ORconst [c] x)
|
|
|
|
|
(XOR (MOVVconst [c]) x) && is32Bit(c) -> (XORconst [c] x)
|
|
|
|
|
(XOR x (MOVVconst [c])) && is32Bit(c) -> (XORconst [c] x)
|
|
|
|
|
(NOR (MOVVconst [c]) x) && is32Bit(c) -> (NORconst [c] x)
|
|
|
|
|
(NOR x (MOVVconst [c])) && is32Bit(c) -> (NORconst [c] x)
|
|
|
|
|
|
|
|
|
|
(SLLV _ (MOVVconst [c])) && uint64(c)>=64 -> (MOVVconst [0])
|
|
|
|
|
(SRLV _ (MOVVconst [c])) && uint64(c)>=64 -> (MOVVconst [0])
|
|
|
|
|
(SRAV x (MOVVconst [c])) && uint64(c)>=64 -> (SRAVconst x [63])
|
|
|
|
|
(SLLV x (MOVVconst [c])) -> (SLLVconst x [c])
|
|
|
|
|
(SRLV x (MOVVconst [c])) -> (SRLVconst x [c])
|
|
|
|
|
(SRAV x (MOVVconst [c])) -> (SRAVconst x [c])
|
|
|
|
|
|
|
|
|
|
(SGT (MOVVconst [c]) x) && is32Bit(c) -> (SGTconst [c] x)
|
|
|
|
|
(SGTU (MOVVconst [c]) x) && is32Bit(c) -> (SGTUconst [c] x)
|
|
|
|
|
|
|
|
|
|
// mul by constant
|
|
|
|
|
(Select1 (MULVU x (MOVVconst [-1]))) -> (NEGV x)
|
|
|
|
|
(Select1 (MULVU _ (MOVVconst [0]))) -> (MOVVconst [0])
|
|
|
|
|
(Select1 (MULVU x (MOVVconst [1]))) -> x
|
|
|
|
|
(Select1 (MULVU x (MOVVconst [c]))) && isPowerOfTwo(c) -> (SLLVconst [log2(c)] x)
|
|
|
|
|
|
|
|
|
|
(Select1 (MULVU (MOVVconst [-1]) x)) -> (NEGV x)
|
|
|
|
|
(Select1 (MULVU (MOVVconst [0]) _)) -> (MOVVconst [0])
|
|
|
|
|
(Select1 (MULVU (MOVVconst [1]) x)) -> x
|
|
|
|
|
(Select1 (MULVU (MOVVconst [c]) x)) && isPowerOfTwo(c) -> (SLLVconst [log2(c)] x)
|
|
|
|
|
|
|
|
|
|
// div by constant
|
|
|
|
|
(Select1 (DIVVU x (MOVVconst [1]))) -> x
|
|
|
|
|
(Select1 (DIVVU x (MOVVconst [c]))) && isPowerOfTwo(c) -> (SRLVconst [log2(c)] x)
|
|
|
|
|
(Select0 (DIVVU _ (MOVVconst [1]))) -> (MOVVconst [0]) // mod
|
|
|
|
|
(Select0 (DIVVU x (MOVVconst [c]))) && isPowerOfTwo(c) -> (ANDconst [c-1] x) // mod
|
|
|
|
|
|
|
|
|
|
// generic simplifications
|
|
|
|
|
(ADDV x (NEGV y)) -> (SUBV x y)
|
|
|
|
|
(ADDV (NEGV y) x) -> (SUBV x y)
|
|
|
|
|
(SUBV x x) -> (MOVVconst [0])
|
|
|
|
|
(SUBV (MOVVconst [0]) x) -> (NEGV x)
|
|
|
|
|
(AND x x) -> x
|
|
|
|
|
(OR x x) -> x
|
|
|
|
|
(XOR x x) -> (MOVVconst [0])
|
|
|
|
|
|
|
|
|
|
// remove redundant *const ops
|
|
|
|
|
(ADDVconst [0] x) -> x
|
|
|
|
|
(SUBVconst [0] x) -> x
|
|
|
|
|
(ANDconst [0] _) -> (MOVVconst [0])
|
|
|
|
|
(ANDconst [-1] x) -> x
|
|
|
|
|
(ORconst [0] x) -> x
|
|
|
|
|
(ORconst [-1] _) -> (MOVVconst [-1])
|
|
|
|
|
(XORconst [0] x) -> x
|
|
|
|
|
(XORconst [-1] x) -> (NORconst [0] x)
|
|
|
|
|
|
|
|
|
|
// generic constant folding
|
|
|
|
|
(ADDVconst [c] (MOVVconst [d])) -> (MOVVconst [c+d])
|
|
|
|
|
(ADDVconst [c] (ADDVconst [d] x)) && is32Bit(c+d) -> (ADDVconst [c+d] x)
|
|
|
|
|
(ADDVconst [c] (SUBVconst [d] x)) && is32Bit(c-d) -> (ADDVconst [c-d] x)
|
|
|
|
|
(SUBVconst [c] (MOVVconst [d])) -> (MOVVconst [d-c])
|
|
|
|
|
(SUBVconst [c] (SUBVconst [d] x)) && is32Bit(-c-d) -> (ADDVconst [-c-d] x)
|
|
|
|
|
(SUBVconst [c] (ADDVconst [d] x)) && is32Bit(-c+d) -> (ADDVconst [-c+d] x)
|
|
|
|
|
(SLLVconst [c] (MOVVconst [d])) -> (MOVVconst [int64(d)<<uint64(c)])
|
|
|
|
|
(SRLVconst [c] (MOVVconst [d])) -> (MOVVconst [int64(uint64(d)>>uint64(c))])
|
|
|
|
|
(SRAVconst [c] (MOVVconst [d])) -> (MOVVconst [int64(d)>>uint64(c)])
|
|
|
|
|
(Select1 (MULVU (MOVVconst [c]) (MOVVconst [d]))) -> (MOVVconst [c*d])
|
|
|
|
|
(Select1 (DIVV (MOVVconst [c]) (MOVVconst [d]))) -> (MOVVconst [int64(c)/int64(d)])
|
|
|
|
|
(Select1 (DIVVU (MOVVconst [c]) (MOVVconst [d]))) -> (MOVVconst [int64(uint64(c)/uint64(d))])
|
|
|
|
|
(Select0 (DIVV (MOVVconst [c]) (MOVVconst [d]))) -> (MOVVconst [int64(c)%int64(d)]) // mod
|
|
|
|
|
(Select0 (DIVVU (MOVVconst [c]) (MOVVconst [d]))) -> (MOVVconst [int64(uint64(c)%uint64(d))]) // mod
|
|
|
|
|
(ANDconst [c] (MOVVconst [d])) -> (MOVVconst [c&d])
|
|
|
|
|
(ANDconst [c] (ANDconst [d] x)) -> (ANDconst [c&d] x)
|
|
|
|
|
(ORconst [c] (MOVVconst [d])) -> (MOVVconst [c|d])
|
|
|
|
|
(ORconst [c] (ORconst [d] x)) && is32Bit(c|d) -> (ORconst [c|d] x)
|
|
|
|
|
(XORconst [c] (MOVVconst [d])) -> (MOVVconst [c^d])
|
|
|
|
|
(XORconst [c] (XORconst [d] x)) && is32Bit(c^d) -> (XORconst [c^d] x)
|
|
|
|
|
(NORconst [c] (MOVVconst [d])) -> (MOVVconst [^(c|d)])
|
|
|
|
|
(NEGV (MOVVconst [c])) -> (MOVVconst [-c])
|
|
|
|
|
(MOVBreg (MOVVconst [c])) -> (MOVVconst [int64(int8(c))])
|
|
|
|
|
(MOVBUreg (MOVVconst [c])) -> (MOVVconst [int64(uint8(c))])
|
|
|
|
|
(MOVHreg (MOVVconst [c])) -> (MOVVconst [int64(int16(c))])
|
|
|
|
|
(MOVHUreg (MOVVconst [c])) -> (MOVVconst [int64(uint16(c))])
|
|
|
|
|
(MOVWreg (MOVVconst [c])) -> (MOVVconst [int64(int32(c))])
|
|
|
|
|
(MOVWUreg (MOVVconst [c])) -> (MOVVconst [int64(uint32(c))])
|
|
|
|
|
(MOVVreg (MOVVconst [c])) -> (MOVVconst [c])
|
|
|
|
|
|
|
|
|
|
// constant comparisons
|
|
|
|
|
(SGTconst [c] (MOVVconst [d])) && int64(c)>int64(d) -> (MOVVconst [1])
|
|
|
|
|
(SGTconst [c] (MOVVconst [d])) && int64(c)<=int64(d) -> (MOVVconst [0])
|
|
|
|
|
(SGTUconst [c] (MOVVconst [d])) && uint64(c)>uint64(d) -> (MOVVconst [1])
|
|
|
|
|
(SGTUconst [c] (MOVVconst [d])) && uint64(c)<=uint64(d) -> (MOVVconst [0])
|
|
|
|
|
|
|
|
|
|
// other known comparisons
|
|
|
|
|
(SGTconst [c] (MOVBreg _)) && 0x7f < int64(c) -> (MOVVconst [1])
|
|
|
|
|
(SGTconst [c] (MOVBreg _)) && int64(c) <= -0x80 -> (MOVVconst [0])
|
|
|
|
|
(SGTconst [c] (MOVBUreg _)) && 0xff < int64(c) -> (MOVVconst [1])
|
|
|
|
|
(SGTconst [c] (MOVBUreg _)) && int64(c) < 0 -> (MOVVconst [0])
|
|
|
|
|
(SGTUconst [c] (MOVBUreg _)) && 0xff < uint64(c) -> (MOVVconst [1])
|
|
|
|
|
(SGTconst [c] (MOVHreg _)) && 0x7fff < int64(c) -> (MOVVconst [1])
|
|
|
|
|
(SGTconst [c] (MOVHreg _)) && int64(c) <= -0x8000 -> (MOVVconst [0])
|
|
|
|
|
(SGTconst [c] (MOVHUreg _)) && 0xffff < int64(c) -> (MOVVconst [1])
|
|
|
|
|
(SGTconst [c] (MOVHUreg _)) && int64(c) < 0 -> (MOVVconst [0])
|
|
|
|
|
(SGTUconst [c] (MOVHUreg _)) && 0xffff < uint64(c) -> (MOVVconst [1])
|
|
|
|
|
(SGTconst [c] (MOVWUreg _)) && int64(c) < 0 -> (MOVVconst [0])
|
|
|
|
|
(SGTconst [c] (ANDconst [m] _)) && 0 <= m && m < c -> (MOVVconst [1])
|
|
|
|
|
(SGTUconst [c] (ANDconst [m] _)) && uint64(m) < uint64(c) -> (MOVVconst [1])
|
|
|
|
|
(SGTconst [c] (SRLVconst _ [d])) && 0 <= c && 0 < d && d <= 63 && 1<<uint64(64-d) <= c -> (MOVVconst [1])
|
|
|
|
|
(SGTUconst [c] (SRLVconst _ [d])) && 0 < d && d <= 63 && 1<<uint64(64-d) <= uint64(c) -> (MOVVconst [1])
|
|
|
|
|
|
|
|
|
|
// absorb constants into branches
|
|
|
|
|
(EQ (MOVVconst [0]) yes no) -> (First nil yes no)
|
|
|
|
|
(EQ (MOVVconst [c]) yes no) && c != 0 -> (First nil no yes)
|
|
|
|
|
(NE (MOVVconst [0]) yes no) -> (First nil no yes)
|
|
|
|
|
(NE (MOVVconst [c]) yes no) && c != 0 -> (First nil yes no)
|
|
|
|
|
(LTZ (MOVVconst [c]) yes no) && c < 0 -> (First nil yes no)
|
|
|
|
|
(LTZ (MOVVconst [c]) yes no) && c >= 0 -> (First nil no yes)
|
|
|
|
|
(LEZ (MOVVconst [c]) yes no) && c <= 0 -> (First nil yes no)
|
|
|
|
|
(LEZ (MOVVconst [c]) yes no) && c > 0 -> (First nil no yes)
|
|
|
|
|
(GTZ (MOVVconst [c]) yes no) && c > 0 -> (First nil yes no)
|
|
|
|
|
(GTZ (MOVVconst [c]) yes no) && c <= 0 -> (First nil no yes)
|
|
|
|
|
(GEZ (MOVVconst [c]) yes no) && c >= 0 -> (First nil yes no)
|
|
|
|
|
(GEZ (MOVVconst [c]) yes no) && c < 0 -> (First nil no yes)
|
|
|
|
|