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cmd/compile: merge sign extension and shift into SBFIZ

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This patch adds some rules to rewrite "(LeftShift (SignExtend x) lc)"
expression as "SBFIZ".

Add the test cases.

Change-Id: I294c4ba09712eeb02c7a952447bb006780f1e60d
Reviewed-on: https://go-review.googlesource.com/c/go/+/267602
Trust: fannie zhang <Fannie.Zhang@arm.com>
Trust: Cherry Mui <cherryyz@google.com>
Run-TryBot: fannie zhang <Fannie.Zhang@arm.com>
TryBot-Result: Go Bot <gobot@golang.org>
Reviewed-by: Keith Randall <khr@golang.org>
This commit is contained in:
fanzha02 2021-09-06 11:15:30 +08:00 committed by fannie zhang
parent 43b05173a2
commit 7b69ddc171
3 changed files with 55 additions and 0 deletions
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4
src/cmd/compile/internal/ssa/gen/ARM64.rules
View file

@ -1827,6 +1827,10 @@
(MOVWreg (SLLconst [lc] x)) && lc < 32 => (SBFIZ [armBFAuxInt(lc, 32-lc)] x)
(MOVHreg (SLLconst [lc] x)) && lc < 16 => (SBFIZ [armBFAuxInt(lc, 16-lc)] x)
(MOVBreg (SLLconst [lc] x)) && lc < 8 => (SBFIZ [armBFAuxInt(lc, 8-lc)] x)
// int64(x) << lc
(SLLconst [lc] (MOVWreg x)) => (SBFIZ [armBFAuxInt(lc, min(32, 64-lc))] x)
(SLLconst [lc] (MOVHreg x)) => (SBFIZ [armBFAuxInt(lc, min(16, 64-lc))] x)
(SLLconst [lc] (MOVBreg x)) => (SBFIZ [armBFAuxInt(lc, min(8, 64-lc))] x)
// sbfx
// (x << lc) >> rc

39
src/cmd/compile/internal/ssa/rewriteARM64.go
View file

@ -20087,6 +20087,45 @@ func rewriteValueARM64_OpARM64SLLconst(v *Value) bool {
v.AddArg(x)
return true
}
// match: (SLLconst [lc] (MOVWreg x))
// result: (SBFIZ [armBFAuxInt(lc, min(32, 64-lc))] x)
for {
lc := auxIntToInt64(v.AuxInt)
if v_0.Op != OpARM64MOVWreg {
break
}
x := v_0.Args[0]
v.reset(OpARM64SBFIZ)
v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc, min(32, 64-lc)))
v.AddArg(x)
return true
}
// match: (SLLconst [lc] (MOVHreg x))
// result: (SBFIZ [armBFAuxInt(lc, min(16, 64-lc))] x)
for {
lc := auxIntToInt64(v.AuxInt)
if v_0.Op != OpARM64MOVHreg {
break
}
x := v_0.Args[0]
v.reset(OpARM64SBFIZ)
v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc, min(16, 64-lc)))
v.AddArg(x)
return true
}
// match: (SLLconst [lc] (MOVBreg x))
// result: (SBFIZ [armBFAuxInt(lc, min(8, 64-lc))] x)
for {
lc := auxIntToInt64(v.AuxInt)
if v_0.Op != OpARM64MOVBreg {
break
}
x := v_0.Args[0]
v.reset(OpARM64SBFIZ)
v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc, min(8, 64-lc)))
v.AddArg(x)
return true
}
// match: (SLLconst [sc] (ANDconst [ac] x))
// cond: isARM64BFMask(sc, ac, 0)
// result: (UBFIZ [armBFAuxInt(sc, arm64BFWidth(ac, 0))] x)

12
test/codegen/bitfield.go
View file

@ -99,6 +99,18 @@ func sbfiz5(x int32) int32 {
return (x << 4) >> 3
}
func sbfiz5(x int32) int64 {
return int64(x+1) << 40 // arm64:"SBFIZ\t[$]40, R[0-9]+, [$]24",-"LSL"
}
func sbfiz6(x int16) int64 {
return int64(x+1) << 3 // arm64:"SBFIZ\t[$]3, R[0-9]+, [$]16",-"LSL"
}
func sbfiz7(x int8) int64 {
return int64(x+1) << 62 // arm64:"SBFIZ\t[$]62, R[0-9]+, [$]2",-"LSL"
}
// sbfx
func sbfx1(x int64) int64 {
return (x << 3) >> 4 // arm64:"SBFX\t[$]1, R[0-9]+, [$]60",-"LSL",-"ASR"