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cmd/compile: enable const division for arm64
performance: benchmark old ns/op new ns/op delta BenchmarkDivconstI64-8 8.28 2.70 -67.39% BenchmarkDivconstU64-8 8.28 4.69 -43.36% BenchmarkDivconstI32-8 8.28 6.39 -22.83% BenchmarkDivconstU32-8 8.28 4.43 -46.50% BenchmarkDivconstI16-8 5.17 5.17 +0.00% BenchmarkDivconstU16-8 5.33 5.34 +0.19% BenchmarkDivconstI8-8 3.50 3.50 +0.00% BenchmarkDivconstU8-8 3.51 3.50 -0.28% Fixes #15382 Change-Id: Ibce7b28f0586d593b33c4d4ecc5d5e7e7c905d13 Reviewed-on: https://go-review.googlesource.com/22292 Reviewed-by: Michael Munday <munday@ca.ibm.com> Reviewed-by: David Chase <drchase@google.com>
This commit is contained in:
parent
7538b1db8e
commit
74a9bad638
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@ -29,6 +29,8 @@ func Main() {
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gc.Thearch.Betypeinit = betypeinit
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gc.Thearch.Betypeinit = betypeinit
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gc.Thearch.Cgen_hmul = cgen_hmul
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gc.Thearch.Cgen_hmul = cgen_hmul
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gc.Thearch.AddSetCarry = AddSetCarry
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gc.Thearch.RightShiftWithCarry = RightShiftWithCarry
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gc.Thearch.Cgen_shift = cgen_shift
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gc.Thearch.Cgen_shift = cgen_shift
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gc.Thearch.Clearfat = clearfat
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gc.Thearch.Clearfat = clearfat
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gc.Thearch.Defframe = defframe
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gc.Thearch.Defframe = defframe
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@ -252,6 +252,53 @@ func dodiv(op gc.Op, nl *gc.Node, nr *gc.Node, res *gc.Node) {
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}
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}
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}
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}
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// RightShiftWithCarry generates a constant unsigned
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// right shift with carry.
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//
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// res = n >> shift // with carry
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func RightShiftWithCarry(n *gc.Node, shift uint, res *gc.Node) {
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// Extra 1 is for carry bit.
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maxshift := uint(n.Type.Width*8 + 1)
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if shift == 0 {
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gmove(n, res)
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} else if shift < maxshift {
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// 1. clear rightmost bit of target
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var n1 gc.Node
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gc.Nodconst(&n1, n.Type, 1)
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gins(optoas(gc.ORSH, n.Type), &n1, n)
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gins(optoas(gc.OLSH, n.Type), &n1, n)
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// 2. add carry flag to target
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var n2 gc.Node
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gc.Nodconst(&n1, n.Type, 0)
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gc.Regalloc(&n2, n.Type, nil)
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gins(optoas(gc.OAS, n.Type), &n1, &n2)
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gins(arm64.AADC, &n2, n)
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// 3. right rotate 1 bit
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gc.Nodconst(&n1, n.Type, 1)
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gins(arm64.AROR, &n1, n)
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// ARM64 backend doesn't eliminate shifts by 0. It is manually checked here.
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if shift > 1 {
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var n3 gc.Node
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gc.Nodconst(&n3, n.Type, int64(shift-1))
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cgen_shift(gc.ORSH, true, n, &n3, res)
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} else {
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gmove(n, res)
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}
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gc.Regfree(&n2)
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} else {
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gc.Fatalf("RightShiftWithCarry: shift(%v) is bigger than max size(%v)", shift, maxshift)
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}
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}
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// AddSetCarry generates add and set carry.
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//
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// res = nl + nr // with carry flag set
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func AddSetCarry(nl *gc.Node, nr *gc.Node, res *gc.Node) {
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gins(arm64.AADDS, nl, nr)
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gmove(nr, res)
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}
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/*
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/*
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* generate high multiply:
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* generate high multiply:
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* res = (nl*nr) >> width
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* res = (nl*nr) >> width
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@ -890,18 +890,6 @@ func optoas(op gc.Op, t *gc.Type) obj.As {
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ORSH_ | gc.TINT64:
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ORSH_ | gc.TINT64:
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a = arm64.AASR
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a = arm64.AASR
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// TODO(minux): handle rotates
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//case CASE(ORROTC, TINT8):
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//case CASE(ORROTC, TUINT8):
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//case CASE(ORROTC, TINT16):
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//case CASE(ORROTC, TUINT16):
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//case CASE(ORROTC, TINT32):
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//case CASE(ORROTC, TUINT32):
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//case CASE(ORROTC, TINT64):
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//case CASE(ORROTC, TUINT64):
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// a = 0//??? RLDC??
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// break;
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case OHMUL_ | gc.TINT64:
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case OHMUL_ | gc.TINT64:
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a = arm64.ASMULH
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a = arm64.ASMULH
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@ -534,10 +534,13 @@ func copyu(p *obj.Prog, v *obj.Addr, s *obj.Addr) int {
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return 0
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return 0
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case arm64.AADD, /* read p->from, read p->reg, write p->to */
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case arm64.AADD, /* read p->from, read p->reg, write p->to */
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arm64.AADDS,
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arm64.ASUB,
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arm64.ASUB,
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arm64.AADC,
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arm64.AAND,
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arm64.AAND,
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arm64.AORR,
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arm64.AORR,
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arm64.AEOR,
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arm64.AEOR,
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arm64.AROR,
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arm64.AMUL,
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arm64.AMUL,
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arm64.ASMULL,
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arm64.ASMULL,
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arm64.AUMULL,
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arm64.AUMULL,
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@ -59,6 +59,9 @@ var progtable = [arm64.ALAST & obj.AMask]obj.ProgInfo{
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arm64.ALSR & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite},
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arm64.ALSR & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite},
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arm64.AASR & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite},
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arm64.AASR & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite},
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arm64.ACMP & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead},
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arm64.ACMP & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead},
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arm64.AADC & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite | gc.UseCarry},
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arm64.AROR & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite},
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arm64.AADDS & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite | gc.SetCarry},
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// Floating point.
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// Floating point.
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arm64.AFADDD & obj.AMask: {Flags: gc.SizeD | gc.LeftRead | gc.RegRead | gc.RightWrite},
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arm64.AFADDD & obj.AMask: {Flags: gc.SizeD | gc.LeftRead | gc.RegRead | gc.RightWrite},
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@ -2642,9 +2642,9 @@ func cgen_ret(n *Node) {
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// signed and unsigned high multiplication (OHMUL).
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// signed and unsigned high multiplication (OHMUL).
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func hasHMUL64() bool {
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func hasHMUL64() bool {
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switch Ctxt.Arch.Family {
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switch Ctxt.Arch.Family {
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case sys.AMD64, sys.S390X:
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case sys.AMD64, sys.S390X, sys.ARM64:
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return true
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return true
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case sys.ARM, sys.ARM64, sys.I386, sys.MIPS64, sys.PPC64:
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case sys.ARM, sys.I386, sys.MIPS64, sys.PPC64:
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return false
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return false
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}
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}
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Fatalf("unknown architecture")
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Fatalf("unknown architecture")
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@ -2664,6 +2664,28 @@ func hasRROTC64() bool {
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return false
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return false
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}
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}
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func hasRightShiftWithCarry() bool {
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switch Ctxt.Arch.Family {
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case sys.ARM64:
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return true
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case sys.AMD64, sys.ARM, sys.I386, sys.MIPS64, sys.PPC64, sys.S390X:
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return false
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}
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Fatalf("unknown architecture")
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return false
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}
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func hasAddSetCarry() bool {
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switch Ctxt.Arch.Family {
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case sys.ARM64:
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return true
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case sys.AMD64, sys.ARM, sys.I386, sys.MIPS64, sys.PPC64, sys.S390X:
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return false
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}
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Fatalf("unknown architecture")
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return false
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}
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// generate division according to op, one of:
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// generate division according to op, one of:
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// res = nl / nr
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// res = nl / nr
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// res = nl % nr
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// res = nl % nr
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@ -2699,8 +2721,9 @@ func cgen_div(op Op, nl *Node, nr *Node, res *Node) {
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// the MSB. For now this needs the RROTC instruction.
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// the MSB. For now this needs the RROTC instruction.
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// TODO(mundaym): Hacker's Delight 2nd ed. chapter 10 proposes
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// TODO(mundaym): Hacker's Delight 2nd ed. chapter 10 proposes
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// an alternative sequence of instructions for architectures
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// an alternative sequence of instructions for architectures
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// that do not have a shift right with carry instruction.
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// (TODO: MIPS64, PPC64, S390X) that do not have a shift
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if m.Ua != 0 && !hasRROTC64() {
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// right with carry instruction.
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if m.Ua != 0 && !hasRROTC64() && !hasRightShiftWithCarry() {
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goto longdiv
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goto longdiv
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}
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}
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if op == OMOD {
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if op == OMOD {
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@ -2717,12 +2740,20 @@ func cgen_div(op Op, nl *Node, nr *Node, res *Node) {
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if m.Ua != 0 {
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if m.Ua != 0 {
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// Need to add numerator accounting for overflow.
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// Need to add numerator accounting for overflow.
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Thearch.Gins(Thearch.Optoas(OADD, nl.Type), &n1, &n3)
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if hasAddSetCarry() {
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Thearch.AddSetCarry(&n1, &n3, &n3)
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} else {
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Thearch.Gins(Thearch.Optoas(OADD, nl.Type), &n1, &n3)
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}
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Nodconst(&n2, nl.Type, 1)
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if !hasRROTC64() {
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Thearch.Gins(Thearch.Optoas(ORROTC, nl.Type), &n2, &n3)
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Thearch.RightShiftWithCarry(&n3, uint(m.S), &n3)
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Nodconst(&n2, nl.Type, int64(m.S)-1)
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} else {
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Thearch.Gins(Thearch.Optoas(ORSH, nl.Type), &n2, &n3)
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Nodconst(&n2, nl.Type, 1)
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Thearch.Gins(Thearch.Optoas(ORROTC, nl.Type), &n2, &n3)
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Nodconst(&n2, nl.Type, int64(m.S)-1)
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Thearch.Gins(Thearch.Optoas(ORSH, nl.Type), &n2, &n3)
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}
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} else {
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} else {
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Nodconst(&n2, nl.Type, int64(m.S))
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Nodconst(&n2, nl.Type, int64(m.S))
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Thearch.Gins(Thearch.Optoas(ORSH, nl.Type), &n2, &n3) // shift dx
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Thearch.Gins(Thearch.Optoas(ORSH, nl.Type), &n2, &n3) // shift dx
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@ -378,23 +378,25 @@ type Arch struct {
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MAXWIDTH int64
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MAXWIDTH int64
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ReservedRegs []int
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ReservedRegs []int
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AddIndex func(*Node, int64, *Node) bool // optional
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AddIndex func(*Node, int64, *Node) bool // optional
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Betypeinit func()
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Betypeinit func()
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Bgen_float func(*Node, bool, int, *obj.Prog) // optional
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Bgen_float func(*Node, bool, int, *obj.Prog) // optional
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Cgen64 func(*Node, *Node) // only on 32-bit systems
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Cgen64 func(*Node, *Node) // only on 32-bit systems
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Cgenindex func(*Node, *Node, bool) *obj.Prog
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Cgenindex func(*Node, *Node, bool) *obj.Prog
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Cgen_bmul func(Op, *Node, *Node, *Node) bool
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Cgen_bmul func(Op, *Node, *Node, *Node) bool
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Cgen_float func(*Node, *Node) // optional
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Cgen_float func(*Node, *Node) // optional
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Cgen_hmul func(*Node, *Node, *Node)
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Cgen_hmul func(*Node, *Node, *Node)
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Cgen_shift func(Op, bool, *Node, *Node, *Node)
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RightShiftWithCarry func(*Node, uint, *Node) // only on systems without RROTC instruction
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Clearfat func(*Node)
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AddSetCarry func(*Node, *Node, *Node) // only on systems when ADD does not update carry flag
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Cmp64 func(*Node, *Node, Op, int, *obj.Prog) // only on 32-bit systems
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Cgen_shift func(Op, bool, *Node, *Node, *Node)
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Defframe func(*obj.Prog)
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Clearfat func(*Node)
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Dodiv func(Op, *Node, *Node, *Node)
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Cmp64 func(*Node, *Node, Op, int, *obj.Prog) // only on 32-bit systems
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Excise func(*Flow)
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Defframe func(*obj.Prog)
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Expandchecks func(*obj.Prog)
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Dodiv func(Op, *Node, *Node, *Node)
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Getg func(*Node)
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Excise func(*Flow)
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Gins func(obj.As, *Node, *Node) *obj.Prog
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Expandchecks func(*obj.Prog)
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Getg func(*Node)
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Gins func(obj.As, *Node, *Node) *obj.Prog
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// Ginscmp generates code comparing n1 to n2 and jumping away if op is satisfied.
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// Ginscmp generates code comparing n1 to n2 and jumping away if op is satisfied.
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// The returned prog should be Patch'ed with the jump target.
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// The returned prog should be Patch'ed with the jump target.
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@ -3424,7 +3424,7 @@ func walkdiv(n *Node, init *Nodes) *Node {
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// if >= 0, nr is 1<<pow // 1 if nr is negative.
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// if >= 0, nr is 1<<pow // 1 if nr is negative.
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// TODO(minux)
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// TODO(minux)
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if Thearch.LinkArch.InFamily(sys.MIPS64, sys.ARM64, sys.PPC64) {
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if Thearch.LinkArch.InFamily(sys.MIPS64, sys.PPC64) {
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return n
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return n
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}
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}
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@ -3485,6 +3485,16 @@ func walkdiv(n *Node, init *Nodes) *Node {
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goto ret
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goto ret
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}
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}
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// TODO(zhongwei) Test shows that TUINT8, TINT8, TUINT16 and TINT16's "quick division" method
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// on current arm64 backend is slower than hardware div instruction on ARM64 due to unnecessary
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// data movement between registers. It could be enabled when generated code is good enough.
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if Thearch.LinkArch.Family == sys.ARM64 {
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switch Simtype[nl.Type.Etype] {
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case TUINT8, TINT8, TUINT16, TINT16:
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return n
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}
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}
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switch Simtype[nl.Type.Etype] {
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switch Simtype[nl.Type.Etype] {
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default:
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default:
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return n
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return n
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@ -155,6 +155,7 @@ var optab = []Optab{
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{AADC, C_REG, C_REG, C_REG, 1, 4, 0, 0, 0},
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{AADC, C_REG, C_REG, C_REG, 1, 4, 0, 0, 0},
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{AADC, C_REG, C_NONE, C_REG, 1, 4, 0, 0, 0},
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{AADC, C_REG, C_NONE, C_REG, 1, 4, 0, 0, 0},
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{ANEG, C_REG, C_NONE, C_REG, 25, 4, 0, 0, 0},
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{ANEG, C_REG, C_NONE, C_REG, 25, 4, 0, 0, 0},
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{ANEG, C_NONE, C_NONE, C_REG, 25, 4, 0, 0, 0},
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{ANGC, C_REG, C_NONE, C_REG, 17, 4, 0, 0, 0},
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{ANGC, C_REG, C_NONE, C_REG, 17, 4, 0, 0, 0},
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{ACMP, C_REG, C_REG, C_NONE, 1, 4, 0, 0, 0},
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{ACMP, C_REG, C_REG, C_NONE, 1, 4, 0, 0, 0},
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{AADD, C_ADDCON, C_RSP, C_RSP, 2, 4, 0, 0, 0},
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{AADD, C_ADDCON, C_RSP, C_RSP, 2, 4, 0, 0, 0},
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@ -2198,6 +2199,9 @@ func asmout(ctxt *obj.Link, p *obj.Prog, o *Optab, out []uint32) {
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o1 = oprrr(ctxt, p.As)
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o1 = oprrr(ctxt, p.As)
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rf := int(p.From.Reg)
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rf := int(p.From.Reg)
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if rf == C_NONE {
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rf = int(p.To.Reg)
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}
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rt := int(p.To.Reg)
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rt := int(p.To.Reg)
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o1 |= (uint32(rf&31) << 16) | (REGZERO & 31 << 5) | uint32(rt&31)
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o1 |= (uint32(rf&31) << 16) | (REGZERO & 31 << 5) | uint32(rt&31)
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@ -195,7 +195,6 @@ func dodiv(n, d uint64) (q, r uint64) {
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if GOARCH == "arm" {
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if GOARCH == "arm" {
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// arm doesn't have a division instruction, so
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// arm doesn't have a division instruction, so
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// slowdodiv is the best that we can do.
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// slowdodiv is the best that we can do.
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// TODO: revisit for arm64.
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return slowdodiv(n, d)
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return slowdodiv(n, d)
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}
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}
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73
test/bench/go1/divconst_test.go
Normal file
73
test/bench/go1/divconst_test.go
Normal file
|
@ -0,0 +1,73 @@
|
||||||
|
// Copyright 2016 The Go Authors. All rights reserved.
|
||||||
|
// Use of this source code is governed by a BSD-style
|
||||||
|
// license that can be found in the LICENSE file.
|
||||||
|
|
||||||
|
package go1
|
||||||
|
|
||||||
|
import (
|
||||||
|
"testing"
|
||||||
|
)
|
||||||
|
|
||||||
|
var i64res int64
|
||||||
|
|
||||||
|
func BenchmarkDivconstI64(b *testing.B) {
|
||||||
|
for i := 0; i < b.N; i++ {
|
||||||
|
i64res = int64(i) / 7
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
var u64res uint64
|
||||||
|
|
||||||
|
func BenchmarkDivconstU64(b *testing.B) {
|
||||||
|
for i := 0; i < b.N; i++ {
|
||||||
|
u64res = uint64(i) / 7
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
var i32res int32
|
||||||
|
|
||||||
|
func BenchmarkDivconstI32(b *testing.B) {
|
||||||
|
for i := 0; i < b.N; i++ {
|
||||||
|
i32res = int32(i) / 7
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
var u32res uint32
|
||||||
|
|
||||||
|
func BenchmarkDivconstU32(b *testing.B) {
|
||||||
|
for i := 0; i < b.N; i++ {
|
||||||
|
u32res = uint32(i) / 7
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
var i16res int16
|
||||||
|
|
||||||
|
func BenchmarkDivconstI16(b *testing.B) {
|
||||||
|
for i := 0; i < b.N; i++ {
|
||||||
|
i16res = int16(i) / 7
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
var u16res uint16
|
||||||
|
|
||||||
|
func BenchmarkDivconstU16(b *testing.B) {
|
||||||
|
for i := 0; i < b.N; i++ {
|
||||||
|
u16res = uint16(i) / 7
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
var i8res int8
|
||||||
|
|
||||||
|
func BenchmarkDivconstI8(b *testing.B) {
|
||||||
|
for i := 0; i < b.N; i++ {
|
||||||
|
i8res = int8(i) / 7
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
var u8res uint8
|
||||||
|
|
||||||
|
func BenchmarkDivconstU8(b *testing.B) {
|
||||||
|
for i := 0; i < b.N; i++ {
|
||||||
|
u8res = uint8(i) / 7
|
||||||
|
}
|
||||||
|
}
|
Loading…
Reference in a new issue