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cmd/compile: add indexed SET* opcodes for amd64
Update #61356 Change-Id: I391af98563b1c068208784c80ea736c78c29639d Reviewed-on: https://go-review.googlesource.com/c/go/+/510435 Run-TryBot: Keith Randall <khr@golang.org> Reviewed-by: Matthew Dempsky <mdempsky@google.com> Reviewed-by: Martin Möhrmann <martin@golang.org> TryBot-Result: Gopher Robot <gobot@golang.org> Reviewed-by: Martin Möhrmann <moehrmann@google.com>
This commit is contained in:
Keith Randall
parent
505e50b1e3
commit
67983c0f78
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@ -1187,6 +1187,15 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
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p.To.Reg = v.Args[0].Reg()
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ssagen.AddAux(&p.To, v)
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case ssa.OpAMD64SETEQstoreidx1, ssa.OpAMD64SETNEstoreidx1,
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ssa.OpAMD64SETLstoreidx1, ssa.OpAMD64SETLEstoreidx1,
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ssa.OpAMD64SETGstoreidx1, ssa.OpAMD64SETGEstoreidx1,
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ssa.OpAMD64SETBstoreidx1, ssa.OpAMD64SETBEstoreidx1,
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ssa.OpAMD64SETAstoreidx1, ssa.OpAMD64SETAEstoreidx1:
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p := s.Prog(v.Op.Asm())
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memIdx(&p.To, v)
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ssagen.AddAux(&p.To, v)
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case ssa.OpAMD64SETNEF:
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t := v.RegTmp()
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p := s.Prog(v.Op.Asm())
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@ -697,16 +697,27 @@ func init() {
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{name: "SETAE", argLength: 1, reg: readflags, asm: "SETCC"}, // extract unsigned >= condition from arg0
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{name: "SETO", argLength: 1, reg: readflags, asm: "SETOS"}, // extract if overflow flag is set from arg0
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// Variants that store result to memory
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{name: "SETEQstore", argLength: 3, reg: gpstoreconst, asm: "SETEQ", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract == condition from arg1 to arg0+auxint+aux, arg2=mem
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{name: "SETNEstore", argLength: 3, reg: gpstoreconst, asm: "SETNE", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract != condition from arg1 to arg0+auxint+aux, arg2=mem
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{name: "SETLstore", argLength: 3, reg: gpstoreconst, asm: "SETLT", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract signed < condition from arg1 to arg0+auxint+aux, arg2=mem
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{name: "SETLEstore", argLength: 3, reg: gpstoreconst, asm: "SETLE", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract signed <= condition from arg1 to arg0+auxint+aux, arg2=mem
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{name: "SETGstore", argLength: 3, reg: gpstoreconst, asm: "SETGT", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract signed > condition from arg1 to arg0+auxint+aux, arg2=mem
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{name: "SETGEstore", argLength: 3, reg: gpstoreconst, asm: "SETGE", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract signed >= condition from arg1 to arg0+auxint+aux, arg2=mem
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{name: "SETBstore", argLength: 3, reg: gpstoreconst, asm: "SETCS", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract unsigned < condition from arg1 to arg0+auxint+aux, arg2=mem
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{name: "SETBEstore", argLength: 3, reg: gpstoreconst, asm: "SETLS", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract unsigned <= condition from arg1 to arg0+auxint+aux, arg2=mem
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{name: "SETAstore", argLength: 3, reg: gpstoreconst, asm: "SETHI", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract unsigned > condition from arg1 to arg0+auxint+aux, arg2=mem
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{name: "SETAEstore", argLength: 3, reg: gpstoreconst, asm: "SETCC", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract unsigned >= condition from arg1 to arg0+auxint+aux, arg2=mem
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{name: "SETEQstore", argLength: 3, reg: gpstoreconst, asm: "SETEQ", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract == condition from arg1 to arg0+auxint+aux, arg2=mem
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{name: "SETNEstore", argLength: 3, reg: gpstoreconst, asm: "SETNE", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract != condition from arg1 to arg0+auxint+aux, arg2=mem
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{name: "SETLstore", argLength: 3, reg: gpstoreconst, asm: "SETLT", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract signed < condition from arg1 to arg0+auxint+aux, arg2=mem
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{name: "SETLEstore", argLength: 3, reg: gpstoreconst, asm: "SETLE", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract signed <= condition from arg1 to arg0+auxint+aux, arg2=mem
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{name: "SETGstore", argLength: 3, reg: gpstoreconst, asm: "SETGT", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract signed > condition from arg1 to arg0+auxint+aux, arg2=mem
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{name: "SETGEstore", argLength: 3, reg: gpstoreconst, asm: "SETGE", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract signed >= condition from arg1 to arg0+auxint+aux, arg2=mem
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{name: "SETBstore", argLength: 3, reg: gpstoreconst, asm: "SETCS", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract unsigned < condition from arg1 to arg0+auxint+aux, arg2=mem
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{name: "SETBEstore", argLength: 3, reg: gpstoreconst, asm: "SETLS", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract unsigned <= condition from arg1 to arg0+auxint+aux, arg2=mem
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{name: "SETAstore", argLength: 3, reg: gpstoreconst, asm: "SETHI", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract unsigned > condition from arg1 to arg0+auxint+aux, arg2=mem
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{name: "SETAEstore", argLength: 3, reg: gpstoreconst, asm: "SETCC", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract unsigned >= condition from arg1 to arg0+auxint+aux, arg2=mem
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{name: "SETEQstoreidx1", argLength: 4, reg: gpstoreconstidx, asm: "SETEQ", aux: "SymOff", typ: "Mem", scale: 1, commutative: true, symEffect: "Write"}, // extract == condition from arg2 to arg0+arg1+auxint+aux, arg3=mem
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{name: "SETNEstoreidx1", argLength: 4, reg: gpstoreconstidx, asm: "SETNE", aux: "SymOff", typ: "Mem", scale: 1, commutative: true, symEffect: "Write"}, // extract != condition from arg2 to arg0+arg1+auxint+aux, arg3=mem
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{name: "SETLstoreidx1", argLength: 4, reg: gpstoreconstidx, asm: "SETLT", aux: "SymOff", typ: "Mem", scale: 1, commutative: true, symEffect: "Write"}, // extract signed < condition from arg2 to arg0+arg1+auxint+aux, arg3=mem
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{name: "SETLEstoreidx1", argLength: 4, reg: gpstoreconstidx, asm: "SETLE", aux: "SymOff", typ: "Mem", scale: 1, commutative: true, symEffect: "Write"}, // extract signed <= condition from arg2 to arg0+arg1+auxint+aux, arg3=mem
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{name: "SETGstoreidx1", argLength: 4, reg: gpstoreconstidx, asm: "SETGT", aux: "SymOff", typ: "Mem", scale: 1, commutative: true, symEffect: "Write"}, // extract signed > condition from arg2 to arg0+arg1+auxint+aux, arg3=mem
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{name: "SETGEstoreidx1", argLength: 4, reg: gpstoreconstidx, asm: "SETGE", aux: "SymOff", typ: "Mem", scale: 1, commutative: true, symEffect: "Write"}, // extract signed >= condition from arg2 to arg0+arg1+auxint+aux, arg3=mem
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{name: "SETBstoreidx1", argLength: 4, reg: gpstoreconstidx, asm: "SETCS", aux: "SymOff", typ: "Mem", scale: 1, commutative: true, symEffect: "Write"}, // extract unsigned < condition from arg2 to arg0+arg1+auxint+aux, arg3=mem
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{name: "SETBEstoreidx1", argLength: 4, reg: gpstoreconstidx, asm: "SETLS", aux: "SymOff", typ: "Mem", scale: 1, commutative: true, symEffect: "Write"}, // extract unsigned <= condition from arg2 to arg0+arg1+auxint+aux, arg3=mem
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{name: "SETAstoreidx1", argLength: 4, reg: gpstoreconstidx, asm: "SETHI", aux: "SymOff", typ: "Mem", scale: 1, commutative: true, symEffect: "Write"}, // extract unsigned > condition from arg2 to arg0+arg1+auxint+aux, arg3=mem
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{name: "SETAEstoreidx1", argLength: 4, reg: gpstoreconstidx, asm: "SETCC", aux: "SymOff", typ: "Mem", scale: 1, commutative: true, symEffect: "Write"}, // extract unsigned >= condition from arg2 to arg0+arg1+auxint+aux, arg3=mem
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// Need different opcodes for floating point conditions because
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// any comparison involving a NaN is always FALSE and thus
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// the patterns for inverting conditions cannot be used.
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@ -195,6 +195,17 @@ var combine = map[[2]Op]Op{
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[2]Op{OpAMD64MOVQstoreconst, OpAMD64LEAQ1}: OpAMD64MOVQstoreconstidx1,
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[2]Op{OpAMD64MOVQstoreconst, OpAMD64LEAQ8}: OpAMD64MOVQstoreconstidx8,
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[2]Op{OpAMD64SETEQstore, OpAMD64LEAQ1}: OpAMD64SETEQstoreidx1,
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[2]Op{OpAMD64SETNEstore, OpAMD64LEAQ1}: OpAMD64SETNEstoreidx1,
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[2]Op{OpAMD64SETLstore, OpAMD64LEAQ1}: OpAMD64SETLstoreidx1,
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[2]Op{OpAMD64SETLEstore, OpAMD64LEAQ1}: OpAMD64SETLEstoreidx1,
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[2]Op{OpAMD64SETGstore, OpAMD64LEAQ1}: OpAMD64SETGstoreidx1,
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[2]Op{OpAMD64SETGEstore, OpAMD64LEAQ1}: OpAMD64SETGEstoreidx1,
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[2]Op{OpAMD64SETBstore, OpAMD64LEAQ1}: OpAMD64SETBstoreidx1,
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[2]Op{OpAMD64SETBEstore, OpAMD64LEAQ1}: OpAMD64SETBEstoreidx1,
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[2]Op{OpAMD64SETAstore, OpAMD64LEAQ1}: OpAMD64SETAstoreidx1,
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[2]Op{OpAMD64SETAEstore, OpAMD64LEAQ1}: OpAMD64SETAEstoreidx1,
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// These instructions are re-split differently for performance, see needSplit above.
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// TODO if 386 versions are created, also update needSplit and _gen/386splitload.rules
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[2]Op{OpAMD64CMPBload, OpAMD64ADDQ}: OpAMD64CMPBloadidx1,
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@ -935,6 +935,16 @@ const (
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OpAMD64SETBEstore
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OpAMD64SETAstore
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OpAMD64SETAEstore
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OpAMD64SETEQstoreidx1
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OpAMD64SETNEstoreidx1
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OpAMD64SETLstoreidx1
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OpAMD64SETLEstoreidx1
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OpAMD64SETGstoreidx1
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OpAMD64SETGEstoreidx1
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OpAMD64SETBstoreidx1
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OpAMD64SETBEstoreidx1
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OpAMD64SETAstoreidx1
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OpAMD64SETAEstoreidx1
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OpAMD64SETEQF
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OpAMD64SETNEF
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OpAMD64SETORD
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@ -12150,6 +12160,156 @@ var opcodeTable = [...]opInfo{
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},
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},
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},
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{
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name: "SETEQstoreidx1",
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auxType: auxSymOff,
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argLen: 4,
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commutative: true,
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symEffect: SymWrite,
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asm: x86.ASETEQ,
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scale: 1,
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reg: regInfo{
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inputs: []inputInfo{
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{1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
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{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
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},
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},
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},
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{
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name: "SETNEstoreidx1",
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auxType: auxSymOff,
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argLen: 4,
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commutative: true,
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symEffect: SymWrite,
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asm: x86.ASETNE,
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scale: 1,
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reg: regInfo{
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inputs: []inputInfo{
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{1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
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{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
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},
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},
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},
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{
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name: "SETLstoreidx1",
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auxType: auxSymOff,
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argLen: 4,
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commutative: true,
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symEffect: SymWrite,
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asm: x86.ASETLT,
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scale: 1,
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reg: regInfo{
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inputs: []inputInfo{
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{1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
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{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
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},
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},
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},
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{
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name: "SETLEstoreidx1",
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auxType: auxSymOff,
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argLen: 4,
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commutative: true,
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symEffect: SymWrite,
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asm: x86.ASETLE,
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scale: 1,
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reg: regInfo{
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inputs: []inputInfo{
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{1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
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{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
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},
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},
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},
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{
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name: "SETGstoreidx1",
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auxType: auxSymOff,
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argLen: 4,
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commutative: true,
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symEffect: SymWrite,
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asm: x86.ASETGT,
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scale: 1,
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reg: regInfo{
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inputs: []inputInfo{
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{1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
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{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
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},
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},
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},
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{
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name: "SETGEstoreidx1",
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auxType: auxSymOff,
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argLen: 4,
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commutative: true,
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symEffect: SymWrite,
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asm: x86.ASETGE,
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scale: 1,
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reg: regInfo{
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inputs: []inputInfo{
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{1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
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{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
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},
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},
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},
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{
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name: "SETBstoreidx1",
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auxType: auxSymOff,
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argLen: 4,
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commutative: true,
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symEffect: SymWrite,
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asm: x86.ASETCS,
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scale: 1,
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reg: regInfo{
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inputs: []inputInfo{
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{1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
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{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
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},
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},
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},
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{
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name: "SETBEstoreidx1",
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auxType: auxSymOff,
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argLen: 4,
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commutative: true,
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symEffect: SymWrite,
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asm: x86.ASETLS,
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scale: 1,
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reg: regInfo{
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inputs: []inputInfo{
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{1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
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{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
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},
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},
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},
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{
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name: "SETAstoreidx1",
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auxType: auxSymOff,
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argLen: 4,
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commutative: true,
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symEffect: SymWrite,
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asm: x86.ASETHI,
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scale: 1,
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reg: regInfo{
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inputs: []inputInfo{
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{1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
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{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
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},
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},
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},
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{
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name: "SETAEstoreidx1",
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auxType: auxSymOff,
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argLen: 4,
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commutative: true,
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symEffect: SymWrite,
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asm: x86.ASETCC,
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scale: 1,
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reg: regInfo{
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inputs: []inputInfo{
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{1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
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{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
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},
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},
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},
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{
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name: "SETEQF",
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argLen: 1,
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@ -365,3 +365,10 @@ func idxFloatOps(a []float64, b []float32, i int) (float64, float32) {
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d /= b[i+4]
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return c, d
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}
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func storeTest(a []bool, v int, i int) {
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// amd64: `BTL\t\$0,`,`SETCS\t4\([A-Z]+[0-9]*\)`
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a[4] = v&1 != 0
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// amd64: `BTL\t\$1,`,`SETCS\t3\([A-Z]+[0-9]*\)\([A-Z]+[0-9]*\*1\)`
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a[3+i] = v&2 != 0
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}
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