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https://github.com/golang/go
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cmd/compile/internal/ssa: improve masking codegen on PPC64
Generate RLDIC[LR] instead of MOVD mask, Rx; AND Rx, Ry, Rz. This helps reduce code size, and reduces the latency caused by the constant load. Similarly, for smaller-than-register values, truncate constants which exceed the range of the value's type to avoid needing to load a constant. Change-Id: I6019684795eb8962d4fd6d9585d08b17c15e7d64 Reviewed-on: https://go-review.googlesource.com/c/go/+/515576 Reviewed-by: Lynn Boger <laboger@linux.vnet.ibm.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Run-TryBot: Paul Murphy <murp@ibm.com> TryBot-Result: Gopher Robot <gobot@golang.org> Reviewed-by: Cherry Mui <cherryyz@google.com>
This commit is contained in:
Paul E. Murphy
Paul Murphy
parent
2186909d86
commit
5cdb132228
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@ -17,3 +17,16 @@
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(SETBCR [0] cmp) && buildcfg.GOPPC64 <= 9 => (ISELZ [4] (MOVDconst [1]) cmp)
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(SETBC [1] cmp) && buildcfg.GOPPC64 <= 9 => (ISELZ [1] (MOVDconst [1]) cmp)
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(SETBCR [1] cmp) && buildcfg.GOPPC64 <= 9 => (ISELZ [5] (MOVDconst [1]) cmp)
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// The upper bits of the smaller than register values is undefined. Take advantage of that.
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(AND <t> x:(MOVDconst [m]) n) && t.Size() <= 2 => (Select0 (ANDCCconst [int64(int16(m))] n))
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// Convert simple bit masks to an equivalent rldic[lr] if possible.
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(AND x:(MOVDconst [m]) n) && isPPC64ValidShiftMask(m) => (RLDICL [encodePPC64RotateMask(0,m,64)] n)
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(AND x:(MOVDconst [m]) n) && m != 0 && isPPC64ValidShiftMask(^m) => (RLDICR [encodePPC64RotateMask(0,m,64)] n)
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// If the RLDICL does not rotate its value, a shifted value can be merged.
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(RLDICL [em] x:(SRDconst [s] a)) && (em&0xFF0000) == 0 => (RLDICL [mergePPC64RLDICLandSRDconst(em, s)] a)
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// Convert rotated 32 bit masks on 32 bit values into rlwinm. In general, this leaves the upper 32 bits in an undefined state.
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(AND <t> x:(MOVDconst [m]) n) && t.Size() == 4 && isPPC64WordRotateMask(m) => (RLWINM [encodePPC64RotateMask(0,m,32)] n)
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@ -1499,6 +1499,25 @@ func encodePPC64RotateMask(rotate, mask, nbits int64) int64 {
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return int64(me) | int64(mb<<8) | int64(rotate<<16) | int64(nbits<<24)
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}
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// Merge (RLDICL [encoded] (SRDconst [s] x)) into (RLDICL [new_encoded] x)
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// SRDconst on PPC64 is an extended mnemonic of RLDICL. If the input to an
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// RLDICL is an SRDconst, and the RLDICL does not rotate its value, the two
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// operations can be combined. This functions assumes the two opcodes can
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// be merged, and returns an encoded rotate+mask value of the combined RLDICL.
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func mergePPC64RLDICLandSRDconst(encoded, s int64) int64 {
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mb := s
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r := 64 - s
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// A larger mb is a smaller mask.
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if (encoded>>8)&0xFF < mb {
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encoded = (encoded &^ 0xFF00) | mb<<8
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}
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// The rotate is expected to be 0.
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if (encoded & 0xFF0000) != 0 {
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panic("non-zero rotate")
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}
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return encoded | r<<16
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}
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// DecodePPC64RotateMask is the inverse operation of encodePPC64RotateMask. The values returned as
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// mb and me satisfy the POWER ISA definition of MASK(x,y) where MASK(mb,me) = mask.
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func DecodePPC64RotateMask(sauxint int64) (rotate, mb, me int64, mask uint64) {
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@ -3,11 +3,16 @@
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package ssa
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import "internal/buildcfg"
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import "cmd/compile/internal/types"
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func rewriteValuePPC64latelower(v *Value) bool {
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switch v.Op {
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case OpPPC64AND:
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return rewriteValuePPC64latelower_OpPPC64AND(v)
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case OpPPC64ISEL:
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return rewriteValuePPC64latelower_OpPPC64ISEL(v)
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case OpPPC64RLDICL:
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return rewriteValuePPC64latelower_OpPPC64RLDICL(v)
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case OpPPC64SETBC:
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return rewriteValuePPC64latelower_OpPPC64SETBC(v)
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case OpPPC64SETBCR:
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@ -15,6 +20,101 @@ func rewriteValuePPC64latelower(v *Value) bool {
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}
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return false
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}
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func rewriteValuePPC64latelower_OpPPC64AND(v *Value) bool {
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v_1 := v.Args[1]
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v_0 := v.Args[0]
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b := v.Block
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typ := &b.Func.Config.Types
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// match: (AND <t> x:(MOVDconst [m]) n)
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// cond: t.Size() <= 2
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// result: (Select0 (ANDCCconst [int64(int16(m))] n))
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for {
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t := v.Type
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for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
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x := v_0
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if x.Op != OpPPC64MOVDconst {
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continue
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}
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m := auxIntToInt64(x.AuxInt)
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n := v_1
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if !(t.Size() <= 2) {
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continue
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}
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v.reset(OpSelect0)
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v0 := b.NewValue0(v.Pos, OpPPC64ANDCCconst, types.NewTuple(typ.Int, types.TypeFlags))
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v0.AuxInt = int64ToAuxInt(int64(int16(m)))
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v0.AddArg(n)
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v.AddArg(v0)
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return true
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}
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break
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}
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// match: (AND x:(MOVDconst [m]) n)
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// cond: isPPC64ValidShiftMask(m)
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// result: (RLDICL [encodePPC64RotateMask(0,m,64)] n)
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for {
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for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
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x := v_0
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if x.Op != OpPPC64MOVDconst {
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continue
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}
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m := auxIntToInt64(x.AuxInt)
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n := v_1
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if !(isPPC64ValidShiftMask(m)) {
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continue
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}
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v.reset(OpPPC64RLDICL)
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v.AuxInt = int64ToAuxInt(encodePPC64RotateMask(0, m, 64))
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v.AddArg(n)
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return true
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}
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break
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}
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// match: (AND x:(MOVDconst [m]) n)
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// cond: m != 0 && isPPC64ValidShiftMask(^m)
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// result: (RLDICR [encodePPC64RotateMask(0,m,64)] n)
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for {
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for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
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x := v_0
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if x.Op != OpPPC64MOVDconst {
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continue
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}
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m := auxIntToInt64(x.AuxInt)
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n := v_1
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if !(m != 0 && isPPC64ValidShiftMask(^m)) {
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continue
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}
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v.reset(OpPPC64RLDICR)
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v.AuxInt = int64ToAuxInt(encodePPC64RotateMask(0, m, 64))
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v.AddArg(n)
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return true
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}
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break
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}
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// match: (AND <t> x:(MOVDconst [m]) n)
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// cond: t.Size() == 4 && isPPC64WordRotateMask(m)
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// result: (RLWINM [encodePPC64RotateMask(0,m,32)] n)
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for {
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t := v.Type
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for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
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x := v_0
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if x.Op != OpPPC64MOVDconst {
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continue
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}
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m := auxIntToInt64(x.AuxInt)
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n := v_1
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if !(t.Size() == 4 && isPPC64WordRotateMask(m)) {
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continue
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}
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v.reset(OpPPC64RLWINM)
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v.AuxInt = int64ToAuxInt(encodePPC64RotateMask(0, m, 32))
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v.AddArg(n)
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return true
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}
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break
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}
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return false
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}
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func rewriteValuePPC64latelower_OpPPC64ISEL(v *Value) bool {
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v_2 := v.Args[2]
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v_1 := v.Args[1]
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@ -49,6 +149,29 @@ func rewriteValuePPC64latelower_OpPPC64ISEL(v *Value) bool {
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}
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return false
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}
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func rewriteValuePPC64latelower_OpPPC64RLDICL(v *Value) bool {
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v_0 := v.Args[0]
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// match: (RLDICL [em] x:(SRDconst [s] a))
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// cond: (em&0xFF0000)==0
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// result: (RLDICL [mergePPC64RLDICLandSRDconst(em, s)] a)
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for {
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em := auxIntToInt64(v.AuxInt)
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x := v_0
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if x.Op != OpPPC64SRDconst {
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break
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}
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s := auxIntToInt64(x.AuxInt)
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a := x.Args[0]
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if !((em & 0xFF0000) == 0) {
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break
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}
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v.reset(OpPPC64RLDICL)
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v.AuxInt = int64ToAuxInt(mergePPC64RLDICLandSRDconst(em, s))
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v.AddArg(a)
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return true
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}
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return false
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}
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func rewriteValuePPC64latelower_OpPPC64SETBC(v *Value) bool {
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v_0 := v.Args[0]
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b := v.Block
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@ -394,3 +394,29 @@ func zeroextendAndMask8to64(a int8, b int16) (x, y uint64) {
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return
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}
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// Verify rotate and mask instructions, and further simplified instructions for small types
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func bitRotateAndMask(io64 [4]uint64, io32 [4]uint32, io16 [4]uint16, io8 [4]uint8) {
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// ppc64x: "RLDICR\t[$]0, R[0-9]*, [$]47, R"
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io64[0] = io64[0] & 0xFFFFFFFFFFFF0000
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// ppc64x: "RLDICL\t[$]0, R[0-9]*, [$]16, R"
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io64[1] = io64[1] & 0x0000FFFFFFFFFFFF
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// ppc64x: -"SRD", -"AND", "RLDICL\t[$]60, R[0-9]*, [$]16, R"
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io64[2] = (io64[2] >> 4) & 0x0000FFFFFFFFFFFF
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// ppc64x: -"SRD", -"AND", "RLDICL\t[$]36, R[0-9]*, [$]28, R"
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io64[3] = (io64[3] >> 28) & 0x0000FFFFFFFFFFFF
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// ppc64x: "RLWNM\t[$]0, R[0-9]*, [$]4, [$]19, R"
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io32[0] = io32[0] & 0x0FFFF000
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// ppc64x: "RLWNM\t[$]0, R[0-9]*, [$]20, [$]3, R"
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io32[1] = io32[1] & 0xF0000FFF
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// ppc64x: -"RLWNM", MOVD, AND
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io32[2] = io32[2] & 0xFFFF0002
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var bigc uint32 = 0x12345678
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// ppc64x: "ANDCC\t[$]22136"
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io16[0] = io16[0] & uint16(bigc)
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// ppc64x: "ANDCC\t[$]120"
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io8[0] = io8[0] & uint8(bigc)
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}
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