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cmd/compile/internal: add RLDICR opcode for PPC64
This is encoded similarly to RLDICL, but can clear the least significant bits. Likewise, update the auxint encoding of RLDICL to match those used by the rotate and mask word ssa opcodes for easier usage within lowering rules. The RLDICL ssa opcode is not used yet. Change-Id: I42486dd95714a3e8e2f19ab237a6cf3af520c905 Reviewed-on: https://go-review.googlesource.com/c/go/+/515575 Reviewed-by: Lynn Boger <laboger@linux.vnet.ibm.com> Run-TryBot: Paul Murphy <murp@ibm.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> TryBot-Result: Gopher Robot <gobot@golang.org> Reviewed-by: Michael Knyszek <mknyszek@google.com>
This commit is contained in:
Paul E. Murphy
Paul Murphy
parent
756841bffa
commit
41c71d48a1
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@ -573,18 +573,6 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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// Mask has been set as sh
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case ssa.OpPPC64RLDICL:
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r := v.Reg()
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r1 := v.Args[0].Reg()
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shifts := v.AuxInt
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p := s.Prog(v.Op.Asm())
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p.From = obj.Addr{Type: obj.TYPE_CONST, Offset: ssa.GetPPC64Shiftsh(shifts)}
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p.AddRestSourceConst(ssa.GetPPC64Shiftmb(shifts))
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p.Reg = r1
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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case ssa.OpPPC64ADD, ssa.OpPPC64FADD, ssa.OpPPC64FADDS, ssa.OpPPC64SUB, ssa.OpPPC64FSUB, ssa.OpPPC64FSUBS,
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ssa.OpPPC64MULLD, ssa.OpPPC64MULLW, ssa.OpPPC64DIVDU, ssa.OpPPC64DIVWU,
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ssa.OpPPC64SRAD, ssa.OpPPC64SRAW, ssa.OpPPC64SRD, ssa.OpPPC64SRW, ssa.OpPPC64SLD, ssa.OpPPC64SLW,
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@ -623,13 +611,27 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
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// Auxint holds encoded rotate + mask
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case ssa.OpPPC64RLWINM, ssa.OpPPC64RLWMI:
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rot, mb, me, _ := ssa.DecodePPC64RotateMask(v.AuxInt)
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sh, mb, me, _ := ssa.DecodePPC64RotateMask(v.AuxInt)
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p := s.Prog(v.Op.Asm())
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p.To = obj.Addr{Type: obj.TYPE_REG, Reg: v.Reg()}
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p.Reg = v.Args[0].Reg()
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p.From = obj.Addr{Type: obj.TYPE_CONST, Offset: int64(rot)}
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p.From = obj.Addr{Type: obj.TYPE_CONST, Offset: int64(sh)}
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p.AddRestSourceArgs([]obj.Addr{{Type: obj.TYPE_CONST, Offset: mb}, {Type: obj.TYPE_CONST, Offset: me}})
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// Auxint holds mask
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case ssa.OpPPC64RLDICL, ssa.OpPPC64RLDICR:
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sh, mb, me, _ := ssa.DecodePPC64RotateMask(v.AuxInt)
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p := s.Prog(v.Op.Asm())
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p.From = obj.Addr{Type: obj.TYPE_CONST, Offset: sh}
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switch v.Op {
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case ssa.OpPPC64RLDICL:
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p.AddRestSourceConst(mb)
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case ssa.OpPPC64RLDICR:
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p.AddRestSourceConst(me)
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}
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p.Reg = v.Args[0].Reg()
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p.To = obj.Addr{Type: obj.TYPE_REG, Reg: v.Reg()}
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case ssa.OpPPC64RLWNM:
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_, mb, me, _ := ssa.DecodePPC64RotateMask(v.AuxInt)
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p := s.Prog(v.Op.Asm())
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@ -215,7 +215,6 @@ func init() {
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{name: "ROTLW", argLength: 2, reg: gp21, asm: "ROTLW"}, // uint32(arg0) rotate left by arg1 mod 32
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// The following are ops to implement the extended mnemonics for shifts as described in section C.8 of the ISA.
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// The constant shift values are packed into the aux int32.
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{name: "RLDICL", argLength: 1, reg: gp11, asm: "RLDICL", aux: "Int32"}, // arg0 extract bits identified by shift params"
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{name: "CLRLSLWI", argLength: 1, reg: gp11, asm: "CLRLSLWI", aux: "Int32"}, //
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{name: "CLRLSLDI", argLength: 1, reg: gp11, asm: "CLRLSLDI", aux: "Int32"}, //
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@ -243,6 +242,8 @@ func init() {
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{name: "RLWINM", argLength: 1, reg: gp11, asm: "RLWNM", aux: "Int64"}, // Rotate and mask by immediate "rlwinm". encodePPC64RotateMask describes aux
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{name: "RLWNM", argLength: 2, reg: gp21, asm: "RLWNM", aux: "Int64"}, // Rotate and mask by "rlwnm". encodePPC64RotateMask describes aux
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{name: "RLWMI", argLength: 2, reg: gp21a0, asm: "RLWMI", aux: "Int64", resultInArg0: true}, // "rlwimi" similar aux encoding as above
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{name: "RLDICL", argLength: 1, reg: gp11, asm: "RLDICL", aux: "Int64"}, // Auxint is encoded similarly to RLWINM, but only MB and SH are valid. ME is always 63.
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{name: "RLDICR", argLength: 1, reg: gp11, asm: "RLDICR", aux: "Int64"}, // Likewise, but only ME and SH are valid. MB is always 0.
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{name: "CNTLZD", argLength: 1, reg: gp11, asm: "CNTLZD", clobberFlags: true}, // count leading zeros
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{name: "CNTLZW", argLength: 1, reg: gp11, asm: "CNTLZW", clobberFlags: true}, // count leading zeros (32 bit)
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@ -2136,7 +2136,6 @@ const (
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OpPPC64SLW
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OpPPC64ROTL
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OpPPC64ROTLW
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OpPPC64RLDICL
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OpPPC64CLRLSLWI
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OpPPC64CLRLSLDI
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OpPPC64ADDC
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@ -2159,6 +2158,8 @@ const (
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OpPPC64RLWINM
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OpPPC64RLWNM
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OpPPC64RLWMI
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OpPPC64RLDICL
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OpPPC64RLDICR
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OpPPC64CNTLZD
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OpPPC64CNTLZW
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OpPPC64CNTTZD
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@ -28661,20 +28662,6 @@ var opcodeTable = [...]opInfo{
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},
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},
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},
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{
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name: "RLDICL",
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auxType: auxInt32,
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argLen: 1,
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asm: ppc64.ARLDICL,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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outputs: []outputInfo{
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{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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},
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},
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{
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name: "CLRLSLWI",
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auxType: auxInt32,
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@ -29002,6 +28989,34 @@ var opcodeTable = [...]opInfo{
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},
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},
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},
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{
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name: "RLDICL",
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auxType: auxInt64,
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argLen: 1,
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asm: ppc64.ARLDICL,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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outputs: []outputInfo{
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{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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},
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},
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{
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name: "RLDICR",
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auxType: auxInt64,
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argLen: 1,
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asm: ppc64.ARLDICR,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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outputs: []outputInfo{
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{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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},
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},
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{
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name: "CNTLZD",
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argLen: 1,
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