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cmd/internal/obj/ppc64: add ISA 3.1 instructions
Use ppc64map (from x/arch) to generate ISA 3.1 support for the assembler. A new file asm9_gtables.go is added which contains generated code to encode ISA 3.1 instructions, a function to assist filling out the oprange structure, a lookup table for the fixed bits of each instructions, and a slice of string name. Generated functions are shared if their bitwise encoding match, and the translation from an obj.Prog structure matches. The generated file is entirely self-contained, and does not require regenerating any other files for changes within it. If opcodes in a.out.go are reordered or changed, anames.go must be updated in the same way as before. Future improvements could shrink the generated opcode table to 32 bit entries as there is much less variation of the encoding of the prefix word, but it is not always identical for instructions which share a similar encoding of arguments (e.g PLWA and PLWZ). Updates #44549 Change-Id: Ie83fa02497c9ad2280678d68391043d3aae63175 Reviewed-on: https://go-review.googlesource.com/c/go/+/419535 Run-TryBot: Paul Murphy <murp@ibm.com> TryBot-Result: Gopher Robot <gobot@golang.org> Run-TryBot: Jenny Rakoczy <jenny@golang.org> Reviewed-by: Lynn Boger <laboger@linux.vnet.ibm.com> Reviewed-by: Jenny Rakoczy <jenny@golang.org> Reviewed-by: Michael Pratt <mpratt@google.com> Auto-Submit: Jenny Rakoczy <jenny@golang.org>
This commit is contained in:
Paul E. Murphy
Gopher Robot
parent
c075c21ba5
commit
3a067b288e
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@ -377,6 +377,11 @@ func archPPC64(linkArch *obj.LinkArch) *Arch {
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instructions[s] = obj.As(i) + obj.ABasePPC64
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}
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}
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// The opcodes generated by x/arch's ppc64map are listed in
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// a separate slice, add them too.
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for i, s := range ppc64.GenAnames {
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instructions[s] = obj.As(i) + ppc64.AFIRSTGEN
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}
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// Annoying aliases.
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instructions["BR"] = ppc64.ABR
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instructions["BL"] = ppc64.ABL
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@ -455,6 +455,9 @@ func TestLOONG64Encoder(t *testing.T) {
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func TestPPC64EndToEnd(t *testing.T) {
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testEndToEnd(t, "ppc64", "ppc64")
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// The assembler accepts all instructions irrespective of the GOPPC64 value.
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testEndToEnd(t, "ppc64", "ppc64_p10")
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}
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func TestRISCVEndToEnd(t *testing.T) {
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266
src/cmd/asm/internal/asm/testdata/ppc64_p10.s
vendored
Normal file
266
src/cmd/asm/internal/asm/testdata/ppc64_p10.s
vendored
Normal file
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@ -0,0 +1,266 @@
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// Copyright 2022 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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// This contains the valid opcode combinations available
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// in cmd/internal/obj/ppc64/asm9.go which exist for
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// POWER10/ISA 3.1.
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#include "../../../../../runtime/textflag.h"
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TEXT asmtest(SB), DUPOK|NOSPLIT, $0
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BRD R1, R2 // 7c220176
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BRH R1, R2 // 7c2201b6
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BRW R1, R2 // 7c220136
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CFUGED R1, R2, R3 // 7c2311b8
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CNTLZDM R2, R3, R1 // 7c411876
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CNTTZDM R2, R3, R1 // 7c411c76
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DCFFIXQQ V1, F2 // fc400fc4
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DCTFIXQQ F2, V3 // fc6117c4
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LXVKQ $0, VS33 // f03f02d1
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LXVP 12352(R5), VS6 // 18c53040
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LXVPX (R1)(R2), VS4 // 7c820a9a
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LXVRBX (R1)(R2), VS4 // 7c82081a
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LXVRDX (R1)(R2), VS4 // 7c8208da
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LXVRHX (R1)(R2), VS4 // 7c82085a
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LXVRWX (R1)(R2), VS4 // 7c82089a
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MTVSRBM R1, V1 // 10300e42
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MTVSRBMI $5, V1 // 10220015
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MTVSRDM R1, V1 // 10330e42
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MTVSRHM R1, V1 // 10310e42
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MTVSRQM R1, V1 // 10340e42
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MTVSRWM R1, V1 // 10320e42
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PADDI R3, $1234567890, $1, R4 // 06104996388302d2
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PADDI R0, $1234567890, $0, R4 // 06004996388002d2
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PADDI R0, $1234567890, $1, R4 // 06104996388002d2
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PDEPD R1, R2, R3 // 7c231138
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PEXTD R1, R2, R3 // 7c231178
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PLBZ 1234(R1), $0, R3 // 06000000886104d260000000
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// Note, PLD crosses a 64B boundary, and a nop is inserted between PLBZ and PLD
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PLD 1234(R1), $0, R3 // 04000000e46104d2
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PLFD 1234(R1), $0, F3 // 06000000c86104d2
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PLFS 1234567890(R4), $0, F3 // 06004996c06402d2
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PLFS 1234567890(R0), $1, F3 // 06104996c06002d2
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PLHA 1234(R1), $0, R3 // 06000000a86104d2
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PLHZ 1234(R1), $0, R3 // 06000000a06104d2
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PLQ 1234(R1), $0, R4 // 04000000e08104d2
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PLWA 1234(R1), $0, R3 // 04000000a46104d2
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PLWZ 1234567890(R4), $0, R3 // 06004996806402d2
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PLWZ 1234567890(R0), $1, R3 // 06104996806002d2
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PLXSD 1234(R1), $0, V1 // 04000000a82104d2
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PLXSSP 5(R1), $0, V2 // 04000000ac410005
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PLXSSP 5(R0), $1, V2 // 04100000ac400005
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PLXV 12346891(R6), $1, VS44 // 041000bccd86660b
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PLXVP 12345678(R4), $1, VS4 // 041000bce884614e
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PMXVBF16GER2 VS1, VS2, $1, $2, $3, A1 // 0790c012ec811198
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PMXVBF16GER2NN VS1, VS2, $1, $2, $3, A1 // 0790c012ec811790
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PMXVBF16GER2NP VS1, VS2, $1, $2, $3, A1 // 0790c012ec811390
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PMXVBF16GER2PN VS1, VS2, $1, $2, $3, A1 // 0790c012ec811590
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PMXVBF16GER2PP VS1, VS2, $1, $2, $3, A1 // 0790c012ec811190
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PMXVF16GER2 VS1, VS2, $1, $2, $3, A1 // 0790c012ec811098
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PMXVF16GER2NN VS1, VS2, $1, $2, $3, A1 // 0790c012ec811690
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PMXVF16GER2NP VS1, VS2, $1, $2, $3, A1 // 0790c012ec811290
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PMXVF16GER2PN VS1, VS2, $1, $2, $3, A1 // 0790c012ec811490
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PMXVF16GER2PP VS1, VS2, $1, $2, $3, A1 // 0790c012ec811090
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PMXVF32GER VS1, VS2, $1, $2, A1 // 07900012ec8110d8
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PMXVF32GERNN VS1, VS2, $1, $2, A1 // 07900012ec8116d0
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PMXVF32GERNP VS1, VS2, $1, $2, A1 // 07900012ec8112d0
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PMXVF32GERPN VS1, VS2, $1, $2, A1 // 07900012ec8114d0
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PMXVF32GERPP VS1, VS2, $1, $2, A1 // 07900012ec8110d0
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PMXVF64GER VS4, VS2, $1, $2, A1 // 07900018ec8411d8
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PMXVF64GERNN VS4, VS2, $1, $2, A1 // 07900018ec8417d0
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PMXVF64GERNP VS4, VS2, $1, $2, A1 // 07900018ec8413d0
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PMXVF64GERPN VS4, VS2, $1, $2, A1 // 07900018ec8415d0
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PMXVF64GERPP VS4, VS2, $1, $2, A1 // 07900018ec8411d0
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PMXVI16GER2 VS1, VS2, $1, $2, $3, A1 // 0790c012ec811258
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PMXVI16GER2PP VS1, VS2, $1, $2, $3, A1 // 0790c012ec811358
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PMXVI16GER2S VS1, VS2, $1, $2, $3, A1 // 0790c012ec811158
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PMXVI16GER2SPP VS1, VS2, $1, $2, $3, A1 // 0790c012ec811150
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PMXVI4GER8 VS1, VS2, $1, $2, $3, A1 // 07900312ec811118
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PMXVI4GER8PP VS1, VS2, $1, $2, $3, A1 // 07900312ec811110
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PMXVI8GER4 VS1, VS2, $1, $2, $3, A1 // 07903012ec811018
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PMXVI8GER4PP VS1, VS2, $1, $2, $3, A1 // 07903012ec811010
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PMXVI8GER4SPP VS1, VS2, $1, $2, $3, A1 // 07903012ec811318
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PNOP // 0700000000000000
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PSTB R1, $1, 12345678(R2) // 061000bc9822614e
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PSTD R1, $1, 12345678(R2) // 041000bcf422614e
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PSTFD F1, $1, 12345678(R2) // 061000bcd822614e
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PSTFS F1, $1, 123456789(R7) // 0610075bd027cd15
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PSTH R1, $1, 12345678(R2) // 061000bcb022614e
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PSTQ R2, $1, 12345678(R2) // 041000bcf042614e
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PSTW R1, $1, 12345678(R2) // 061000bc9022614e
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PSTW R24, $0, 45(R13) // 06000000930d002d
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PSTXSD V1, $1, 12345678(R2) // 041000bcb822614e
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PSTXSSP V1, $1, 1234567890(R0) // 04104996bc2002d2
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PSTXSSP V1, $1, 1234567890(R1) // 04104996bc2102d2
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PSTXSSP V1, $0, 1234567890(R3) // 04004996bc2302d2
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PSTXV VS6, $1, 1234567890(R5) // 04104996d8c502d2
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PSTXVP VS2, $1, 12345678(R2) // 041000bcf842614e
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PSTXVP VS62, $0, 5555555(R3) // 04000054fbe3c563
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SETBC CR2EQ, R2 // 7c4a0300
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SETBCR CR2LT, R2 // 7c480340
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SETNBC CR2GT, R2 // 7c490380
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SETNBCR CR6SO, R2 // 7c5b03c0
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STXVP VS6, 12352(R5) // 18c53041
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STXVPX VS22, (R1)(R2) // 7ec20b9a
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STXVRBX VS2, (R1)(R2) // 7c42091a
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STXVRDX VS2, (R1)(R2) // 7c4209da
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STXVRHX VS2, (R1)(R2) // 7c42095a
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STXVRWX VS2, (R1)(R2) // 7c42099a
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VCFUGED V1, V2, V3 // 1061154d
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VCLRLB V1, R2, V3 // 1061118d
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VCLRRB V1, R2, V3 // 106111cd
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VCLZDM V1, V2, V3 // 10611784
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VCMPEQUQ V1, V2, V3 // 106111c7
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VCMPEQUQCC V1, V2, V3 // 106115c7
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VCMPGTSQ V1, V2, V3 // 10611387
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VCMPGTSQCC V1, V2, V3 // 10611787
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VCMPGTUQ V1, V2, V3 // 10611287
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VCMPGTUQCC V1, V2, V3 // 10611687
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VCMPSQ V1, V2, CR2 // 11011141
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VCMPUQ V1, V2, CR3 // 11811101
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VCNTMBB V1, $1, R3 // 10790e42
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VCNTMBD V1, $1, R3 // 107f0e42
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VCNTMBH V1, $1, R3 // 107b0e42
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VCNTMBW V1, $1, R3 // 107d0e42
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VCTZDM V1, V2, V3 // 106117c4
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VDIVESD V1, V2, V3 // 106113cb
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VDIVESQ V1, V2, V3 // 1061130b
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VDIVESW V1, V2, V3 // 1061138b
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VDIVEUD V1, V2, V3 // 106112cb
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VDIVEUQ V1, V2, V3 // 1061120b
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VDIVEUW V1, V2, V3 // 1061128b
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VDIVSD V1, V2, V3 // 106111cb
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VDIVSQ V1, V2, V3 // 1061110b
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VDIVSW V1, V2, V3 // 1061118b
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VDIVUD V1, V2, V3 // 106110cb
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VDIVUQ V1, V2, V3 // 1061100b
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VDIVUW V1, V2, V3 // 1061108b
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VEXPANDBM V1, V2 // 10400e42
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VEXPANDDM V1, V2 // 10430e42
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VEXPANDHM V1, V2 // 10410e42
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VEXPANDQM V1, V2 // 10440e42
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VEXPANDWM V1, V2 // 10420e42
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VEXTDDVLX V1, V2, R3, V4 // 108110de
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VEXTDDVRX V1, V2, R3, V4 // 108110df
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VEXTDUBVLX V1, V2, R3, V4 // 108110d8
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VEXTDUBVRX V1, V2, R3, V4 // 108110d9
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VEXTDUHVLX V1, V2, R3, V4 // 108110da
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VEXTDUHVRX V1, V2, R3, V4 // 108110db
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VEXTDUWVLX V1, V2, R3, V4 // 108110dc
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VEXTDUWVRX V1, V2, R5, V3 // 1061115d
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VEXTRACTBM V1, R2 // 10480e42
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VEXTRACTDM V1, R2 // 104b0e42
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VEXTRACTHM V1, R2 // 10490e42
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VEXTRACTQM V1, R2 // 104c0e42
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VEXTRACTWM V1, R6 // 10ca0e42
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VEXTSD2Q V1, V2 // 105b0e02
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VGNB V1, $1, R31 // 13e10ccc
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VINSBLX R1, R2, V3 // 1061120f
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VINSBRX R1, R2, V3 // 1061130f
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VINSBVLX R1, V1, V2 // 1041080f
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VINSBVRX R1, V1, V2 // 1041090f
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VINSD R1, $2, V2 // 104209cf
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VINSDLX R1, R2, V3 // 106112cf
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VINSDRX R1, R2, V3 // 106113cf
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VINSHLX R1, R2, V3 // 1061124f
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VINSHRX R1, R2, V3 // 1061134f
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VINSHVLX R1, V2, V3 // 1061104f
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VINSHVRX R1, V2, V3 // 1061114f
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VINSW R1, $4, V3 // 106408cf
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VINSWLX R1, R2, V3 // 1061128f
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VINSWRX R1, R2, V3 // 1061138f
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VINSWVLX R1, V2, V3 // 1061108f
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VINSWVRX R1, V2, V3 // 1061118f
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VMODSD V1, V2, V3 // 106117cb
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VMODSQ V1, V2, V3 // 1061170b
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VMODSW V1, V2, V3 // 1061178b
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VMODUD V1, V2, V3 // 106116cb
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VMODUQ V1, V2, V3 // 1061160b
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VMODUW V1, V2, V3 // 1061168b
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VMSUMCUD V1, V2, V3, V4 // 108110d7
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VMULESD V1, V2, V3 // 106113c8
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VMULEUD V1, V2, V3 // 106112c8
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VMULHSD V1, V2, V3 // 106113c9
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VMULHSW V1, V2, V3 // 10611389
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VMULHUD V1, V2, V3 // 106112c9
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VMULHUW V1, V2, V3 // 10611289
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VMULLD V1, V2, V3 // 106111c9
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VMULOSD V1, V2, V3 // 106111c8
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VMULOUD V1, V2, V3 // 106110c8
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VPDEPD V1, V2, V3 // 106115cd
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VPEXTD V1, V2, V3 // 1061158d
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VRLQ V1, V2, V3 // 10611005
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VRLQMI V1, V2, V3 // 10611045
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VRLQNM V1, V2, V3 // 10611145
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VSLDBI V1, V2, $3, V3 // 106110d6
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VSLQ V1, V2, V3 // 10611105
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VSRAQ V1, V2, V3 // 10611305
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VSRDBI V1, V2, $3, V4 // 108112d6
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VSRQ V1, V2, V3 // 10611205
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VSTRIBL V1, V2 // 1040080d
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VSTRIBLCC V1, V2 // 10400c0d
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VSTRIBR V1, V2 // 1041080d
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VSTRIBRCC V1, V2 // 10410c0d
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VSTRIHL V1, V2 // 1042080d
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VSTRIHLCC V1, V2 // 10420c0d
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VSTRIHR V1, V2 // 1043080d
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VSTRIHRCC V1, V2 // 10430c0d
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XSCMPEQQP V1, V2, V3 // fc611088
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XSCMPGEQP V1, V2, V3 // fc611188
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XSCMPGTQP V1, V2, V3 // fc6111c8
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XSCVQPSQZ V1, V2 // fc480e88
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XSCVQPUQZ V1, V2 // fc400e88
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XSCVSQQP V1, V2 // fc4b0e88
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XSCVUQQP V2, V3 // fc631688
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XSMAXCQP V1, V2, V3 // fc611548
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XSMINCQP V1, V2, V4 // fc8115c8
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XVBF16GER2 VS1, VS2, A1 // ec811198
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XVBF16GER2NN VS1, VS2, A1 // ec811790
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XVBF16GER2NP VS1, VS2, A1 // ec811390
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XVBF16GER2PN VS1, VS2, A1 // ec811590
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XVBF16GER2PP VS1, VS2, A1 // ec811190
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XVCVBF16SPN VS2, VS3 // f070176c
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XVCVSPBF16 VS1, VS4 // f0910f6c
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XVF16GER2 VS1, VS2, A1 // ec811098
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XVF16GER2NN VS1, VS2, A1 // ec811690
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XVF16GER2NP VS1, VS2, A1 // ec811290
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XVF16GER2PN VS1, VS2, A1 // ec811490
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XVF16GER2PP VS1, VS2, A1 // ec811090
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XVF32GER VS1, VS2, A1 // ec8110d8
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XVF32GERNN VS1, VS2, A1 // ec8116d0
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XVF32GERNP VS1, VS2, A1 // ec8112d0
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XVF32GERPN VS1, VS2, A1 // ec8114d0
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XVF32GERPP VS1, VS2, A1 // ec8110d0
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XVF64GER VS2, VS1, A1 // ec8209d8
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XVF64GERNN VS2, VS1, A1 // ec820fd0
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XVF64GERNP VS2, VS1, A1 // ec820bd0
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XVF64GERPN VS2, VS1, A1 // ec820dd0
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XVF64GERPP VS2, VS1, A1 // ec8209d0
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XVI16GER2 VS1, VS2, A1 // ec811258
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XVI16GER2PP VS1, VS2, A1 // ec811358
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XVI16GER2S VS1, VS2, A1 // ec811158
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XVI16GER2SPP VS1, VS2, A1 // ec811150
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XVI4GER8 VS1, VS2, A1 // ec811118
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XVI4GER8PP VS1, VS2, A1 // ec811110
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XVI8GER4 VS1, VS2, A1 // ec811018
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XVI8GER4PP VS1, VS2, A1 // ec811010
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XVI8GER4SPP VS4, VS6, A1 // ec843318
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XVTLSBB VS1, CR2 // f1020f6c
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XXBLENDVB VS1, VS3, VS7, VS11 // 05000000856119c0
|
||||
XXBLENDVD VS1, VS3, VS7, VS11 // 05000000856119f0
|
||||
XXBLENDVH VS1, VS3, VS7, VS11 // 05000000856119d0
|
||||
XXBLENDVW VS1, VS3, VS7, VS11 // 05000000856119e0
|
||||
XXEVAL VS1, VS2, VS3, $2, VS4 // 05000002888110d0
|
||||
XXGENPCVBM V2, $2, VS3 // f0621728
|
||||
XXGENPCVDM V2, $2, VS3 // f062176a
|
||||
XXGENPCVHM V2, $2, VS3 // f062172a
|
||||
XXGENPCVWM V2, $2, VS3 // f0621768
|
||||
XXMFACC A1 // 7c800162
|
||||
XXMTACC A1 // 7c810162
|
||||
XXPERMX VS1, VS34, VS2, $2, VS3 // 0500000288611082
|
||||
XXSETACCZ A1 // 7c830162
|
||||
XXSPLTI32DX $1, $1234, VS3 // 05000000806204d2
|
||||
XXSPLTIDP $12345678, VS4 // 050000bc8084614e
|
||||
XXSPLTIW $123456, VS3 // 050000018066e240
|
||||
RET
|
||||
|
|
@ -1091,13 +1091,10 @@ const (
|
|||
AXVCVSXWSP
|
||||
AXVCVUXDSP
|
||||
AXVCVUXWSP
|
||||
|
||||
/* ISA 3.1 opcodes */
|
||||
APNOP
|
||||
|
||||
ALAST
|
||||
ALASTAOUT // The last instruction in this list. Also the first opcode generated by ppc64map.
|
||||
|
||||
// aliases
|
||||
ABR = obj.AJMP
|
||||
ABL = obj.ACALL
|
||||
ABR = obj.AJMP
|
||||
ABL = obj.ACALL
|
||||
ALAST = ALASTGEN // The final enumerated instruction value + 1. This is used to size the oprange table.
|
||||
)
|
||||
|
|
|
|||
|
|
@ -615,6 +615,5 @@ var Anames = []string{
|
|||
"XVCVSXWSP",
|
||||
"XVCVUXDSP",
|
||||
"XVCVUXWSP",
|
||||
"PNOP",
|
||||
"LAST",
|
||||
"LASTAOUT",
|
||||
}
|
||||
|
|
|
|||
|
|
@ -74,6 +74,8 @@ type Optab struct {
|
|||
// prefixed instruction. The prefixed instruction should be written first
|
||||
// (e.g when Optab.size > 8).
|
||||
ispfx bool
|
||||
|
||||
asmout func(*ctxt9, *obj.Prog, *Optab, *[5]uint32)
|
||||
}
|
||||
|
||||
// optab contains an array to be sliced of accepted operand combinations for an
|
||||
|
|
@ -524,8 +526,6 @@ var optab = []Optab{
|
|||
{as: ALSW, a1: C_XOREG, a6: C_REG, type_: 45, size: 4},
|
||||
{as: ALSW, a1: C_ZOREG, a3: C_LCON, a6: C_REG, type_: 42, size: 4},
|
||||
|
||||
{as: APNOP, type_: 105, size: 8, ispfx: true},
|
||||
|
||||
{as: obj.AUNDEF, type_: 78, size: 4},
|
||||
{as: obj.APCDATA, a1: C_LCON, a6: C_LCON, type_: 0, size: 0},
|
||||
{as: obj.AFUNCDATA, a1: C_SCON, a6: C_ADDR, type_: 0, size: 0},
|
||||
|
|
@ -536,8 +536,6 @@ var optab = []Optab{
|
|||
{as: obj.ADUFFZERO, a6: C_LBRA, type_: 11, size: 4}, // same as ABR/ABL
|
||||
{as: obj.ADUFFCOPY, a6: C_LBRA, type_: 11, size: 4}, // same as ABR/ABL
|
||||
{as: obj.APCALIGN, a1: C_LCON, type_: 0, size: 0}, // align code
|
||||
|
||||
{as: obj.AXXX, type_: 0, size: 4},
|
||||
}
|
||||
|
||||
var oprange [ALAST & obj.AMask][]Optab
|
||||
|
|
@ -660,7 +658,7 @@ func span9(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) {
|
|||
|
||||
var otxt int64
|
||||
var q *obj.Prog
|
||||
var out [6]uint32
|
||||
var out [5]uint32
|
||||
var falign int32 // Track increased alignment requirements for prefix.
|
||||
for bflag != 0 {
|
||||
bflag = 0
|
||||
|
|
@ -679,7 +677,7 @@ func span9(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) {
|
|||
// and only one extra branch is needed to reach the target.
|
||||
tgt := p.To.Target()
|
||||
p.To.SetTarget(p.Link)
|
||||
c.asmout(p, o, out[:])
|
||||
o.asmout(&c, p, o, &out)
|
||||
p.To.SetTarget(tgt)
|
||||
|
||||
bo := int64(out[0]>>21) & 31
|
||||
|
|
@ -832,7 +830,7 @@ func span9(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) {
|
|||
c.ctxt.Arch.ByteOrder.PutUint32(bp, nop)
|
||||
bp = bp[4:]
|
||||
}
|
||||
c.asmout(p, o, out[:])
|
||||
o.asmout(&c, p, o, &out)
|
||||
for i = 0; i < int32(o.size/4); i++ {
|
||||
c.ctxt.Arch.ByteOrder.PutUint32(bp, out[i])
|
||||
bp = bp[4:]
|
||||
|
|
@ -1206,22 +1204,12 @@ func cmp(a int, b int) bool {
|
|||
return false
|
||||
}
|
||||
|
||||
type ocmp []Optab
|
||||
|
||||
func (x ocmp) Len() int {
|
||||
return len(x)
|
||||
}
|
||||
|
||||
func (x ocmp) Swap(i, j int) {
|
||||
x[i], x[j] = x[j], x[i]
|
||||
}
|
||||
|
||||
// Used when sorting the optab. Sorting is
|
||||
// done in a way so that the best choice of
|
||||
// opcode/operand combination is considered first.
|
||||
func (x ocmp) Less(i, j int) bool {
|
||||
p1 := &x[i]
|
||||
p2 := &x[j]
|
||||
func optabLess(i, j int) bool {
|
||||
p1 := &optab[i]
|
||||
p2 := &optab[j]
|
||||
n := int(p1.as) - int(p2.as)
|
||||
// same opcode
|
||||
if n != 0 {
|
||||
|
|
@ -1278,32 +1266,37 @@ func buildop(ctxt *obj.Link) {
|
|||
return
|
||||
}
|
||||
|
||||
var n int
|
||||
|
||||
for i := 0; i < C_NCLASS; i++ {
|
||||
for n = 0; n < C_NCLASS; n++ {
|
||||
for n := 0; n < C_NCLASS; n++ {
|
||||
if cmp(n, i) {
|
||||
xcmp[i][n] = true
|
||||
}
|
||||
}
|
||||
}
|
||||
for n = 0; optab[n].as != obj.AXXX; n++ {
|
||||
for i := range optab {
|
||||
// Use the legacy assembler function if none provided.
|
||||
if optab[i].asmout == nil {
|
||||
optab[i].asmout = asmout
|
||||
}
|
||||
}
|
||||
sort.Sort(ocmp(optab[:n]))
|
||||
for i := 0; i < n; i++ {
|
||||
// Append the generated entries, sort, and fill out oprange.
|
||||
optab = append(optab, optabGen...)
|
||||
sort.Slice(optab, optabLess)
|
||||
for i := 0; i < len(optab); {
|
||||
r := optab[i].as
|
||||
r0 := r & obj.AMask
|
||||
start := i
|
||||
for optab[i].as == r {
|
||||
for i < len(optab) && optab[i].as == r {
|
||||
i++
|
||||
}
|
||||
oprange[r0] = optab[start:i]
|
||||
i--
|
||||
|
||||
switch r {
|
||||
default:
|
||||
ctxt.Diag("unknown op in build: %v", r)
|
||||
log.Fatalf("instruction missing from switch in asm9.go:buildop: %v", r)
|
||||
if !opsetGen(r) {
|
||||
ctxt.Diag("unknown op in build: %v", r)
|
||||
log.Fatalf("instruction missing from switch in asm9.go:buildop: %v", r)
|
||||
}
|
||||
|
||||
case ADCBF: /* unary indexed: op (b+a); op (b) */
|
||||
opset(ADCBI, r0)
|
||||
|
|
@ -2480,7 +2473,7 @@ func high16adjusted(d int32) uint16 {
|
|||
return uint16(d >> 16)
|
||||
}
|
||||
|
||||
func (c *ctxt9) asmout(p *obj.Prog, o *Optab, out []uint32) {
|
||||
func asmout(c *ctxt9, p *obj.Prog, o *Optab, out *[5]uint32) {
|
||||
o1 := uint32(0)
|
||||
o2 := uint32(0)
|
||||
o3 := uint32(0)
|
||||
|
|
@ -3768,10 +3761,6 @@ func (c *ctxt9) asmout(p *obj.Prog, o *Optab, out []uint32) {
|
|||
case 104: /* VSX mtvsr* instructions, XX1-form RA,RB,XT */
|
||||
o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
|
||||
|
||||
case 105: /* PNOP */
|
||||
o1 = 0x07000000
|
||||
o2 = 0x00000000
|
||||
|
||||
case 106: /* MOVD spr, soreg */
|
||||
v := int32(p.From.Reg)
|
||||
o1 = OPVCC(31, 339, 0, 0) /* mfspr */
|
||||
|
|
|
|||
1616
src/cmd/internal/obj/ppc64/asm9_gtables.go
Normal file
1616
src/cmd/internal/obj/ppc64/asm9_gtables.go
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -36,7 +36,9 @@ import (
|
|||
|
||||
func init() {
|
||||
obj.RegisterRegister(obj.RBasePPC64, REG_SPR0+1024, rconv)
|
||||
obj.RegisterOpcode(obj.ABasePPC64, Anames)
|
||||
// Note, the last entry in Anames is "LASTAOUT", it is not a real opcode.
|
||||
obj.RegisterOpcode(obj.ABasePPC64, Anames[:len(Anames)-1])
|
||||
obj.RegisterOpcode(AFIRSTGEN, GenAnames)
|
||||
}
|
||||
|
||||
func rconv(r int) string {
|
||||
|
|
|
|||
|
|
@ -1382,12 +1382,23 @@ func (c *ctxt9) stacksplit(p *obj.Prog, framesize int32) *obj.Prog {
|
|||
return p
|
||||
}
|
||||
|
||||
// MMA accumulator to/from instructions are slightly ambiguous since
|
||||
// the argument represents both source and destination, specified as
|
||||
// an accumulator. It is treated as a unary destination to simplify
|
||||
// the code generation in ppc64map.
|
||||
var unaryDst = map[obj.As]bool{
|
||||
AXXSETACCZ: true,
|
||||
AXXMTACC: true,
|
||||
AXXMFACC: true,
|
||||
}
|
||||
|
||||
var Linkppc64 = obj.LinkArch{
|
||||
Arch: sys.ArchPPC64,
|
||||
Init: buildop,
|
||||
Preprocess: preprocess,
|
||||
Assemble: span9,
|
||||
Progedit: progedit,
|
||||
UnaryDst: unaryDst,
|
||||
DWARFRegisters: PPC64DWARFRegisters,
|
||||
}
|
||||
|
||||
|
|
@ -1397,5 +1408,6 @@ var Linkppc64le = obj.LinkArch{
|
|||
Preprocess: preprocess,
|
||||
Assemble: span9,
|
||||
Progedit: progedit,
|
||||
UnaryDst: unaryDst,
|
||||
DWARFRegisters: PPC64DWARFRegisters,
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue