mirror of
https://github.com/golang/go
synced 2024-11-02 09:28:34 +00:00
cmd/vendor: update to golang.org/x/arch@5a4828b
This updates master to fix the ppc64 objdump. There were many cases where the Go objdump was generating opcodes that didn't exist in the Go assembler, or generated operands in the wrong order. The goal is to generate a Go objdump that is acceptable to the Go assembler, or as close as possible. An additional change will be needed for the Go objdump tool to make use of this. Change-Id: Ie8d2d534e13b9a64852c99b4b864a9c08ed7e036 Reviewed-on: https://go-review.googlesource.com/c/152517 Reviewed-by: Carlos Eduardo Seo <cseo@linux.vnet.ibm.com> Reviewed-by: Cherry Zhang <cherryyz@google.com> Run-TryBot: Cherry Zhang <cherryyz@google.com> TryBot-Result: Gobot Gobot <gobot@golang.org>
This commit is contained in:
parent
cd47e8944d
commit
162de6b5f0
8 changed files with 941 additions and 760 deletions
2
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/decode.go
generated
vendored
2
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/decode.go
generated
vendored
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@ -172,7 +172,7 @@ func Decode(src []byte, ord binary.ByteOrder) (inst Inst, err error) {
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}
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break
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}
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if inst.Op == 0 {
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if inst.Op == 0 && inst.Enc != 0 {
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return inst, errUnknown
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}
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return inst, nil
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4
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/decode_test.go
generated
vendored
4
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/decode_test.go
generated
vendored
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@ -50,8 +50,8 @@ func TestDecode(t *testing.T) {
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switch syntax {
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case "gnu":
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out = GNUSyntax(inst)
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//case "plan9":
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// out = GoSyntax(inst, 0, nil, nil)
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case "plan9":
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out = GoSyntax(inst, 0, nil)
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default:
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t.Errorf("unknown syntax %q", syntax)
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continue
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8
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/gnu.go
generated
vendored
8
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/gnu.go
generated
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@ -14,8 +14,12 @@ import (
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// This form typically matches the syntax defined in the Power ISA Reference Manual.
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func GNUSyntax(inst Inst) string {
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var buf bytes.Buffer
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if inst.Op == 0 {
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return "error: unkown instruction"
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// When there are all 0s, identify them as the disassembler
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// in binutils would.
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if inst.Enc == 0 {
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return ".long 0x0"
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} else if inst.Op == 0 {
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return "error: unknown instruction"
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}
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buf.WriteString(inst.Op.String())
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sep := " "
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4
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/objdump_test.go
generated
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4
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/objdump_test.go
generated
vendored
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@ -49,11 +49,11 @@ func allowedMismatchObjdump(text string, size int, inst *Inst, dec ExtInst) bool
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switch inst.Op {
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case BC, BCA, BL, BLA, BCL, BCLA, TDI, TWI, TW, TD:
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return true // TODO(minux): we lack the support for extended opcodes here
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case RLWNM, RLWNM_, RLDICL, RLDICL_, RLWINM, RLWINM_, RLDCL, RLDCL_:
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case RLWNM, RLWNMCC, RLDICL, RLDICLCC, RLWINM, RLWINMCC, RLDCL, RLDCLCC:
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return true // TODO(minux): we lack the support for extended opcodes here
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case DCBTST, DCBT:
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return true // objdump uses the embedded argument order, we use the server argument order
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case MTFSF, MTFSF_: // objdump doesn't show the last two arguments
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case MTFSF, MTFSFCC: // objdump doesn't show the last two arguments
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return true
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case VSPLTB, VSPLTH, VSPLTW: // objdump generates unreasonable result "vspltw v6,v19,4" for 10c49a8c, the last 4 should be 0.
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return true
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129
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go
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vendored
129
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go
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@ -19,7 +19,9 @@ func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64)) strin
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if symname == nil {
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symname = func(uint64) (string, uint64) { return "", 0 }
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}
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if inst.Op == 0 {
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if inst.Op == 0 && inst.Enc == 0 {
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return "WORD $0"
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} else if inst.Op == 0 {
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return "?"
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}
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var args []string
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@ -28,13 +30,27 @@ func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64)) strin
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break
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}
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if s := plan9Arg(&inst, i, pc, a, symname); s != "" {
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args = append(args, s)
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// In the case for some BC instructions, a CondReg arg has
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// both the CR and the branch condition encoded in its value.
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// plan9Arg will return a string with the string representation
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// of these values separated by a blank that will be treated
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// as 2 args from this point on.
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if strings.IndexByte(s, ' ') > 0 {
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t := strings.Split(s, " ")
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args = append(args, t[0])
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args = append(args, t[1])
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} else {
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args = append(args, s)
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}
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}
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}
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var op string
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op = plan9OpMap[inst.Op]
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if op == "" {
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op = strings.ToUpper(inst.Op.String())
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if op[len(op)-1] == '.' {
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op = op[:len(op)-1] + "CC"
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}
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}
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// laid out the instruction
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switch inst.Op {
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@ -45,15 +61,60 @@ func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64)) strin
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return fmt.Sprintf("%s %s", op, args[0])
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}
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args = append(args, args[0])
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return op + " " + strings.Join(args[1:], ", ")
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return op + " " + strings.Join(args[1:], ",")
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case SYNC:
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if args[0] == "$1" {
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return "LWSYNC"
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}
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return "HWSYNC"
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case ISEL:
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return "ISEL " + args[3] + "," + args[1] + "," + args[2] + "," + args[0]
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// store instructions always have the memory operand at the end, no need to reorder
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case STB, STBU, STBX, STBUX,
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STH, STHU, STHX, STHUX,
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STW, STWU, STWX, STWUX,
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STD, STDU, STDX, STDUX,
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STQ,
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STHBRX, STWBRX:
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return op + " " + strings.Join(args, ", ")
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// indexed stores handled separately
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case STB, STBU,
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STH, STHU,
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STW, STWU,
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STD, STDU,
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STQ:
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return op + " " + strings.Join(args, ",")
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case CMPD, CMPDI, CMPLD, CMPLDI, CMPW, CMPWI, CMPLW, CMPLWI:
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if len(args) == 2 {
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return op + " " + args[0] + "," + args[1]
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} else if len(args) == 3 {
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return op + " " + args[0] + "," + args[1] + "," + args[2]
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}
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return op + " " + args[0] + " ??"
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case LIS:
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return "ADDIS $0," + args[1] + "," + args[0]
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// store instructions with index registers
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case STBX, STBUX, STHX, STHUX, STWX, STWUX, STDX, STDUX,
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STHBRX, STWBRX, STDBRX, STSWX, STFSX, STFSUX, STFDX, STFDUX, STFIWX, STFDPX:
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return "MOV" + op[2:len(op)-1] + " " + args[0] + ",(" + args[2] + ")(" + args[1] + ")"
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case STDCXCC, STWCXCC, STHCXCC, STBCXCC:
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return op + " " + args[0] + ",(" + args[2] + ")(" + args[1] + ")"
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case STXVD2X, STXVW4X:
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return op + " " + args[0] + ",(" + args[2] + ")(" + args[1] + ")"
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// load instructions with index registers
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case LBZX, LBZUX, LHZX, LHZUX, LWZX, LWZUX, LDX, LDUX,
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LHBRX, LWBRX, LDBRX, LSWX, LFSX, LFSUX, LFDX, LFDUX, LFIWAX, LFIWZX:
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return "MOV" + op[1:len(op)-1] + " (" + args[2] + ")(" + args[1] + ")," + args[0]
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case LDARX, LWARX, LHARX, LBARX:
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return op + " (" + args[2] + ")(" + args[1] + ")," + args[0]
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case LXVD2X, LXVW4X:
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return op + " (" + args[2] + ")(" + args[1] + ")," + args[0]
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case DCBT, DCBTST, DCBZ, DCBST:
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return op + " (" + args[1] + ")"
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// branch instructions needs additional handling
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case BCLR:
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if int(inst.Args[0].(Imm))&20 == 20 { // unconditional
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return op + " " + strings.Join(args, ", ")
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case BC:
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if int(inst.Args[0].(Imm))&0x1c == 12 { // jump on cond bit set
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if len(args) == 4 {
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return fmt.Sprintf("B%s %s,%s", args[1], args[2], args[3])
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}
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return fmt.Sprintf("B%s %s", args[1], args[2])
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} else if int(inst.Args[0].(Imm))&0x1c == 4 && revCondMap[args[1]] != "" { // jump on cond bit not set
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if len(args) == 4 {
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return fmt.Sprintf("B%s %s,%s", revCondMap[args[1]], args[2], args[3])
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}
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return fmt.Sprintf("B%s %s", revCondMap[args[1]], args[2])
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}
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return op + " " + strings.Join(args, ", ")
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return op + " " + strings.Join(args, ",")
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case BCCTR:
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if int(inst.Args[0].(Imm))&20 == 20 { // unconditional
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return "BR (CTR)"
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if int(inst.Args[0].(Imm))&20 == 20 { // unconditional
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return "BL (CTR)"
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}
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return op + " " + strings.Join(args, ", ")
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return op + " " + strings.Join(args, ",")
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case BCA, BCL, BCLA, BCLRL, BCTAR, BCTARL:
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return op + " " + strings.Join(args, ", ")
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return op + " " + strings.Join(args, ",")
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}
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}
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@ -102,6 +169,10 @@ func plan9Arg(inst *Inst, argIndex int, pc uint64, arg Arg, symname func(uint64)
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}
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return strings.ToUpper(arg.String())
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case CondReg:
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// This op is left as its numerical value, not mapped onto CR + condition
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if inst.Op == ISEL {
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return fmt.Sprintf("$%d", (arg - Cond0LT))
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}
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if arg == CR0 && strings.HasPrefix(inst.Op.String(), "cmp") {
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return "" // don't show cr0 for cmp instructions
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} else if arg >= CR0 {
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@ -111,7 +182,7 @@ func plan9Arg(inst *Inst, argIndex int, pc uint64, arg Arg, symname func(uint64)
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if arg <= Cond0SO {
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return bit
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}
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return fmt.Sprintf("4*CR%d+%s", int(arg-Cond0LT)/4, bit)
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return fmt.Sprintf("%s CR%d", bit, int(arg-Cond0LT)/4)
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case Imm:
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return fmt.Sprintf("$%d", arg)
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case SpReg:
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@ -148,25 +219,27 @@ var revCondMap = map[string]string{
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// plan9OpMap maps an Op to its Plan 9 mnemonics, if different than its GNU mnemonics.
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var plan9OpMap = map[Op]string{
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LWARX: "LWAR", STWCX_: "STWCCC",
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LDARX: "LDAR", STDCX_: "STDCCC",
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LHARX: "LHAR", STHCX_: "STHCCC",
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LBARX: "LBAR", STBCX_: "STBCCC",
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ADDI: "ADD",
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ADD_: "ADDCC",
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LBZ: "MOVBZ", STB: "MOVB",
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LBZU: "MOVBZU", STBU: "MOVBU", // TODO(minux): indexed forms are not handled
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LWARX: "LWAR",
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LDARX: "LDAR",
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LHARX: "LHAR",
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LBARX: "LBAR",
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ADDI: "ADD",
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SRADI: "SRAD",
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SUBF: "SUB",
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LI: "MOVD",
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LBZ: "MOVBZ", STB: "MOVB",
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LBZU: "MOVBZU", STBU: "MOVBU",
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LHZ: "MOVHZ", LHA: "MOVH", STH: "MOVH",
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LHZU: "MOVHZU", STHU: "MOVHU",
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LI: "MOVD",
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LIS: "ADDIS",
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LWZ: "MOVWZ", LWA: "MOVW", STW: "MOVW",
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LWZU: "MOVWZU", STWU: "MOVWU",
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LD: "MOVD", STD: "MOVD",
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LDU: "MOVDU", STDU: "MOVDU",
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CMPD: "CMP", CMPDI: "CMP",
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CMPW: "CMPW", CMPWI: "CMPW",
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CMPLD: "CMPU", CMPLDI: "CMPU",
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CMPLW: "CMPWU", CMPLWI: "CMPWU",
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MTSPR: "MOVD", MFSPR: "MOVD", // the width is ambiguous for SPRs
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B: "BR",
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BL: "CALL",
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CMPLD: "CMPU", CMPLW: "CMPWU",
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CMPD: "CMP", CMPW: "CMPW",
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B: "BR",
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BL: "CALL",
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}
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|
|
1495
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go
generated
vendored
1495
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go
generated
vendored
File diff suppressed because it is too large
Load diff
55
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/testdata/decode.txt
generated
vendored
55
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/testdata/decode.txt
generated
vendored
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@ -1,25 +1,56 @@
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6d746162| gnu xoris r20,r11,24930
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6d746162| plan9 XORIS R11,$24930,R20
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4c040000| gnu mcrf cr0,cr1
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88000017| gnu lbz r0,23(0)
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4abaa88a| gnu ba 0xfebaa888
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7d8fc2a6| gnu mfspr r12,783
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||||
00000000| gnu error: unknown instruction
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||||
88a70002| gnu lbz r5,2(r7)
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88a70002| plan9 MOVBZ 2(R7),R5
|
||||
00000000| plan9 WORD $0
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00010000| plan9 error: unknown instruction
|
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00000000| gnu .long 0x0
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00002000| gnu error: unknown instruction
|
||||
a1841e80| gnu lhz r12,7808(r4)
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a1841e80| plan9 MOVHZ 7808(R4),R12
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||||
42093d10| gnu bc 16,4*cr2+gt,.+0x3d10
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e38d5b90| gnu lq r28,23440(r13)
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84127a20| gnu lwzu r0,31264(r18)
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c61bb730| gnu lfsu f16,-18640(r27)
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||||
0825f440| gnu tdi 1,r5,-3008
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a9a912c1| gnu lha r13,4801(r9)
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||||
84127a20| plan9 MOVWZU 31264(R18),R0
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||||
a8630000| gnu lha r3,0(r3)
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a8630000| plan9 MOVH 0(R3),R3
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||||
ebb24fd1| gnu ldu r29,20432(r18)
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||||
ebb24fd1| plan9 MOVDU 20432(R18),R29
|
||||
b1ce0612| gnu sth r14,1554(r14)
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||||
f3c04322| gnu xvcvdpuxws vs30,vs40
|
||||
b1ce0612| plan9 MOVH R14,1554(R14)
|
||||
945c62a2| gnu stwu r2,25250(r28)
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||||
9c8156e3| gnu stbu r4,22243(r1)
|
||||
f91b9c7a| gnu stq r8,-25480(r27)
|
||||
2c1c81b4| gnu cmpwi r28,-32332
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||||
f87b904d| gnu stdu r3,-28596(r27)
|
||||
eab3c832| gnu lwa r21,-14288(r19)
|
||||
2c030001| gnu cmpwi r3,1
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||||
2c030001| plan9 CMPW R3,$1
|
||||
e8610032| gnu lwa r3,48(r1)
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||||
e8610032| plan9 MOVW 48(R1),R3
|
||||
4320336b| gnu bcla 25,lt,0x3368
|
||||
7e40092e| gnu stwx r18,0,r1
|
||||
7e40092e| plan9 MOVW R18,(R1)(0)
|
||||
7c103c2c| gnu lwbrx r0,r16,r7
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||||
7c103c2c| plan9 MOVWBR (R7)(R16),R0
|
||||
7c441d28| gnu stdbrx r2,r4,r3
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||||
7c441d28| plan9 MOVDBR R2,(R3)(R4)
|
||||
3d220001| gnu addis r9,r2,1
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||||
3d220001| plan9 ADDIS R2,$1,R9
|
||||
7ce628ae| gnu lbzx r7,r6,r5
|
||||
7ce628ae| plan9 MOVBZ (R5)(R6),R7
|
||||
7c0e1e99| gnu lxvd2x vs32,r14,r3
|
||||
7c0e1e99| plan9 LXVD2X (R3)(R14),VS32
|
||||
7c00422c| gnu dcbt r0,r8,0
|
||||
7c00422c| plan9 DCBT (R8)
|
||||
7fab3040| gnu cmpld cr7,r11,r6
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||||
7fab3040| plan9 CMPU CR7,R11,R6
|
||||
2c030001| gnu cmpwi r3,1
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||||
2c030001| plan9 CMPW R3,$1
|
||||
7c2b4840| gnu cmpld r11,r9
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||||
7c2b4840| plan9 CMPU R11,R9
|
||||
7c6521ad| gnu stdcx. r3,r5,r4
|
||||
7c6521ad| plan9 STDCXCC R3,(R4)(R5)
|
||||
fbe1ffd1| gnu stdu r31,-48(r1)
|
||||
fbe1ffd1| plan9 MOVDU R31,-48(R1)
|
||||
7c941f19| gnu stxvw4x vs36,r20,r3
|
||||
7c941f19| plan9 STXVW4X VS36,(R3)(R20)
|
||||
7c6520a8| gnu ldarx r3,r5,r4
|
||||
7c6520a8| plan9 LDAR (R4)(R5),R3
|
||||
|
|
4
src/cmd/vendor/vendor.json
vendored
4
src/cmd/vendor/vendor.json
vendored
|
@ -116,8 +116,8 @@
|
|||
},
|
||||
{
|
||||
"path": "golang.org/x/arch/ppc64/ppc64asm",
|
||||
"revision": "5099b4b992f2813e39cfe2623c6f638718bd0fc6",
|
||||
"revisionTime": "2018-04-06T10:28:20Z"
|
||||
"revision": "5a4828bb704534b8a2fa09c791c67d0fb372f472",
|
||||
"revisionTime": "2018-12-03T22:54:21Z"
|
||||
},
|
||||
{
|
||||
"path": "golang.org/x/arch/x86/x86asm",
|
||||
|
|
Loading…
Reference in a new issue