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cmd/compile/internal/amd64: Use 32-bit operands for byte operations
We already generate ADDL for byte operations, reflect this in code. This also allows inc/dec for +-1 operation, which are 1-byte shorter, and enables lea for 3-operand addition/subtraction. Change-Id: Ibfdfee50667ca4cd3c28f72e3dece0c6d114d3ae Reviewed-on: https://go-review.googlesource.com/21251 Reviewed-by: Keith Randall <khr@golang.org> Run-TryBot: Ilya Tocar <ilya.tocar@intel.com> TryBot-Result: Gobot Gobot <gobot@golang.org>
This commit is contained in:
Ilya Tocar
Keith Randall
parent
ffbd31e9f7
commit
036d09d5bf
1 changed files with 20 additions and 38 deletions
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@ -160,7 +160,7 @@ func opregreg(op obj.As, dest, src int16) *obj.Prog {
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func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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s.SetLineno(v.Line)
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switch v.Op {
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case ssa.OpAMD64ADDQ, ssa.OpAMD64ADDL, ssa.OpAMD64ADDW:
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case ssa.OpAMD64ADDQ, ssa.OpAMD64ADDL, ssa.OpAMD64ADDW, ssa.OpAMD64ADDB:
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r := gc.SSARegNum(v)
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r1 := gc.SSARegNum(v.Args[0])
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r2 := gc.SSARegNum(v.Args[1])
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@ -179,12 +179,9 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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p.To.Reg = r
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default:
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var asm obj.As
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switch v.Op {
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case ssa.OpAMD64ADDQ:
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if v.Op == ssa.OpAMD64ADDQ {
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asm = x86.ALEAQ
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case ssa.OpAMD64ADDL:
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asm = x86.ALEAL
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case ssa.OpAMD64ADDW:
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} else {
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asm = x86.ALEAL
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}
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p := gc.Prog(asm)
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@ -196,7 +193,7 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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p.To.Reg = r
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}
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// 2-address opcode arithmetic, symmetric
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case ssa.OpAMD64ADDB, ssa.OpAMD64ADDSS, ssa.OpAMD64ADDSD,
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case ssa.OpAMD64ADDSS, ssa.OpAMD64ADDSD,
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ssa.OpAMD64ANDQ, ssa.OpAMD64ANDL, ssa.OpAMD64ANDW, ssa.OpAMD64ANDB,
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ssa.OpAMD64ORQ, ssa.OpAMD64ORL, ssa.OpAMD64ORW, ssa.OpAMD64ORB,
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ssa.OpAMD64XORQ, ssa.OpAMD64XORL, ssa.OpAMD64XORW, ssa.OpAMD64XORB,
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@ -416,21 +413,20 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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p.From.Reg = gc.SSARegNum(v.Args[1]) // should be CX
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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case ssa.OpAMD64ADDQconst, ssa.OpAMD64ADDLconst, ssa.OpAMD64ADDWconst:
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case ssa.OpAMD64ADDQconst, ssa.OpAMD64ADDLconst, ssa.OpAMD64ADDWconst, ssa.OpAMD64ADDBconst:
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r := gc.SSARegNum(v)
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a := gc.SSARegNum(v.Args[0])
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if r == a {
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if v.AuxInt == 1 {
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var asm obj.As
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switch v.Op {
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// Software optimization manual recommends add $1,reg.
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// But inc/dec is 1 byte smaller. ICC always uses inc
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// Clang/GCC choose depending on flags, but prefer add.
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// Experiments show that inc/dec is both a little faster
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// and make a binary a little smaller.
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case ssa.OpAMD64ADDQconst:
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if v.Op == ssa.OpAMD64ADDQconst {
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asm = x86.AINCQ
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case ssa.OpAMD64ADDLconst, ssa.OpAMD64ADDWconst, ssa.OpAMD64ADDBconst:
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} else {
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asm = x86.AINCL
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}
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p := gc.Prog(asm)
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@ -439,10 +435,9 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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return
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} else if v.AuxInt == -1 {
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var asm obj.As
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switch v.Op {
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case ssa.OpAMD64ADDQconst:
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if v.Op == ssa.OpAMD64ADDQconst {
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asm = x86.ADECQ
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case ssa.OpAMD64ADDLconst, ssa.OpAMD64ADDWconst, ssa.OpAMD64ADDBconst:
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} else {
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asm = x86.ADECL
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}
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p := gc.Prog(asm)
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@ -459,12 +454,9 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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}
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}
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var asm obj.As
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switch v.Op {
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case ssa.OpAMD64ADDQconst:
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if v.Op == ssa.OpAMD64ADDQconst {
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asm = x86.ALEAQ
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case ssa.OpAMD64ADDLconst:
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asm = x86.ALEAL
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case ssa.OpAMD64ADDWconst:
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} else {
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asm = x86.ALEAL
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}
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p := gc.Prog(asm)
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@ -520,7 +512,7 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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//p.From3 = new(obj.Addr)
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//p.From3.Type = obj.TYPE_REG
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//p.From3.Reg = gc.SSARegNum(v.Args[0])
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case ssa.OpAMD64SUBQconst, ssa.OpAMD64SUBLconst, ssa.OpAMD64SUBWconst:
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case ssa.OpAMD64SUBQconst, ssa.OpAMD64SUBLconst, ssa.OpAMD64SUBWconst, ssa.OpAMD64SUBBconst:
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x := gc.SSARegNum(v.Args[0])
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r := gc.SSARegNum(v)
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// We have 3-op add (lea), so transforming a = b - const into
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@ -546,12 +538,9 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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var asm obj.As
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// x = x - (-1) is the same as x++
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// See OpAMD64ADDQconst comments about inc vs add $1,reg
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switch v.Op {
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case ssa.OpAMD64SUBQconst:
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if v.Op == ssa.OpAMD64SUBQconst {
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asm = x86.AINCQ
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case ssa.OpAMD64SUBLconst:
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asm = x86.AINCL
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case ssa.OpAMD64SUBWconst:
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} else {
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asm = x86.AINCL
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}
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p := gc.Prog(asm)
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@ -559,12 +548,9 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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p.To.Reg = r
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} else if x == r && v.AuxInt == 1 {
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var asm obj.As
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switch v.Op {
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case ssa.OpAMD64SUBQconst:
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if v.Op == ssa.OpAMD64SUBQconst {
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asm = x86.ADECQ
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case ssa.OpAMD64SUBLconst:
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asm = x86.ADECL
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case ssa.OpAMD64SUBWconst:
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} else {
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asm = x86.ADECL
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}
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p := gc.Prog(asm)
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@ -572,12 +558,9 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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p.To.Reg = r
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} else {
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var asm obj.As
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switch v.Op {
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case ssa.OpAMD64SUBQconst:
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if v.Op == ssa.OpAMD64SUBQconst {
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asm = x86.ALEAQ
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case ssa.OpAMD64SUBLconst:
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asm = x86.ALEAL
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case ssa.OpAMD64SUBWconst:
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} else {
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asm = x86.ALEAL
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}
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p := gc.Prog(asm)
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@ -588,11 +571,10 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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p.To.Reg = r
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}
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case ssa.OpAMD64ADDBconst,
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ssa.OpAMD64ANDQconst, ssa.OpAMD64ANDLconst, ssa.OpAMD64ANDWconst, ssa.OpAMD64ANDBconst,
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case ssa.OpAMD64ANDQconst, ssa.OpAMD64ANDLconst, ssa.OpAMD64ANDWconst, ssa.OpAMD64ANDBconst,
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ssa.OpAMD64ORQconst, ssa.OpAMD64ORLconst, ssa.OpAMD64ORWconst, ssa.OpAMD64ORBconst,
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ssa.OpAMD64XORQconst, ssa.OpAMD64XORLconst, ssa.OpAMD64XORWconst, ssa.OpAMD64XORBconst,
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ssa.OpAMD64SUBBconst, ssa.OpAMD64SHLQconst, ssa.OpAMD64SHLLconst, ssa.OpAMD64SHLWconst,
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ssa.OpAMD64SHLQconst, ssa.OpAMD64SHLLconst, ssa.OpAMD64SHLWconst,
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ssa.OpAMD64SHLBconst, ssa.OpAMD64SHRQconst, ssa.OpAMD64SHRLconst, ssa.OpAMD64SHRWconst,
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ssa.OpAMD64SHRBconst, ssa.OpAMD64SARQconst, ssa.OpAMD64SARLconst, ssa.OpAMD64SARWconst,
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ssa.OpAMD64SARBconst, ssa.OpAMD64ROLQconst, ssa.OpAMD64ROLLconst, ssa.OpAMD64ROLWconst,
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