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![Ryan Macnak](/assets/img/avatar_default.png)
- Initial and final marking no longer visit all of new-space, reducing the STW pause for major GC. - A scavenge during concurrent marking must forward / filter objects in the marking worklist that are moved / collected, increasing the STW pause for minor GC. - Unreachable intergenerational cycles and weak references are collected in the next mark-sweep instead of first requiring enough scavenges to promote the whole cycle or weak target into old-space. - Artificial minor GCs are no longer needed to avoid memory leaks from back-to-back major GCs. - reachabilityBarrier is now just a count of major GCs. TEST=ci Change-Id: I1e653c9b5d3e02e45b280302c832157a75788db6 Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/345350 Commit-Queue: Ryan Macnak <rmacnak@google.com> Reviewed-by: Siva Annamalai <asiva@google.com>
173 lines
5.6 KiB
C++
173 lines
5.6 KiB
C++
// Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
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// for details. All rights reserved. Use of this source code is governed by a
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// BSD-style license that can be found in the LICENSE file.
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#ifndef RUNTIME_PLATFORM_ATOMIC_H_
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#define RUNTIME_PLATFORM_ATOMIC_H_
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#include <atomic>
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namespace dart {
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// Like std::atomic, but operations default to relaxed ordering instead of
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// sequential consistency.
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template <typename T>
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class RelaxedAtomic {
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public:
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constexpr RelaxedAtomic() : value_() {}
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constexpr RelaxedAtomic(T arg) : value_(arg) {} // NOLINT
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RelaxedAtomic(const RelaxedAtomic& arg) : value_(arg) {} // NOLINT
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T load(std::memory_order order = std::memory_order_relaxed) const {
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return value_.load(order);
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}
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T load(std::memory_order order = std::memory_order_relaxed) const volatile {
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return value_.load(order);
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}
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void store(T arg, std::memory_order order = std::memory_order_relaxed) {
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value_.store(arg, order);
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}
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void store(T arg,
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std::memory_order order = std::memory_order_relaxed) volatile {
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value_.store(arg, order);
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}
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T fetch_add(T arg, std::memory_order order = std::memory_order_relaxed) {
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return value_.fetch_add(arg, order);
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}
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T fetch_sub(T arg, std::memory_order order = std::memory_order_relaxed) {
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return value_.fetch_sub(arg, order);
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}
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T fetch_or(T arg, std::memory_order order = std::memory_order_relaxed) {
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return value_.fetch_or(arg, order);
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}
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T fetch_and(T arg, std::memory_order order = std::memory_order_relaxed) {
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return value_.fetch_and(arg, order);
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}
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T exchange(T arg, std::memory_order order = std::memory_order_relaxed) {
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return value_.exchange(arg, order);
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}
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bool compare_exchange_weak(
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T& expected, // NOLINT
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T desired,
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std::memory_order order = std::memory_order_relaxed) {
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return value_.compare_exchange_weak(expected, desired, order, order);
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}
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bool compare_exchange_weak(
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T& expected, // NOLINT
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T desired,
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std::memory_order order = std::memory_order_relaxed) volatile {
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return value_.compare_exchange_weak(expected, desired, order, order);
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}
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bool compare_exchange_strong(
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T& expected, // NOLINT
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T desired,
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std::memory_order order = std::memory_order_relaxed) {
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return value_.compare_exchange_strong(expected, desired, order, order);
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}
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operator T() const { return load(); }
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T operator=(T arg) {
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store(arg);
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return arg;
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}
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T operator=(const RelaxedAtomic& arg) {
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T loaded_once = arg;
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store(loaded_once);
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return loaded_once;
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}
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T operator+=(T arg) { return fetch_add(arg) + arg; }
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T operator-=(T arg) { return fetch_sub(arg) - arg; }
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T& operator++() { return fetch_add(1) + 1; }
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T& operator--() { return fetch_sub(1) - 1; }
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T operator++(int) { return fetch_add(1); }
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T operator--(int) { return fetch_sub(1); }
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private:
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std::atomic<T> value_;
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};
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// Like std::atomic, but operations default to acquire for load, release for
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// stores, and acquire-release for read-and-updates.
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template <typename T>
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class AcqRelAtomic {
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public:
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constexpr AcqRelAtomic() : value_() {}
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constexpr AcqRelAtomic(T arg) : value_(arg) {} // NOLINT
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AcqRelAtomic(const AcqRelAtomic& arg) = delete;
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T load(std::memory_order order = std::memory_order_acquire) const {
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return value_.load(order);
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}
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void store(T arg, std::memory_order order = std::memory_order_release) {
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value_.store(arg, order);
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}
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T fetch_add(T arg, std::memory_order order = std::memory_order_acq_rel) {
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return value_.fetch_add(arg, order);
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}
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T fetch_sub(T arg, std::memory_order order = std::memory_order_acq_rel) {
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return value_.fetch_sub(arg, order);
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}
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T fetch_or(T arg, std::memory_order order = std::memory_order_acq_rel) {
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return value_.fetch_or(arg, order);
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}
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T fetch_and(T arg, std::memory_order order = std::memory_order_acq_rel) {
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return value_.fetch_and(arg, order);
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}
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bool compare_exchange_weak(
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T& expected, // NOLINT
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T desired,
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std::memory_order success_order = std::memory_order_acq_rel,
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std::memory_order failure_order = std::memory_order_seq_cst) {
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return value_.compare_exchange_weak(expected, desired, success_order,
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failure_order);
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}
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bool compare_exchange_strong(
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T& expected, // NOLINT
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T desired,
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std::memory_order success_order = std::memory_order_acq_rel,
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std::memory_order failure_order = std::memory_order_seq_cst) {
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return value_.compare_exchange_strong(expected, desired, success_order,
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failure_order);
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}
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// Require explicit loads and stores.
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operator T() const = delete;
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T operator=(T arg) = delete;
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T operator=(const AcqRelAtomic& arg) = delete;
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T operator+=(T arg) = delete;
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T operator-=(T arg) = delete;
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private:
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std::atomic<T> value_;
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};
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template <typename T>
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static inline T LoadRelaxed(const T* ptr) {
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static_assert(sizeof(std::atomic<T>) == sizeof(T));
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return reinterpret_cast<const std::atomic<T>*>(ptr)->load(
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std::memory_order_relaxed);
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}
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template <typename T>
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static inline T LoadAcquire(const T* ptr) {
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static_assert(sizeof(std::atomic<T>) == sizeof(T));
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return reinterpret_cast<const std::atomic<T>*>(ptr)->load(
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std::memory_order_acquire);
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}
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template <typename T>
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static inline void StoreRelease(T* ptr, T value) {
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static_assert(sizeof(std::atomic<T>) == sizeof(T));
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reinterpret_cast<std::atomic<T>*>(ptr)->store(value,
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std::memory_order_release);
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}
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} // namespace dart
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#endif // RUNTIME_PLATFORM_ATOMIC_H_
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