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2bfecc160b
TEST=build Change-Id: I2dd8ae69764af27f480a19995b491e98f52476ae Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/293902 Reviewed-by: Liam Appelbe <liama@google.com> Commit-Queue: Ryan Macnak <rmacnak@google.com>
279 lines
8.2 KiB
C++
279 lines
8.2 KiB
C++
// Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
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// for details. All rights reserved. Use of this source code is governed by a
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// BSD-style license that can be found in the LICENSE file.
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// Classes that describe assembly patterns as used by inline caches.
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#ifndef RUNTIME_VM_INSTRUCTIONS_ARM_H_
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#define RUNTIME_VM_INSTRUCTIONS_ARM_H_
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#ifndef RUNTIME_VM_INSTRUCTIONS_H_
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#error Do not include instructions_arm.h directly; use instructions.h instead.
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#endif
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#include "vm/allocation.h"
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#include "vm/constants.h"
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#include "vm/native_function.h"
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#include "vm/tagged_pointer.h"
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#if !defined(DART_PRECOMPILED_RUNTIME)
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#include "vm/compiler/assembler/assembler.h"
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#endif // !defined(DART_PRECOMPILED_RUNTIME)
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namespace dart {
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class ICData;
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class Code;
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class Object;
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class ObjectPool;
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class UntaggedCode;
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class InstructionPattern : public AllStatic {
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public:
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// Decodes a load sequence ending at 'end' (the last instruction of the
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// load sequence is the instruction before the one at end). Returns the
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// address of the first instruction in the sequence. Returns the register
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// being loaded and the loaded immediate value in the output parameters
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// 'reg' and 'value' respectively.
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static uword DecodeLoadWordImmediate(uword end,
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Register* reg,
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intptr_t* value);
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// Encodes a load immediate sequence ending at 'end' (the last instruction of
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// the load sequence is the instruction before the one at end).
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//
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// Supports only a subset of [DecodeLoadWordImmediate], namely:
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// movw r, #lower16
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// movt r, #upper16
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static void EncodeLoadWordImmediate(uword end, Register reg, intptr_t value);
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// Decodes a load sequence ending at 'end' (the last instruction of the
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// load sequence is the instruction before the one at end). Returns the
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// address of the first instruction in the sequence. Returns the register
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// being loaded and the index in the pool being read from in the output
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// parameters 'reg' and 'index' respectively.
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// IMPORTANT: When generating code loading values from pool on ARM use
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// LoadWordFromPool macro instruction instead of emitting direct load.
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// The macro instruction takes care of pool offsets that can't be
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// encoded as immediates.
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static uword DecodeLoadWordFromPool(uword end,
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Register* reg,
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intptr_t* index);
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};
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class CallPattern : public ValueObject {
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public:
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CallPattern(uword pc, const Code& code);
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CodePtr TargetCode() const;
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void SetTargetCode(const Code& code) const;
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private:
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const ObjectPool& object_pool_;
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intptr_t target_code_pool_index_;
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DISALLOW_COPY_AND_ASSIGN(CallPattern);
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};
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class ICCallPattern : public ValueObject {
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public:
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ICCallPattern(uword pc, const Code& code);
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ObjectPtr Data() const;
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void SetData(const Object& data) const;
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CodePtr TargetCode() const;
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void SetTargetCode(const Code& code) const;
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private:
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const ObjectPool& object_pool_;
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intptr_t target_pool_index_;
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intptr_t data_pool_index_;
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DISALLOW_COPY_AND_ASSIGN(ICCallPattern);
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};
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class NativeCallPattern : public ValueObject {
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public:
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NativeCallPattern(uword pc, const Code& code);
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CodePtr target() const;
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void set_target(const Code& target) const;
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NativeFunction native_function() const;
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void set_native_function(NativeFunction target) const;
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private:
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const ObjectPool& object_pool_;
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uword end_;
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intptr_t native_function_pool_index_;
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intptr_t target_code_pool_index_;
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DISALLOW_COPY_AND_ASSIGN(NativeCallPattern);
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};
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// Instance call that can switch between a direct monomorphic call, an IC call,
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// and a megamorphic call.
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// load guarded cid load ICData load MegamorphicCache
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// load monomorphic target <-> load ICLookup stub -> load MMLookup stub
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// call target.entry call stub.entry call stub.entry
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class SwitchableCallPatternBase : public ValueObject {
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public:
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explicit SwitchableCallPatternBase(const ObjectPool& object_pool);
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ObjectPtr data() const;
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void SetData(const Object& data) const;
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protected:
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const ObjectPool& object_pool_;
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intptr_t data_pool_index_;
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intptr_t target_pool_index_;
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private:
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DISALLOW_COPY_AND_ASSIGN(SwitchableCallPatternBase);
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};
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// See [SwitchableCallBase] for a switchable calls in general.
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//
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// The target slot is always a [Code] object: Either the code of the
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// monomorphic function or a stub code.
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class SwitchableCallPattern : public SwitchableCallPatternBase {
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public:
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SwitchableCallPattern(uword pc, const Code& code);
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uword target_entry() const;
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void SetTarget(const Code& target) const;
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private:
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DISALLOW_COPY_AND_ASSIGN(SwitchableCallPattern);
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};
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// See [SwitchableCallBase] for a switchable calls in general.
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//
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// The target slot is always a direct entrypoint address: Either the entry point
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// of the monomorphic function or a stub entry point.
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class BareSwitchableCallPattern : public SwitchableCallPatternBase {
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public:
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explicit BareSwitchableCallPattern(uword pc);
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uword target_entry() const;
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void SetTarget(const Code& target) const;
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private:
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DISALLOW_COPY_AND_ASSIGN(BareSwitchableCallPattern);
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};
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class ReturnPattern : public ValueObject {
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public:
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explicit ReturnPattern(uword pc);
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// bx_lr = 1.
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static constexpr int kLengthInBytes = 1 * Instr::kInstrSize;
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int pattern_length_in_bytes() const { return kLengthInBytes; }
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bool IsValid() const;
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private:
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const uword pc_;
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};
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class PcRelativeCallPatternBase : public ValueObject {
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public:
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// 24 bit signed integer which will get multiplied by 4.
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static constexpr intptr_t kLowerCallingRange =
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-(1 << 25) + Instr::kPCReadOffset;
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static constexpr intptr_t kUpperCallingRange =
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(1 << 25) - Instr::kInstrSize + Instr::kPCReadOffset;
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explicit PcRelativeCallPatternBase(uword pc) : pc_(pc) {}
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static constexpr int kLengthInBytes = 1 * Instr::kInstrSize;
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int32_t distance() {
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#if !defined(DART_PRECOMPILED_RUNTIME)
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return compiler::Assembler::DecodeBranchOffset(
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*reinterpret_cast<int32_t*>(pc_));
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#else
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UNREACHABLE();
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return 0;
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#endif
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}
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void set_distance(int32_t distance) {
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#if !defined(DART_PRECOMPILED_RUNTIME)
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int32_t* word = reinterpret_cast<int32_t*>(pc_);
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*word = compiler::Assembler::EncodeBranchOffset(distance, *word);
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#else
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UNREACHABLE();
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#endif
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}
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protected:
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uword pc_;
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};
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class PcRelativeCallPattern : public PcRelativeCallPatternBase {
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public:
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explicit PcRelativeCallPattern(uword pc) : PcRelativeCallPatternBase(pc) {}
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bool IsValid() const;
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};
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class PcRelativeTailCallPattern : public PcRelativeCallPatternBase {
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public:
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explicit PcRelativeTailCallPattern(uword pc)
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: PcRelativeCallPatternBase(pc) {}
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bool IsValid() const;
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};
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// Instruction pattern for a tail call to a signed 32-bit PC-relative offset
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//
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// The AOT compiler can emit PC-relative calls. If the destination of such a
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// call is not in range for the "bl.<cond> <offset>" instruction, the AOT
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// compiler will emit a trampoline which is in range. That trampoline will
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// then tail-call to the final destination (also via PC-relative offset, but it
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// supports a full signed 32-bit offset).
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//
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// The pattern of the trampoline looks like:
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//
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// movw TMP, #lower16
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// movt TMP, #upper16
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// add PC, PC, TMP lsl #0
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//
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class PcRelativeTrampolineJumpPattern : public ValueObject {
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public:
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explicit PcRelativeTrampolineJumpPattern(uword pattern_start)
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: pattern_start_(pattern_start) {
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USE(pattern_start_);
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}
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static constexpr int kLengthInBytes = 3 * Instr::kInstrSize;
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void Initialize();
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int32_t distance();
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void set_distance(int32_t distance);
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bool IsValid() const;
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private:
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// This offset must be applied to account for the fact that
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// a) the actual "branch" is only in the 3rd instruction
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// b) when reading the PC it reports current instruction + 8
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static constexpr intptr_t kDistanceOffset = -4 * Instr::kInstrSize;
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// add PC, PC, TMP lsl #0
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static constexpr uint32_t kAddPcEncoding =
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(ADD << kOpcodeShift) | (AL << kConditionShift) | (PC << kRnShift) |
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(PC << kRdShift) | (TMP << kRmShift);
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uword pattern_start_;
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};
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} // namespace dart
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#endif // RUNTIME_VM_INSTRUCTIONS_ARM_H_
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