mirror of
https://github.com/dart-lang/sdk
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1618fd965b
Load*Field and Init*Field IL instructions are fused into load instructions with 'calls_initializer' flag. A new, more powerful elimination of lazy initializer calls uses data flow analysis and load forwarding (place numbering). In addition to improved elimination of initializer calls, fusing instructions avoids extra load after field is already loaded for lazy initialization check. Fixes https://github.com/dart-lang/sdk/issues/41417 Change-Id: Ibb2a63f84b9b0c970db67b3d6684ec15384a64e7 Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/148283 Commit-Queue: Alexander Markov <alexmarkov@google.com> Reviewed-by: Martin Kustermann <kustermann@google.com>
970 lines
29 KiB
C++
970 lines
29 KiB
C++
// Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
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// for details. All rights reserved. Use of this source code is governed by a
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// BSD-style license that can be found in the LICENSE file.
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#ifndef RUNTIME_VM_CONSTANTS_ARM_H_
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#define RUNTIME_VM_CONSTANTS_ARM_H_
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#ifndef RUNTIME_VM_CONSTANTS_H_
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#error Do not include constants_arm.h directly; use constants.h instead.
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#endif
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#include "platform/assert.h"
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#include "platform/globals.h"
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#include "vm/constants_base.h"
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namespace dart {
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// We support both VFPv3-D16 and VFPv3-D32 profiles, but currently only one at
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// a time.
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#if defined(__ARM_ARCH_7A__)
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#define VFPv3_D32
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#elif defined(TARGET_ARCH_ARM) && !defined(HOST_ARCH_ARM)
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// If we're running in the simulator, use all 32.
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#define VFPv3_D32
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#else
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#define VFPv3_D16
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#endif
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#if defined(VFPv3_D16) == defined(VFPv3_D32)
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#error "Exactly one of VFPv3_D16 or VFPv3_D32 can be defined at a time."
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#endif
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// The Linux/Android ABI and the iOS ABI differ in their choice of frame
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// pointer, their treatment of R9, and the interprocedural stack alignment.
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// EABI (Linux, Android)
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// See "Procedure Call Standard for the ARM Architecture".
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// R0-R1: Argument / result / volatile
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// R2-R3: Argument / volatile
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// R4-R10: Preserved
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// R11: Frame pointer
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// R12: Volatile
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// R13: Stack pointer
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// R14: Link register
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// R15: Program counter
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// Stack alignment: 4 bytes always, 8 bytes at public interfaces
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// Linux (Debian armhf) and Android also differ in whether floating point
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// arguments are passed in floating point registers. Linux uses hardfp and
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// Android uses softfp. See TargetCPUFeatures::hardfp_supported().
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// iOS ABI
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// See "iOS ABI Function Call Guide"
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// R0-R1: Argument / result / volatile
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// R2-R3: Argument / volatile
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// R4-R6: Preserved
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// R7: Frame pointer
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// R8-R11: Preserved
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// R12: Volatile
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// R13: Stack pointer
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// R14: Link register
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// R15: Program counter
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// Stack alignment: 4 bytes always, 4 bytes at public interfaces
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// iOS passes floating point arguments in integer registers (softfp)
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enum Register {
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R0 = 0,
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R1 = 1,
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R2 = 2,
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R3 = 3,
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R4 = 4,
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R5 = 5, // PP
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R6 = 6, // CODE
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R7 = 7, // iOS FP
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R8 = 8,
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R9 = 9,
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R10 = 10, // THR
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R11 = 11, // Linux FP
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R12 = 12, // IP aka TMP
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R13 = 13, // SP
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R14 = 14, // LR
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R15 = 15, // PC
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kNumberOfCpuRegisters = 16,
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kNoRegister = -1, // Signals an illegal register.
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// Aliases.
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#if defined(TARGET_OS_MACOS) || defined(TARGET_OS_MACOS_IOS)
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FP = R7,
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NOTFP = R11,
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#else
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FP = R11,
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NOTFP = R7,
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#endif
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IP = R12,
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SP = R13,
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LR = R14,
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PC = R15,
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};
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// Values for single-precision floating point registers.
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enum SRegister {
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kNoSRegister = -1,
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S0 = 0,
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S1 = 1,
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S2 = 2,
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S3 = 3,
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S4 = 4,
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S5 = 5,
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S6 = 6,
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S7 = 7,
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S8 = 8,
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S9 = 9,
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S10 = 10,
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S11 = 11,
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S12 = 12,
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S13 = 13,
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S14 = 14,
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S15 = 15,
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S16 = 16,
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S17 = 17,
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S18 = 18,
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S19 = 19,
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S20 = 20,
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S21 = 21,
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S22 = 22,
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S23 = 23,
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S24 = 24,
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S25 = 25,
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S26 = 26,
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S27 = 27,
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S28 = 28,
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S29 = 29,
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S30 = 30,
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S31 = 31,
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kNumberOfSRegisters = 32,
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};
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// Values for double-precision floating point registers.
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enum DRegister {
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kNoDRegister = -1,
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D0 = 0,
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D1 = 1,
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D2 = 2,
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D3 = 3,
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D4 = 4,
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D5 = 5,
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D6 = 6,
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D7 = 7,
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D8 = 8,
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D9 = 9,
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D10 = 10,
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D11 = 11,
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D12 = 12,
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D13 = 13,
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D14 = 14,
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D15 = 15,
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#if defined(VFPv3_D16)
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kNumberOfDRegisters = 16,
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// Leaving these defined, but marking them as kNoDRegister to avoid polluting
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// other parts of the code with #ifdef's. Instead, query kNumberOfDRegisters
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// to see which registers are valid.
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D16 = kNoDRegister,
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D17 = kNoDRegister,
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D18 = kNoDRegister,
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D19 = kNoDRegister,
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D20 = kNoDRegister,
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D21 = kNoDRegister,
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D22 = kNoDRegister,
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D23 = kNoDRegister,
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D24 = kNoDRegister,
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D25 = kNoDRegister,
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D26 = kNoDRegister,
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D27 = kNoDRegister,
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D28 = kNoDRegister,
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D29 = kNoDRegister,
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D30 = kNoDRegister,
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D31 = kNoDRegister,
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#else
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D16 = 16,
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D17 = 17,
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D18 = 18,
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D19 = 19,
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D20 = 20,
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D21 = 21,
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D22 = 22,
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D23 = 23,
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D24 = 24,
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D25 = 25,
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D26 = 26,
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D27 = 27,
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D28 = 28,
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D29 = 29,
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D30 = 30,
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D31 = 31,
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kNumberOfDRegisters = 32,
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#endif
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kNumberOfOverlappingDRegisters = 16,
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};
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enum QRegister {
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kNoQRegister = -1,
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Q0 = 0,
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Q1 = 1,
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Q2 = 2,
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Q3 = 3,
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Q4 = 4,
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Q5 = 5,
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Q6 = 6,
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Q7 = 7,
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#if defined(VFPv3_D16)
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kNumberOfQRegisters = 8,
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Q8 = kNoQRegister,
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Q9 = kNoQRegister,
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Q10 = kNoQRegister,
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Q11 = kNoQRegister,
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Q12 = kNoQRegister,
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Q13 = kNoQRegister,
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Q14 = kNoQRegister,
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Q15 = kNoQRegister,
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#else
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Q8 = 8,
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Q9 = 9,
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Q10 = 10,
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Q11 = 11,
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Q12 = 12,
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Q13 = 13,
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Q14 = 14,
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Q15 = 15,
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kNumberOfQRegisters = 16,
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#endif
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};
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static inline DRegister EvenDRegisterOf(QRegister q) {
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return static_cast<DRegister>(q * 2);
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}
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static inline DRegister OddDRegisterOf(QRegister q) {
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return static_cast<DRegister>((q * 2) + 1);
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}
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static inline SRegister EvenSRegisterOf(DRegister d) {
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#if defined(VFPv3_D32)
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// When we have 32 D registers, the S registers only overlap the first 16.
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// That is, there are only 32 S registers.
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ASSERT(d < D16);
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#endif
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return static_cast<SRegister>(d * 2);
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}
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static inline SRegister OddSRegisterOf(DRegister d) {
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#if defined(VFPv3_D32)
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ASSERT(d < D16);
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#endif
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return static_cast<SRegister>((d * 2) + 1);
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}
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static inline QRegister QRegisterOf(DRegister d) {
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return static_cast<QRegister>(d / 2);
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}
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static inline QRegister QRegisterOf(SRegister s) {
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return static_cast<QRegister>(s / 4);
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}
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static inline DRegister DRegisterOf(SRegister s) {
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return static_cast<DRegister>(s / 2);
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}
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// Register aliases for floating point scratch registers.
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const QRegister QTMP = Q7; // Overlaps with DTMP, STMP.
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const DRegister DTMP = EvenDRegisterOf(QTMP); // Overlaps with STMP.
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const SRegister STMP DART_USED = EvenSRegisterOf(DTMP);
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// Architecture independent aliases.
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typedef QRegister FpuRegister;
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const FpuRegister FpuTMP = QTMP;
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const int kNumberOfFpuRegisters = kNumberOfQRegisters;
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const FpuRegister kNoFpuRegister = kNoQRegister;
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extern const char* cpu_reg_names[kNumberOfCpuRegisters];
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extern const char* fpu_reg_names[kNumberOfFpuRegisters];
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extern const char* fpu_s_reg_names[kNumberOfSRegisters];
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extern const char* fpu_d_reg_names[kNumberOfDRegisters];
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// Register aliases.
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const Register TMP = IP; // Used as scratch register by assembler.
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const Register TMP2 = kNoRegister; // There is no second assembler temporary.
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const Register PP = R5; // Caches object pool pointer in generated code.
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const Register DISPATCH_TABLE_REG = NOTFP; // Dispatch table register.
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const Register SPREG = SP; // Stack pointer register.
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const Register FPREG = FP; // Frame pointer register.
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const Register LRREG = LR; // Link register.
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const Register ARGS_DESC_REG = R4;
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const Register CODE_REG = R6;
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const Register THR = R10; // Caches current thread in generated code.
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const Register CALLEE_SAVED_TEMP = R8;
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// R15 encodes APSR in the vmrs instruction.
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const Register APSR = R15;
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// ABI for catch-clause entry point.
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const Register kExceptionObjectReg = R0;
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const Register kStackTraceObjectReg = R1;
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// ABI for write barrier stub.
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const Register kWriteBarrierObjectReg = R1;
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const Register kWriteBarrierValueReg = R0;
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const Register kWriteBarrierSlotReg = R9;
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// ABI for allocation stubs.
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const Register kAllocationStubTypeArgumentsReg = R3;
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// ABI for instantiation stubs.
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struct InstantiationABI {
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static const Register kUninstantiatedTypeArgumentsReg = R3;
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static const Register kInstantiatorTypeArgumentsReg = R2;
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static const Register kFunctionTypeArgumentsReg = R1;
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static const Register kResultTypeArgumentsReg = R0;
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static const Register kResultTypeReg = R0;
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};
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// Calling convention when calling TypeTestingStub and SubtypeTestCacheStub.
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struct TypeTestABI {
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static const Register kInstanceReg = R0;
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static const Register kDstTypeReg = R8;
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static const Register kInstantiatorTypeArgumentsReg = R2;
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static const Register kFunctionTypeArgumentsReg = R1;
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static const Register kSubtypeTestCacheReg = R3;
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static const intptr_t kAbiRegisters =
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(1 << kInstanceReg) | (1 << kDstTypeReg) |
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(1 << kInstantiatorTypeArgumentsReg) | (1 << kFunctionTypeArgumentsReg) |
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(1 << kSubtypeTestCacheReg);
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// For call to InstanceOfStub.
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static const Register kResultReg = R0;
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};
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// Registers used inside the implementation of type testing stubs.
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struct TTSInternalRegs {
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static const Register kInstanceTypeArgumentsReg = R4;
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static const Register kScratchReg = R9;
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static const intptr_t kInternalRegisters =
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(1 << kInstanceTypeArgumentsReg) | (1 << kScratchReg);
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};
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// ABI for InitStaticFieldStub.
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struct InitStaticFieldABI {
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static const Register kFieldReg = R0;
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static const Register kResultReg = R0;
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};
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// ABI for InitInstanceFieldStub.
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struct InitInstanceFieldABI {
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static const Register kInstanceReg = R1;
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static const Register kFieldReg = R2;
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static const Register kResultReg = R0;
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};
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// Registers used inside the implementation of InitLateInstanceFieldStub.
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struct InitLateInstanceFieldInternalRegs {
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static const Register kFunctionReg = R0;
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static const Register kAddressReg = R3;
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static const Register kScratchReg = R4;
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};
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// ABI for ThrowStub.
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struct ThrowABI {
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static const Register kExceptionReg = R0;
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};
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// ABI for ReThrowStub.
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struct ReThrowABI {
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static const Register kExceptionReg = R0;
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static const Register kStackTraceReg = R1;
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};
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// ABI for AssertBooleanStub.
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struct AssertBooleanABI {
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static const Register kObjectReg = R0;
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};
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// ABI for RangeErrorStub.
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struct RangeErrorABI {
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static const Register kLengthReg = R0;
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static const Register kIndexReg = R1;
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};
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// TODO(regis): Add ABIs for type testing stubs and is-type test stubs instead
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// of reusing the constants of the instantiation stubs ABI.
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// List of registers used in load/store multiple.
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typedef uint16_t RegList;
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const RegList kAllCpuRegistersList = 0xFFFF;
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// C++ ABI call registers.
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const RegList kAbiArgumentCpuRegs =
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(1 << R0) | (1 << R1) | (1 << R2) | (1 << R3);
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#if defined(TARGET_OS_MACOS) || defined(TARGET_OS_MACOS_IOS)
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const RegList kAbiPreservedCpuRegs =
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(1 << R4) | (1 << R5) | (1 << R6) | (1 << R8) | (1 << R10) | (1 << R11);
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const int kAbiPreservedCpuRegCount = 6;
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#else
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const RegList kAbiPreservedCpuRegs = (1 << R4) | (1 << R5) | (1 << R6) |
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(1 << R7) | (1 << R8) | (1 << R9) |
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(1 << R10);
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const int kAbiPreservedCpuRegCount = 7;
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#endif
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const QRegister kAbiFirstPreservedFpuReg = Q4;
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const QRegister kAbiLastPreservedFpuReg = Q7;
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const int kAbiPreservedFpuRegCount = 4;
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const RegList kReservedCpuRegisters = (1 << SPREG) | (1 << FPREG) | (1 << TMP) |
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(1 << PP) | (1 << THR) | (1 << LR) |
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(1 << PC) | (1 << NOTFP);
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constexpr intptr_t kNumberOfReservedCpuRegisters = 8;
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// CPU registers available to Dart allocator.
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constexpr RegList kDartAvailableCpuRegs =
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kAllCpuRegistersList & ~kReservedCpuRegisters;
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constexpr int kNumberOfDartAvailableCpuRegs =
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kNumberOfCpuRegisters - kNumberOfReservedCpuRegisters;
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const intptr_t kStoreBufferWrapperSize = 24;
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// Registers available to Dart that are not preserved by runtime calls.
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const RegList kDartVolatileCpuRegs =
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kDartAvailableCpuRegs & ~kAbiPreservedCpuRegs;
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#if defined(TARGET_OS_MACOS) || defined(TARGET_OS_MACOS_IOS)
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const int kDartVolatileCpuRegCount = 6;
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#else
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const int kDartVolatileCpuRegCount = 5;
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#endif
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const QRegister kDartFirstVolatileFpuReg = Q0;
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const QRegister kDartLastVolatileFpuReg = Q3;
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const int kDartVolatileFpuRegCount = 4;
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#define R(REG) (1 << REG)
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class CallingConventions {
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public:
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static const intptr_t kArgumentRegisters = kAbiArgumentCpuRegs;
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static const Register ArgumentRegisters[];
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static const intptr_t kNumArgRegs = 4;
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static const intptr_t kFpuArgumentRegisters = 0;
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static const FpuRegister FpuArgumentRegisters[];
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static const intptr_t kNumFpuArgRegs = 4;
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static const DRegister FpuDArgumentRegisters[];
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static const intptr_t kNumDFpuArgRegs = 8;
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static const SRegister FpuSArgumentRegisters[];
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static const intptr_t kNumSFpuArgRegs = 16;
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static constexpr bool kArgumentIntRegXorFpuReg = false;
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static constexpr intptr_t kCalleeSaveCpuRegisters = kAbiPreservedCpuRegs;
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// Whether larger than wordsize arguments are aligned to even registers.
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static constexpr AlignmentStrategy kArgumentRegisterAlignment =
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kAlignedToWordSizeBut8AlignedTo8;
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// How stack arguments are aligned.
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static constexpr AlignmentStrategy kArgumentStackAlignment =
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kAlignedToWordSizeBut8AlignedTo8;
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// How fields in composites are aligned.
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#if defined(TARGET_OS_MACOS_IOS)
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static constexpr AlignmentStrategy kFieldAlignment =
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kAlignedToValueSizeBut8AlignedTo4;
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#else
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static constexpr AlignmentStrategy kFieldAlignment = kAlignedToValueSize;
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#endif
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// Whether 1 or 2 byte-sized arguments or return values are passed extended
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// to 4 bytes.
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static constexpr ExtensionStrategy kReturnRegisterExtension = kExtendedTo4;
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static constexpr ExtensionStrategy kArgumentRegisterExtension = kExtendedTo4;
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static constexpr ExtensionStrategy kArgumentStackExtension = kExtendedTo4;
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static constexpr Register kReturnReg = R0;
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static constexpr Register kSecondReturnReg = R1;
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static constexpr FpuRegister kReturnFpuReg = Q0;
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// We choose these to avoid overlap between themselves and reserved registers.
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static constexpr Register kFirstNonArgumentRegister = R8;
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static constexpr Register kSecondNonArgumentRegister = R9;
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static constexpr Register kFirstCalleeSavedCpuReg = R4;
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static constexpr Register kStackPointerRegister = SPREG;
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};
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#undef R
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// Values for the condition field as defined in section A3.2.
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enum Condition {
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kNoCondition = -1,
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EQ = 0, // equal
|
|
NE = 1, // not equal
|
|
CS = 2, // carry set/unsigned higher or same
|
|
CC = 3, // carry clear/unsigned lower
|
|
MI = 4, // minus/negative
|
|
PL = 5, // plus/positive or zero
|
|
VS = 6, // overflow
|
|
VC = 7, // no overflow
|
|
HI = 8, // unsigned higher
|
|
LS = 9, // unsigned lower or same
|
|
GE = 10, // signed greater than or equal
|
|
LT = 11, // signed less than
|
|
GT = 12, // signed greater than
|
|
LE = 13, // signed less than or equal
|
|
AL = 14, // always (unconditional)
|
|
kSpecialCondition = 15, // special condition (refer to section A3.2.1)
|
|
kNumberOfConditions = 16,
|
|
|
|
// Platform-independent variants declared for all platforms
|
|
EQUAL = EQ,
|
|
ZERO = EQUAL,
|
|
NOT_EQUAL = NE,
|
|
NOT_ZERO = NOT_EQUAL,
|
|
LESS = LT,
|
|
LESS_EQUAL = LE,
|
|
GREATER_EQUAL = GE,
|
|
GREATER = GT,
|
|
UNSIGNED_LESS = CC,
|
|
UNSIGNED_LESS_EQUAL = LS,
|
|
UNSIGNED_GREATER = HI,
|
|
UNSIGNED_GREATER_EQUAL = CS,
|
|
OVERFLOW = VS,
|
|
NO_OVERFLOW = VC,
|
|
|
|
kInvalidCondition = 16
|
|
};
|
|
|
|
static inline Condition InvertCondition(Condition c) {
|
|
COMPILE_ASSERT((EQ ^ NE) == 1);
|
|
COMPILE_ASSERT((CS ^ CC) == 1);
|
|
COMPILE_ASSERT((MI ^ PL) == 1);
|
|
COMPILE_ASSERT((VS ^ VC) == 1);
|
|
COMPILE_ASSERT((HI ^ LS) == 1);
|
|
COMPILE_ASSERT((GE ^ LT) == 1);
|
|
COMPILE_ASSERT((GT ^ LE) == 1);
|
|
ASSERT(c != AL);
|
|
ASSERT(c != kSpecialCondition);
|
|
ASSERT(c != kInvalidCondition);
|
|
return static_cast<Condition>(c ^ 1);
|
|
}
|
|
|
|
// Opcodes for Data-processing instructions (instructions with a type 0 and 1)
|
|
// as defined in section A3.4
|
|
enum Opcode {
|
|
kNoOperand = -1,
|
|
AND = 0, // Logical AND
|
|
EOR = 1, // Logical Exclusive OR
|
|
SUB = 2, // Subtract
|
|
RSB = 3, // Reverse Subtract
|
|
ADD = 4, // Add
|
|
ADC = 5, // Add with Carry
|
|
SBC = 6, // Subtract with Carry
|
|
RSC = 7, // Reverse Subtract with Carry
|
|
TST = 8, // Test
|
|
TEQ = 9, // Test Equivalence
|
|
CMP = 10, // Compare
|
|
CMN = 11, // Compare Negated
|
|
ORR = 12, // Logical (inclusive) OR
|
|
MOV = 13, // Move
|
|
BIC = 14, // Bit Clear
|
|
MVN = 15, // Move Not
|
|
kMaxOperand = 16
|
|
};
|
|
|
|
// Shifter types for Data-processing operands as defined in section A5.1.2.
|
|
enum Shift {
|
|
kNoShift = -1,
|
|
LSL = 0, // Logical shift left
|
|
LSR = 1, // Logical shift right
|
|
ASR = 2, // Arithmetic shift right
|
|
ROR = 3, // Rotate right
|
|
kMaxShift = 4
|
|
};
|
|
|
|
// Constants used for the decoding or encoding of the individual fields of
|
|
// instructions. Based on the "Figure 3-1 ARM instruction set summary".
|
|
enum InstructionFields {
|
|
kConditionShift = 28,
|
|
kConditionBits = 4,
|
|
kTypeShift = 25,
|
|
kTypeBits = 3,
|
|
kLinkShift = 24,
|
|
kLinkBits = 1,
|
|
kUShift = 23,
|
|
kUBits = 1,
|
|
kOpcodeShift = 21,
|
|
kOpcodeBits = 4,
|
|
kSShift = 20,
|
|
kSBits = 1,
|
|
kRnShift = 16,
|
|
kRnBits = 4,
|
|
kRdShift = 12,
|
|
kRdBits = 4,
|
|
kRsShift = 8,
|
|
kRsBits = 4,
|
|
kRmShift = 0,
|
|
kRmBits = 4,
|
|
|
|
// Immediate instruction fields encoding.
|
|
kRotateShift = 8,
|
|
kRotateBits = 4,
|
|
kImmed8Shift = 0,
|
|
kImmed8Bits = 8,
|
|
|
|
// Shift instruction register fields encodings.
|
|
kShiftImmShift = 7,
|
|
kShiftRegisterShift = 8,
|
|
kShiftImmBits = 5,
|
|
kShiftShift = 5,
|
|
kShiftBits = 2,
|
|
|
|
// Load/store instruction offset field encoding.
|
|
kOffset12Shift = 0,
|
|
kOffset12Bits = 12,
|
|
kOffset12Mask = 0x00000fff,
|
|
|
|
// Mul instruction register field encodings.
|
|
kMulRdShift = 16,
|
|
kMulRdBits = 4,
|
|
kMulRnShift = 12,
|
|
kMulRnBits = 4,
|
|
|
|
// Div instruction register field encodings.
|
|
kDivRdShift = 16,
|
|
kDivRdBits = 4,
|
|
kDivRmShift = 8,
|
|
kDivRmBits = 4,
|
|
kDivRnShift = 0,
|
|
kDivRnBits = 4,
|
|
|
|
// ldrex/strex register field encodings.
|
|
kLdExRnShift = 16,
|
|
kLdExRtShift = 12,
|
|
kStrExRnShift = 16,
|
|
kStrExRdShift = 12,
|
|
kStrExRtShift = 0,
|
|
|
|
// MRC instruction offset field encoding.
|
|
kCRmShift = 0,
|
|
kCRmBits = 4,
|
|
kOpc2Shift = 5,
|
|
kOpc2Bits = 3,
|
|
kCoprocShift = 8,
|
|
kCoprocBits = 4,
|
|
kCRnShift = 16,
|
|
kCRnBits = 4,
|
|
kOpc1Shift = 21,
|
|
kOpc1Bits = 3,
|
|
|
|
kBranchOffsetMask = 0x00ffffff
|
|
};
|
|
|
|
// The class Instr enables access to individual fields defined in the ARM
|
|
// architecture instruction set encoding as described in figure A3-1.
|
|
//
|
|
// Example: Test whether the instruction at ptr sets the condition code bits.
|
|
//
|
|
// bool InstructionSetsConditionCodes(byte* ptr) {
|
|
// Instr* instr = Instr::At(ptr);
|
|
// int type = instr->TypeField();
|
|
// return ((type == 0) || (type == 1)) && instr->HasS();
|
|
// }
|
|
//
|
|
class Instr {
|
|
public:
|
|
enum { kInstrSize = 4, kInstrSizeLog2 = 2, kPCReadOffset = 8 };
|
|
|
|
static const int32_t kNopInstruction = // nop
|
|
((AL << kConditionShift) | (0x32 << 20) | (0xf << 12));
|
|
|
|
static const int32_t kBreakPointCode = 0xdeb0; // For breakpoint.
|
|
static const int32_t kSimulatorBreakCode = 0xdeb2; // For breakpoint in sim.
|
|
static const int32_t kSimulatorRedirectCode = 0xca11; // For redirection.
|
|
|
|
// Breakpoint instruction filling assembler code buffers in debug mode.
|
|
static const int32_t kBreakPointInstruction = // bkpt(0xdeb0)
|
|
((AL << kConditionShift) | (0x12 << 20) | (0xdeb << 8) | (0x7 << 4));
|
|
|
|
// Breakpoint instruction used by the simulator.
|
|
// Should be distinct from kBreakPointInstruction and from a typical user
|
|
// breakpoint inserted in generated code for debugging, e.g. bkpt(0).
|
|
static const int32_t kSimulatorBreakpointInstruction =
|
|
// svc #kBreakpointSvcCode
|
|
((AL << kConditionShift) | (0xf << 24) | kSimulatorBreakCode);
|
|
|
|
// Runtime call redirection instruction used by the simulator.
|
|
static const int32_t kSimulatorRedirectInstruction =
|
|
((AL << kConditionShift) | (0xf << 24) | kSimulatorRedirectCode);
|
|
|
|
// Get the raw instruction bits.
|
|
inline int32_t InstructionBits() const {
|
|
return *reinterpret_cast<const int32_t*>(this);
|
|
}
|
|
|
|
// Set the raw instruction bits to value.
|
|
inline void SetInstructionBits(int32_t value) {
|
|
*reinterpret_cast<int32_t*>(this) = value;
|
|
}
|
|
|
|
// Read one particular bit out of the instruction bits.
|
|
inline int Bit(int nr) const { return (InstructionBits() >> nr) & 1; }
|
|
|
|
// Read a bit field out of the instruction bits.
|
|
inline int Bits(int shift, int count) const {
|
|
return (InstructionBits() >> shift) & ((1 << count) - 1);
|
|
}
|
|
|
|
// Accessors for the different named fields used in the ARM encoding.
|
|
// The naming of these accessor corresponds to figure A3-1.
|
|
// Generally applicable fields
|
|
inline Condition ConditionField() const {
|
|
return static_cast<Condition>(Bits(kConditionShift, kConditionBits));
|
|
}
|
|
inline int TypeField() const { return Bits(kTypeShift, kTypeBits); }
|
|
|
|
inline Register RnField() const {
|
|
return static_cast<Register>(Bits(kRnShift, kRnBits));
|
|
}
|
|
inline Register RdField() const {
|
|
return static_cast<Register>(Bits(kRdShift, kRdBits));
|
|
}
|
|
|
|
// Fields used in Data processing instructions
|
|
inline Opcode OpcodeField() const {
|
|
return static_cast<Opcode>(Bits(kOpcodeShift, kOpcodeBits));
|
|
}
|
|
inline int SField() const { return Bits(kSShift, kSBits); }
|
|
// with register
|
|
inline Register RmField() const {
|
|
return static_cast<Register>(Bits(kRmShift, kRmBits));
|
|
}
|
|
inline Shift ShiftField() const {
|
|
return static_cast<Shift>(Bits(kShiftShift, kShiftBits));
|
|
}
|
|
inline int RegShiftField() const { return Bit(4); }
|
|
inline Register RsField() const {
|
|
return static_cast<Register>(Bits(kRsShift, kRsBits));
|
|
}
|
|
inline int ShiftAmountField() const {
|
|
return Bits(kShiftImmShift, kShiftImmBits);
|
|
}
|
|
// with immediate
|
|
inline int RotateField() const { return Bits(kRotateShift, kRotateBits); }
|
|
inline int Immed8Field() const { return Bits(kImmed8Shift, kImmed8Bits); }
|
|
|
|
// Fields used in Load/Store instructions
|
|
inline int PUField() const { return Bits(23, 2); }
|
|
inline int BField() const { return Bit(22); }
|
|
inline int WField() const { return Bit(21); }
|
|
inline int LField() const { return Bit(20); }
|
|
// with register uses same fields as Data processing instructions above
|
|
// with immediate
|
|
inline int Offset12Field() const {
|
|
return Bits(kOffset12Shift, kOffset12Bits);
|
|
}
|
|
// multiple
|
|
inline int RlistField() const { return Bits(0, 16); }
|
|
// extra loads and stores
|
|
inline int SignField() const { return Bit(6); }
|
|
inline int HField() const { return Bit(5); }
|
|
inline int ImmedHField() const { return Bits(8, 4); }
|
|
inline int ImmedLField() const { return Bits(0, 4); }
|
|
|
|
// Fields used in Branch instructions
|
|
inline int LinkField() const { return Bits(kLinkShift, kLinkBits); }
|
|
inline int32_t SImmed24Field() const {
|
|
uint32_t bits = InstructionBits();
|
|
return static_cast<int32_t>(bits << 8) >> 8;
|
|
}
|
|
|
|
// Fields used in Supervisor Call instructions
|
|
inline uint32_t SvcField() const { return Bits(0, 24); }
|
|
|
|
// Field used in Breakpoint instruction
|
|
inline uint16_t BkptField() const {
|
|
return ((Bits(8, 12) << 4) | Bits(0, 4));
|
|
}
|
|
|
|
// Field used in 16-bit immediate move instructions
|
|
inline uint16_t MovwField() const {
|
|
return ((Bits(16, 4) << 12) | Bits(0, 12));
|
|
}
|
|
|
|
// Field used in VFP float immediate move instruction
|
|
inline float ImmFloatField() const {
|
|
uint32_t imm32 = (Bit(19) << 31) | (((1 << 5) - Bit(18)) << 25) |
|
|
(Bits(16, 2) << 23) | (Bits(0, 4) << 19);
|
|
return bit_cast<float, uint32_t>(imm32);
|
|
}
|
|
|
|
// Field used in VFP double immediate move instruction
|
|
inline double ImmDoubleField() const {
|
|
uint64_t imm64 = (Bit(19) * (1LL << 63)) | (((1LL << 8) - Bit(18)) << 54) |
|
|
(Bits(16, 2) * (1LL << 52)) | (Bits(0, 4) * (1LL << 48));
|
|
return bit_cast<double, uint64_t>(imm64);
|
|
}
|
|
|
|
inline Register DivRdField() const {
|
|
return static_cast<Register>(Bits(kDivRdShift, kDivRdBits));
|
|
}
|
|
inline Register DivRmField() const {
|
|
return static_cast<Register>(Bits(kDivRmShift, kDivRmBits));
|
|
}
|
|
inline Register DivRnField() const {
|
|
return static_cast<Register>(Bits(kDivRnShift, kDivRnBits));
|
|
}
|
|
|
|
// Test for data processing instructions of type 0 or 1.
|
|
// See "ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition",
|
|
// section A5.1 "ARM instruction set encoding".
|
|
inline bool IsDataProcessing() const {
|
|
ASSERT(ConditionField() != kSpecialCondition);
|
|
ASSERT(Bits(26, 2) == 0); // Type 0 or 1.
|
|
return ((Bits(20, 5) & 0x19) != 0x10) &&
|
|
((Bit(25) == 1) || // Data processing immediate.
|
|
(Bit(4) == 0) || // Data processing register.
|
|
(Bit(7) == 0)); // Data processing register-shifted register.
|
|
}
|
|
|
|
// Tests for special encodings of type 0 instructions (extra loads and stores,
|
|
// as well as multiplications, synchronization primitives, and miscellaneous).
|
|
// Can only be called for a type 0 or 1 instruction.
|
|
inline bool IsMiscellaneous() const {
|
|
ASSERT(Bits(26, 2) == 0); // Type 0 or 1.
|
|
return ((Bit(25) == 0) && ((Bits(20, 5) & 0x19) == 0x10) && (Bit(7) == 0));
|
|
}
|
|
inline bool IsMultiplyOrSyncPrimitive() const {
|
|
ASSERT(Bits(26, 2) == 0); // Type 0 or 1.
|
|
return ((Bit(25) == 0) && (Bits(4, 4) == 9));
|
|
}
|
|
|
|
// Test for Supervisor Call instruction.
|
|
inline bool IsSvc() const {
|
|
return ((InstructionBits() & 0x0f000000) == 0x0f000000);
|
|
}
|
|
|
|
// Test for Breakpoint instruction.
|
|
inline bool IsBkpt() const {
|
|
return ((InstructionBits() & 0x0ff000f0) == 0x01200070);
|
|
}
|
|
|
|
// VFP register fields.
|
|
inline SRegister SnField() const {
|
|
return static_cast<SRegister>((Bits(kRnShift, kRnBits) << 1) + Bit(7));
|
|
}
|
|
inline SRegister SdField() const {
|
|
return static_cast<SRegister>((Bits(kRdShift, kRdBits) << 1) + Bit(22));
|
|
}
|
|
inline SRegister SmField() const {
|
|
return static_cast<SRegister>((Bits(kRmShift, kRmBits) << 1) + Bit(5));
|
|
}
|
|
inline DRegister DnField() const {
|
|
return static_cast<DRegister>(Bits(kRnShift, kRnBits) + (Bit(7) << 4));
|
|
}
|
|
inline DRegister DdField() const {
|
|
return static_cast<DRegister>(Bits(kRdShift, kRdBits) + (Bit(22) << 4));
|
|
}
|
|
inline DRegister DmField() const {
|
|
return static_cast<DRegister>(Bits(kRmShift, kRmBits) + (Bit(5) << 4));
|
|
}
|
|
inline QRegister QnField() const {
|
|
const intptr_t bits = Bits(kRnShift, kRnBits) + (Bit(7) << 4);
|
|
return static_cast<QRegister>(bits >> 1);
|
|
}
|
|
inline QRegister QdField() const {
|
|
const intptr_t bits = Bits(kRdShift, kRdBits) + (Bit(22) << 4);
|
|
return static_cast<QRegister>(bits >> 1);
|
|
}
|
|
inline QRegister QmField() const {
|
|
const intptr_t bits = Bits(kRmShift, kRmBits) + (Bit(5) << 4);
|
|
return static_cast<QRegister>(bits >> 1);
|
|
}
|
|
|
|
inline bool IsDivision() const {
|
|
ASSERT(ConditionField() != kSpecialCondition);
|
|
ASSERT(TypeField() == 3);
|
|
return ((Bit(4) == 1) && (Bits(5, 3) == 0) && (Bit(20) == 1) &&
|
|
(Bits(22, 3) == 4));
|
|
}
|
|
|
|
inline bool IsRbit() const {
|
|
ASSERT(ConditionField() != kSpecialCondition);
|
|
ASSERT(TypeField() == 3);
|
|
return ((Bits(4, 4) == 3) && (Bits(8, 4) == 15) && (Bits(16, 4) == 15) &&
|
|
(Bits(20, 8) == 111));
|
|
}
|
|
|
|
// Test for VFP data processing or single transfer instructions of type 7.
|
|
inline bool IsVFPDataProcessingOrSingleTransfer() const {
|
|
ASSERT(ConditionField() != kSpecialCondition);
|
|
ASSERT(TypeField() == 7);
|
|
return ((Bit(24) == 0) && (Bits(9, 3) == 5));
|
|
// Bit(4) == 0: Data Processing
|
|
// Bit(4) == 1: 8, 16, or 32-bit Transfer between ARM Core and VFP
|
|
}
|
|
|
|
// Test for VFP 64-bit transfer instructions of type 6.
|
|
inline bool IsVFPDoubleTransfer() const {
|
|
ASSERT(ConditionField() != kSpecialCondition);
|
|
ASSERT(TypeField() == 6);
|
|
return ((Bits(21, 4) == 2) && (Bits(9, 3) == 5) &&
|
|
((Bits(4, 4) & 0xd) == 1));
|
|
}
|
|
|
|
// Test for VFP load and store instructions of type 6.
|
|
inline bool IsVFPLoadStore() const {
|
|
ASSERT(ConditionField() != kSpecialCondition);
|
|
ASSERT(TypeField() == 6);
|
|
return ((Bits(20, 5) & 0x12) == 0x10) && (Bits(9, 3) == 5);
|
|
}
|
|
|
|
// Test for VFP multiple load and store instructions of type 6.
|
|
inline bool IsVFPMultipleLoadStore() const {
|
|
ASSERT(ConditionField() != kSpecialCondition);
|
|
ASSERT(TypeField() == 6);
|
|
int32_t puw = (PUField() << 1) | Bit(21); // don't care about D bit
|
|
return (Bits(9, 3) == 5) && ((puw == 2) || (puw == 3) || (puw == 5));
|
|
}
|
|
|
|
inline bool IsSIMDDataProcessing() const {
|
|
ASSERT(ConditionField() == kSpecialCondition);
|
|
return (Bits(25, 3) == 1);
|
|
}
|
|
|
|
inline bool IsSIMDLoadStore() const {
|
|
ASSERT(ConditionField() == kSpecialCondition);
|
|
return (Bits(24, 4) == 4) && (Bit(20) == 0);
|
|
}
|
|
|
|
// Special accessors that test for existence of a value.
|
|
inline bool HasS() const { return SField() == 1; }
|
|
inline bool HasB() const { return BField() == 1; }
|
|
inline bool HasW() const { return WField() == 1; }
|
|
inline bool HasL() const { return LField() == 1; }
|
|
inline bool HasSign() const { return SignField() == 1; }
|
|
inline bool HasH() const { return HField() == 1; }
|
|
inline bool HasLink() const { return LinkField() == 1; }
|
|
|
|
// Instructions are read out of a code stream. The only way to get a
|
|
// reference to an instruction is to convert a pointer. There is no way
|
|
// to allocate or create instances of class Instr.
|
|
// Use the At(pc) function to create references to Instr.
|
|
static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); }
|
|
|
|
private:
|
|
DISALLOW_ALLOCATION();
|
|
DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
|
|
};
|
|
|
|
// Floating-point reciprocal estimate and step (see pages A2-85 and A2-86 of
|
|
// ARM Architecture Reference Manual ARMv7-A edition).
|
|
float ReciprocalEstimate(float op);
|
|
float ReciprocalStep(float op1, float op2);
|
|
|
|
// Floating-point reciprocal square root estimate and step (see pages A2-87 to
|
|
// A2-90 of ARM Architecture Reference Manual ARMv7-A edition).
|
|
float ReciprocalSqrtEstimate(float op);
|
|
float ReciprocalSqrtStep(float op1, float op2);
|
|
|
|
constexpr uword kBreakInstructionFiller = 0xE1200070; // bkpt #0
|
|
constexpr uword kDataMemoryBarrier = 0xf57ff050 | 0xb; // dmb ish
|
|
|
|
} // namespace dart
|
|
|
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#endif // RUNTIME_VM_CONSTANTS_ARM_H_
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