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Refactoring motivation: go/dart-simulated-ffi Change-Id: I219aba2793cfb7d7ea5ecc0a2ab93276c6cbf1e0 Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/97325 Reviewed-by: Samir Jindel <sjindel@google.com>
253 lines
8.2 KiB
C++
253 lines
8.2 KiB
C++
// Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file
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// for details. All rights reserved. Use of this source code is governed by a
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// BSD-style license that can be found in the LICENSE file.
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// Declares a Simulator for ARM64 instructions if we are not generating a native
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// ARM64 binary. This Simulator allows us to run and debug ARM64 code generation
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// on regular desktop machines.
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// Dart calls into generated code by "calling" the InvokeDartCode stub,
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// which will start execution in the Simulator or forwards to the real entry
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// on a ARM64 HW platform.
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#ifndef RUNTIME_VM_SIMULATOR_ARM64_H_
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#define RUNTIME_VM_SIMULATOR_ARM64_H_
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#ifndef RUNTIME_VM_SIMULATOR_H_
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#error Do not include simulator_arm64.h directly; use simulator.h.
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#endif
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#include "vm/constants.h"
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namespace dart {
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class Isolate;
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class Mutex;
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class RawObject;
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class SimulatorSetjmpBuffer;
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class Thread;
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typedef struct {
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union {
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int64_t i64[2];
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int32_t i32[4];
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} bits;
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} simd_value_t;
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class Simulator {
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public:
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static const uword kSimulatorStackUnderflowSize = 64;
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Simulator();
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~Simulator();
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// The currently executing Simulator instance, which is associated to the
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// current isolate
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static Simulator* Current();
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// Accessors for register state.
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// The default value for R31Type has to be R31IsSP because get_register is
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// accessed from architecture independent code through SPREG without
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// specifying the type. We also can't translate a dummy value for SPREG into
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// a real value because the architecture independent code expects SPREG to
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// be a real register value.
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void set_register(Instr* instr,
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Register reg,
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int64_t value,
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R31Type r31t = R31IsSP);
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int64_t get_register(Register reg, R31Type r31t = R31IsSP) const;
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void set_wregister(Register reg, int32_t value, R31Type r31t = R31IsSP);
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int32_t get_wregister(Register reg, R31Type r31t = R31IsSP) const;
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int32_t get_vregisters(VRegister reg, int idx) const;
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void set_vregisters(VRegister reg, int idx, int32_t value);
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int64_t get_vregisterd(VRegister reg, int idx) const;
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void set_vregisterd(VRegister reg, int idx, int64_t value);
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void get_vregister(VRegister reg, simd_value_t* value) const;
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void set_vregister(VRegister reg, const simd_value_t& value);
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int64_t get_sp() const { return get_register(SPREG); }
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int64_t get_pc() const;
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int64_t get_last_pc() const;
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void set_pc(int64_t pc);
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// High address.
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uword stack_base() const { return stack_base_; }
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// Limit for StackOverflowError.
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uword overflow_stack_limit() const { return overflow_stack_limit_; }
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// Low address.
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uword stack_limit() const { return stack_limit_; }
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// Accessor to the instruction counter.
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uint64_t get_icount() const { return icount_; }
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// Call on program start.
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static void Init();
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// Dart generally calls into generated code with 4 parameters. This is a
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// convenience function, which sets up the simulator state and grabs the
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// result on return. The return value is R0. The parameters are placed in
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// R0-3.
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int64_t Call(int64_t entry,
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int64_t parameter0,
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int64_t parameter1,
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int64_t parameter2,
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int64_t parameter3,
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bool fp_return = false,
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bool fp_args = false);
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// Runtime and native call support.
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enum CallKind {
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kRuntimeCall,
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kLeafRuntimeCall,
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kLeafFloatRuntimeCall,
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kBootstrapNativeCall,
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kNativeCall
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};
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static uword RedirectExternalReference(uword function,
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CallKind call_kind,
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int argument_count);
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static uword FunctionForRedirect(uword redirect);
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void JumpToFrame(uword pc, uword sp, uword fp, Thread* thread);
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private:
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// Known bad pc value to ensure that the simulator does not execute
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// without being properly setup.
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static const uword kBadLR = -1;
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// A pc value used to signal the simulator to stop execution. Generally
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// the lr is set to this value on transition from native C code to
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// simulated execution, so that the simulator can "return" to the native
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// C code.
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static const uword kEndSimulatingPC = -2;
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// CPU state.
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int64_t registers_[kNumberOfCpuRegisters];
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bool n_flag_;
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bool z_flag_;
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bool c_flag_;
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bool v_flag_;
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simd_value_t vregisters_[kNumberOfVRegisters];
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// Simulator support.
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int64_t last_pc_;
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int64_t pc_;
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char* stack_;
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uword stack_limit_;
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uword overflow_stack_limit_;
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uword stack_base_;
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bool pc_modified_;
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uint64_t icount_;
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static int64_t flag_stop_sim_at_;
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SimulatorSetjmpBuffer* last_setjmp_buffer_;
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// Registered breakpoints.
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Instr* break_pc_;
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int64_t break_instr_;
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// Illegal memory access support.
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static bool IsIllegalAddress(uword addr) { return addr < 64 * 1024; }
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void HandleIllegalAccess(uword addr, Instr* instr);
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// Handles an unaligned memory access.
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void UnalignedAccess(const char* msg, uword addr, Instr* instr);
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// Handles a legal instruction that the simulator does not implement.
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void UnimplementedInstruction(Instr* instr);
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// Unsupported instructions use Format to print an error and stop execution.
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void Format(Instr* instr, const char* format);
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inline uint8_t ReadBU(uword addr);
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inline int8_t ReadB(uword addr);
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inline void WriteB(uword addr, uint8_t value);
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inline uint16_t ReadHU(uword addr, Instr* instr);
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inline int16_t ReadH(uword addr, Instr* instr);
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inline void WriteH(uword addr, uint16_t value, Instr* instr);
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inline uint32_t ReadWU(uword addr, Instr* instr);
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inline int32_t ReadW(uword addr, Instr* instr);
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inline void WriteW(uword addr, uint32_t value, Instr* instr);
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inline intptr_t ReadX(uword addr, Instr* instr);
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inline void WriteX(uword addr, intptr_t value, Instr* instr);
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// Synchronization primitives support.
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void ClearExclusive();
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intptr_t ReadExclusiveX(uword addr, Instr* instr);
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intptr_t WriteExclusiveX(uword addr, intptr_t value, Instr* instr);
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// 32 bit versions.
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intptr_t ReadExclusiveW(uword addr, Instr* instr);
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intptr_t WriteExclusiveW(uword addr, intptr_t value, Instr* instr);
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// Exclusive access reservation: address and value observed during
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// load-exclusive. Store-exclusive verifies that address is the same and
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// performs atomic compare-and-swap with remembered value to observe value
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// changes. This implementation of ldxr/stxr instructions does not detect
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// ABA situation and our uses of ldxr/stxr don't need this detection.
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uword exclusive_access_addr_;
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uword exclusive_access_value_;
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// Helper functions to set the conditional flags in the architecture state.
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void SetNZFlagsW(int32_t val);
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bool CarryFromW(int32_t left, int32_t right, int32_t carry);
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bool OverflowFromW(int32_t left, int32_t right, int32_t carry);
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void SetNZFlagsX(int64_t val);
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bool CarryFromX(int64_t alu_out, int64_t left, int64_t right, bool addition);
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bool OverflowFromX(int64_t alu_out,
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int64_t left,
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int64_t right,
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bool addition);
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void SetCFlag(bool val);
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void SetVFlag(bool val);
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int64_t ShiftOperand(uint8_t reg_size,
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int64_t value,
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Shift shift_type,
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uint8_t amount);
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int64_t ExtendOperand(uint8_t reg_size,
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int64_t value,
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Extend extend_type,
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uint8_t amount);
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int64_t DecodeShiftExtendOperand(Instr* instr);
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bool ConditionallyExecute(Instr* instr);
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void DoRedirectedCall(Instr* instr);
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// Decode instructions.
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void InstructionDecode(Instr* instr);
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#define DECODE_OP(op) void Decode##op(Instr* instr);
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APPLY_OP_LIST(DECODE_OP)
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#undef DECODE_OP
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// Executes ARM64 instructions until the PC reaches kEndSimulatingPC.
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void Execute();
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// Returns true if tracing of executed instructions is enabled.
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bool IsTracingExecution() const;
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// Longjmp support for exceptions.
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SimulatorSetjmpBuffer* last_setjmp_buffer() { return last_setjmp_buffer_; }
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void set_last_setjmp_buffer(SimulatorSetjmpBuffer* buffer) {
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last_setjmp_buffer_ = buffer;
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}
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friend class SimulatorDebugger;
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friend class SimulatorSetjmpBuffer;
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DISALLOW_COPY_AND_ASSIGN(Simulator);
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};
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} // namespace dart
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#endif // RUNTIME_VM_SIMULATOR_ARM64_H_
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