dart-sdk/runtime/vm/simulator_x64.cc
Ryan Macnak 4f7bb16cc5 [vm] Add a stub simx64.
This allows building gen_snapshot with host=arm64, target=x64.

TEST=ci
Bug: https://github.com/flutter/flutter/issues/103386
Change-Id: I478cc0917462896de9b598455d2ed68401323b50
Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/252962
Reviewed-by: Alexander Aprelev <aam@google.com>
Reviewed-by: Siva Annamalai <asiva@google.com>
Commit-Queue: Ryan Macnak <rmacnak@google.com>
2022-07-29 18:11:01 +00:00

73 lines
1.8 KiB
C++

// Copyright (c) 2022, the Dart project authors. Please see the AUTHORS file
// for details. All rights reserved. Use of this source code is governed by a
// BSD-style license that can be found in the LICENSE file.
#include <setjmp.h> // NOLINT
#include <stdlib.h>
#include "vm/globals.h"
#if defined(TARGET_ARCH_X64)
// Only build the simulator if not compiling for real X64 hardware.
#if defined(USING_SIMULATOR)
#include "vm/simulator.h"
#include "vm/heap/safepoint.h"
#include "vm/isolate.h"
namespace dart {
// Get the active Simulator for the current isolate.
Simulator* Simulator::Current() {
Isolate* isolate = Isolate::Current();
Simulator* simulator = isolate->simulator();
if (simulator == NULL) {
NoSafepointScope no_safepoint;
simulator = new Simulator();
isolate->set_simulator(simulator);
}
return simulator;
}
void Simulator::Init() {}
Simulator::Simulator() {}
Simulator::~Simulator() {
Isolate* isolate = Isolate::Current();
if (isolate != NULL) {
isolate->set_simulator(NULL);
}
}
int64_t Simulator::Call(int64_t entry,
int64_t parameter0,
int64_t parameter1,
int64_t parameter2,
int64_t parameter3,
bool fp_return,
bool fp_args) {
UNIMPLEMENTED();
}
void Simulator::JumpToFrame(uword pc, uword sp, uword fp, Thread* thread) {
UNIMPLEMENTED();
}
uword Simulator::RedirectExternalReference(uword function,
CallKind call_kind,
int argument_count) {
return 0;
}
uword Simulator::FunctionForRedirect(uword redirect) {
return 0;
}
} // namespace dart
#endif // !defined(USING_SIMULATOR)
#endif // defined TARGET_ARCH_RISCV