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![Ryan Macnak](/assets/img/avatar_default.png)
Remove fixed uses of X18. TEST=ci (Linux), speculative (Fuchsia) Change-Id: I20e31fc2ab7d44cbf02e591be92261067158509d Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/244943 Reviewed-by: Alexander Markov <alexmarkov@google.com> Commit-Queue: Ryan Macnak <rmacnak@google.com>
457 lines
14 KiB
C++
457 lines
14 KiB
C++
// Copyright (c) 2021, the Dart project authors. Please see the AUTHORS file
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// for details. All rights reserved. Use of this source code is governed by a
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// BSD-style license that can be found in the LICENSE file.
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#include "vm/globals.h" // Needed here to get TARGET_ARCH_RISCV*.
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#if defined(TARGET_ARCH_RISCV32) || defined(TARGET_ARCH_RISCV64)
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#include "vm/instructions.h"
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#include "vm/instructions_riscv.h"
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#include "vm/constants.h"
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#include "vm/cpu.h"
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#include "vm/object.h"
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#include "vm/object_store.h"
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#include "vm/reverse_pc_lookup_cache.h"
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namespace dart {
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CallPattern::CallPattern(uword pc, const Code& code)
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: object_pool_(ObjectPool::Handle(code.GetObjectPool())),
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target_code_pool_index_(-1) {
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ASSERT(code.ContainsInstructionAt(pc));
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// [lui,add,]lx CODE_REG, ##(pp)
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// xxxxxxxx lx ra, ##(CODE_REG)
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// xxxx jalr ra
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// Last instruction: jalr ra.
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ASSERT(*reinterpret_cast<uint16_t*>(pc - 2) == 0x9082);
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Register reg;
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InstructionPattern::DecodeLoadWordFromPool(pc - 6, ®,
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&target_code_pool_index_);
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ASSERT(reg == CODE_REG);
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}
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ICCallPattern::ICCallPattern(uword pc, const Code& code)
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: object_pool_(ObjectPool::Handle(code.GetObjectPool())),
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target_pool_index_(-1),
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data_pool_index_(-1) {
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ASSERT(code.ContainsInstructionAt(pc));
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// [lui,add,]lx IC_DATA_REG, ##(pp)
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// [lui,add,]lx CODE_REG, ##(pp)
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// xxxxxxxx lx ra, ##(CODE_REG)
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// xxxx jalr ra
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// Last instruction: jalr ra.
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ASSERT(*reinterpret_cast<uint16_t*>(pc - 2) == 0x9082);
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Register reg;
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uword data_load_end = InstructionPattern::DecodeLoadWordFromPool(
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pc - 6, ®, &target_pool_index_);
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ASSERT(reg == CODE_REG);
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InstructionPattern::DecodeLoadWordFromPool(data_load_end, ®,
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&data_pool_index_);
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ASSERT(reg == IC_DATA_REG);
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}
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NativeCallPattern::NativeCallPattern(uword pc, const Code& code)
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: object_pool_(ObjectPool::Handle(code.GetObjectPool())),
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end_(pc),
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native_function_pool_index_(-1),
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target_code_pool_index_(-1) {
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ASSERT(code.ContainsInstructionAt(pc));
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// [lui,add,]lx t5, ##(pp)
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// [lui,add,]lx CODE_REG, ##(pp)
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// xxxxxxxx lx ra, ##(CODE_REG)
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// xxxx jalr ra
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// Last instruction: jalr ra.
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ASSERT(*reinterpret_cast<uint16_t*>(pc - 2) == 0x9082);
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Register reg;
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uword native_function_load_end = InstructionPattern::DecodeLoadWordFromPool(
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pc - 6, ®, &target_code_pool_index_);
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ASSERT(reg == CODE_REG);
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InstructionPattern::DecodeLoadWordFromPool(native_function_load_end, ®,
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&native_function_pool_index_);
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ASSERT(reg == T5);
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}
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CodePtr NativeCallPattern::target() const {
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return static_cast<CodePtr>(object_pool_.ObjectAt(target_code_pool_index_));
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}
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void NativeCallPattern::set_target(const Code& target) const {
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object_pool_.SetObjectAt(target_code_pool_index_, target);
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// No need to flush the instruction cache, since the code is not modified.
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}
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NativeFunction NativeCallPattern::native_function() const {
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return reinterpret_cast<NativeFunction>(
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object_pool_.RawValueAt(native_function_pool_index_));
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}
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void NativeCallPattern::set_native_function(NativeFunction func) const {
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object_pool_.SetRawValueAt(native_function_pool_index_,
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reinterpret_cast<uword>(func));
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}
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// Decodes a load sequence ending at 'end' (the last instruction of the load
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// sequence is the instruction before the one at end). Returns a pointer to
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// the first instruction in the sequence. Returns the register being loaded
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// and the loaded immediate value in the output parameters 'reg' and 'value'
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// respectively.
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uword InstructionPattern::DecodeLoadWordImmediate(uword end,
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Register* reg,
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intptr_t* value) {
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UNIMPLEMENTED();
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return 0;
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}
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static bool DecodeLoadX(uword end,
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Register* dst,
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Register* base,
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intptr_t* offset,
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intptr_t* length) {
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Instr instr(*reinterpret_cast<uint32_t*>(end - 4));
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#if XLEN == 32
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if (instr.opcode() == LOAD && instr.funct3() == LW) {
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#elif XLEN == 64
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if (instr.opcode() == LOAD && instr.funct3() == LD) {
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#endif
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*dst = instr.rd();
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*base = instr.rs1();
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*offset = instr.itype_imm();
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*length = 4;
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return true;
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}
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CInstr cinstr(*reinterpret_cast<uint16_t*>(end - 2));
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#if XLEN == 32
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if (cinstr.opcode() == C_LW) {
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#elif XLEN == 64
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if (cinstr.opcode() == C_LD) {
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#endif
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*dst = cinstr.rdp();
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*base = cinstr.rs1p();
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#if XLEN == 32
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*offset = cinstr.mem4_imm();
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#elif XLEN == 64
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*offset = cinstr.mem8_imm();
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#endif
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*length = 2;
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return true;
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}
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return false;
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}
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static bool DecodeLUI(uword end,
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Register* dst,
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intptr_t* imm,
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intptr_t* length) {
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Instr instr(*reinterpret_cast<uint32_t*>(end - 4));
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if (instr.opcode() == LUI) {
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*dst = instr.rd();
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*imm = instr.utype_imm();
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*length = 4;
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return true;
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}
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CInstr cinstr(*reinterpret_cast<uint16_t*>(end - 2));
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if (cinstr.opcode() == C_LUI) {
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*dst = cinstr.rd();
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*imm = cinstr.u_imm();
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*length = 2;
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return true;
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}
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return false;
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}
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// See comment in instructions_arm64.h
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uword InstructionPattern::DecodeLoadWordFromPool(uword end,
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Register* reg,
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intptr_t* index) {
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// [c.]lx dst, offset(pp)
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// or
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// [c.]lui dst, hi
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// c.add dst, dst, pp
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// [c.]lx dst, lo(dst)
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Register base;
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intptr_t lo, length;
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if (!DecodeLoadX(end, reg, &base, &lo, &length)) {
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UNREACHABLE();
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}
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if (base == PP) {
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// PP is untagged on RISCV.
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*index = ObjectPool::IndexFromOffset(lo - kHeapObjectTag);
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return end - length;
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}
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ASSERT(base == *reg);
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end -= length;
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CInstr add_instr(*reinterpret_cast<uint16_t*>(end - 2));
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ASSERT(add_instr.opcode() ==
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C_MV); // Not C_ADD, which extends past the opcode proper.
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ASSERT(add_instr.rd() == base);
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ASSERT(add_instr.rs1() == base);
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ASSERT(add_instr.rs2() == PP);
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end -= 2;
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Register dst;
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intptr_t hi;
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if (!DecodeLUI(end, &dst, &hi, &length)) {
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UNREACHABLE();
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}
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ASSERT(dst == base);
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// PP is untagged on RISC-V.
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*index = ObjectPool::IndexFromOffset(hi + lo - kHeapObjectTag);
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return end - length;
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}
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bool DecodeLoadObjectFromPoolOrThread(uword pc, const Code& code, Object* obj) {
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ASSERT(code.ContainsInstructionAt(pc));
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uint16_t parcel = *reinterpret_cast<uint16_t*>(pc);
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if (IsCInstruction(parcel)) {
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CInstr instr(parcel);
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#if XLEN == 32
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if (instr.opcode() == C_LW) {
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intptr_t offset = instr.mem4_imm();
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#elif XLEN == 64
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if (instr.opcode() == C_LD) {
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intptr_t offset = instr.mem8_imm();
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#endif
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if (instr.rs1p() == PP) {
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// PP is untagged on RISC-V.
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if (!Utils::IsAligned(offset, kWordSize)) {
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return false; // Being used as argument register A5.
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}
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intptr_t index = ObjectPool::IndexFromOffset(offset - kHeapObjectTag);
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return ObjectAtPoolIndex(code, index, obj);
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} else if (instr.rs1p() == THR) {
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return Thread::ObjectAtOffset(offset, obj);
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}
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}
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} else {
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Instr instr(*reinterpret_cast<uint32_t*>(pc));
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#if XLEN == 32
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if (instr.opcode() == LOAD && instr.funct3() == LW) {
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#elif XLEN == 64
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if (instr.opcode() == LOAD && instr.funct3() == LD) {
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#endif
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intptr_t offset = instr.itype_imm();
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if (instr.rs1() == PP) {
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// PP is untagged on RISC-V.
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if (!Utils::IsAligned(offset, kWordSize)) {
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return false; // Being used as argument register A5.
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}
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intptr_t index = ObjectPool::IndexFromOffset(offset - kHeapObjectTag);
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return ObjectAtPoolIndex(code, index, obj);
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} else if (instr.rs1() == THR) {
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return Thread::ObjectAtOffset(offset, obj);
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}
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}
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if ((instr.opcode() == OPIMM) && (instr.funct3() == ADDI) &&
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(instr.rs1() == NULL_REG)) {
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if (instr.itype_imm() == 0) {
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*obj = Object::null();
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return true;
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}
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if (instr.itype_imm() == kTrueOffsetFromNull) {
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*obj = Object::bool_true().ptr();
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return true;
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}
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if (instr.itype_imm() == kFalseOffsetFromNull) {
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*obj = Object::bool_false().ptr();
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return true;
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}
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}
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}
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// TODO(riscv): Loads with offsets beyond 12 bits.
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return false;
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}
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// Encodes a load sequence ending at 'end'. Encodes a fixed length two
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// instruction load from the pool pointer in PP using the destination
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// register reg as a temporary for the base address.
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// Assumes that the location has already been validated for patching.
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void InstructionPattern::EncodeLoadWordFromPoolFixed(uword end,
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int32_t offset) {
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UNIMPLEMENTED();
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}
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CodePtr CallPattern::TargetCode() const {
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return static_cast<CodePtr>(object_pool_.ObjectAt(target_code_pool_index_));
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}
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void CallPattern::SetTargetCode(const Code& target) const {
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object_pool_.SetObjectAt(target_code_pool_index_, target);
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// No need to flush the instruction cache, since the code is not modified.
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}
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ObjectPtr ICCallPattern::Data() const {
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return object_pool_.ObjectAt(data_pool_index_);
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}
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void ICCallPattern::SetData(const Object& data) const {
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ASSERT(data.IsArray() || data.IsICData() || data.IsMegamorphicCache());
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object_pool_.SetObjectAt(data_pool_index_, data);
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}
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CodePtr ICCallPattern::TargetCode() const {
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return static_cast<CodePtr>(object_pool_.ObjectAt(target_pool_index_));
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}
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void ICCallPattern::SetTargetCode(const Code& target) const {
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object_pool_.SetObjectAt(target_pool_index_, target);
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// No need to flush the instruction cache, since the code is not modified.
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}
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SwitchableCallPatternBase::SwitchableCallPatternBase(
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const ObjectPool& object_pool)
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: object_pool_(object_pool), data_pool_index_(-1), target_pool_index_(-1) {}
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ObjectPtr SwitchableCallPatternBase::data() const {
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return object_pool_.ObjectAt(data_pool_index_);
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}
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void SwitchableCallPatternBase::SetData(const Object& data) const {
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ASSERT(!Object::Handle(object_pool_.ObjectAt(data_pool_index_)).IsCode());
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object_pool_.SetObjectAt(data_pool_index_, data);
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}
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SwitchableCallPattern::SwitchableCallPattern(uword pc, const Code& code)
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: SwitchableCallPatternBase(ObjectPool::Handle(code.GetObjectPool())) {
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ASSERT(code.ContainsInstructionAt(pc));
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UNIMPLEMENTED();
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}
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uword SwitchableCallPattern::target_entry() const {
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return Code::Handle(Code::RawCast(object_pool_.ObjectAt(target_pool_index_)))
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.MonomorphicEntryPoint();
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}
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void SwitchableCallPattern::SetTarget(const Code& target) const {
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ASSERT(Object::Handle(object_pool_.ObjectAt(target_pool_index_)).IsCode());
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object_pool_.SetObjectAt(target_pool_index_, target);
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}
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BareSwitchableCallPattern::BareSwitchableCallPattern(uword pc)
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: SwitchableCallPatternBase(ObjectPool::Handle(
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IsolateGroup::Current()->object_store()->global_object_pool())) {
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// [lui,add,]lx RA, ##(pp)
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// [lui,add,]lx IC_DATA_REG, ##(pp)
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// xxxx jalr RA
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// Last instruction: jalr ra.
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ASSERT(*reinterpret_cast<uint16_t*>(pc - 2) == 0x9082);
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Register reg;
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uword target_load_end = InstructionPattern::DecodeLoadWordFromPool(
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pc - 2, ®, &data_pool_index_);
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ASSERT_EQUAL(reg, IC_DATA_REG);
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InstructionPattern::DecodeLoadWordFromPool(target_load_end, ®,
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&target_pool_index_);
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ASSERT_EQUAL(reg, RA);
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}
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uword BareSwitchableCallPattern::target_entry() const {
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return object_pool_.RawValueAt(target_pool_index_);
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}
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void BareSwitchableCallPattern::SetTarget(const Code& target) const {
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ASSERT(object_pool_.TypeAt(target_pool_index_) ==
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ObjectPool::EntryType::kImmediate);
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object_pool_.SetRawValueAt(target_pool_index_,
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target.MonomorphicEntryPoint());
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}
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ReturnPattern::ReturnPattern(uword pc) : pc_(pc) {}
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bool ReturnPattern::IsValid() const {
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return *reinterpret_cast<uint16_t*>(pc_) == 0x8082;
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}
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bool PcRelativeCallPattern::IsValid() const {
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Instr aupic(*reinterpret_cast<uint32_t*>(pc_));
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if (aupic.opcode() != AUIPC) return false;
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Instr jalr(*reinterpret_cast<uint32_t*>(pc_ + 4));
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if (jalr.opcode() != JALR) return false;
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if (aupic.rd() != jalr.rs1()) return false;
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if (jalr.rd() != RA) return false;
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return true;
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}
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bool PcRelativeTailCallPattern::IsValid() const {
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Instr aupic(*reinterpret_cast<uint32_t*>(pc_));
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if (aupic.opcode() != AUIPC) return false;
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Instr jr(*reinterpret_cast<uint32_t*>(pc_ + 4));
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if (jr.opcode() != JALR) return false;
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if (aupic.rd() != jr.rs1()) return false;
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if (jr.rd() != ZR) return false;
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return true;
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}
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void PcRelativeTrampolineJumpPattern::Initialize() {
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UNREACHABLE();
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}
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int32_t PcRelativeTrampolineJumpPattern::distance() {
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UNREACHABLE();
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return 0;
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}
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void PcRelativeTrampolineJumpPattern::set_distance(int32_t distance) {
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UNREACHABLE();
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}
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bool PcRelativeTrampolineJumpPattern::IsValid() const {
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UNREACHABLE();
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return false;
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}
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intptr_t TypeTestingStubCallPattern::GetSubtypeTestCachePoolIndex() {
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// Calls to the type testing stubs look like:
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// lx s4, ...
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// lx Rn, idx(pp)
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// jalr s4
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// where Rn = TypeTestABI::kSubtypeTestCacheReg.
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// Ensure the caller of the type testing stub (whose return address is [pc_])
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// branched via `blr R9` or a pc-relative call.
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if (*reinterpret_cast<uint16_t*>(pc_ - 2) == 0x9a02) { // jalr s4
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// indirect call
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// xxxx c.jalr s4
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Register reg;
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intptr_t pool_index = -1;
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InstructionPattern::DecodeLoadWordFromPool(pc_ - 2, ®, &pool_index);
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ASSERT_EQUAL(reg, TypeTestABI::kSubtypeTestCacheReg);
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return pool_index;
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} else {
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ASSERT(FLAG_precompiled_mode);
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// pc-relative call
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// xxxxxxxx aupic ra, hi
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// xxxxxxxx jalr ra, lo
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Instr jalr(*reinterpret_cast<uint32_t*>(pc_ - 4));
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ASSERT(jalr.opcode() == JALR);
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Instr auipc(*reinterpret_cast<uint32_t*>(pc_ - 8));
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ASSERT(auipc.opcode() == AUIPC);
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Register reg;
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intptr_t pool_index = -1;
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InstructionPattern::DecodeLoadWordFromPool(pc_ - 8, ®, &pool_index);
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ASSERT_EQUAL(reg, TypeTestABI::kSubtypeTestCacheReg);
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return pool_index;
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}
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}
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} // namespace dart
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#endif // defined TARGET_ARCH_RISCV
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