mirror of
https://github.com/dart-lang/sdk
synced 2024-09-23 01:13:46 +00:00
4aa1febbe6
On platforms that already use an object pool, we had a separate object table used only for deoptimization infos. With this CL we don't have separate tables, but only use the common object pool for both purposes. R=vegorov@google.com Review URL: https://codereview.chromium.org//1073173003 git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@45108 260f80e4-7a28-3924-810f-c04153c831b5
1133 lines
41 KiB
C++
1133 lines
41 KiB
C++
// Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
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// for details. All rights reserved. Use of this source code is governed by a
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// BSD-style license that can be found in the LICENSE file.
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#ifndef VM_ASSEMBLER_ARM_H_
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#define VM_ASSEMBLER_ARM_H_
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#ifndef VM_ASSEMBLER_H_
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#error Do not include assembler_arm.h directly; use assembler.h instead.
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#endif
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#include "platform/assert.h"
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#include "platform/utils.h"
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#include "vm/constants_arm.h"
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#include "vm/cpu.h"
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#include "vm/hash_map.h"
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#include "vm/object.h"
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#include "vm/simulator.h"
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namespace dart {
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// Forward declarations.
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class RuntimeEntry;
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class Label : public ValueObject {
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public:
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Label() : position_(0) { }
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~Label() {
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// Assert if label is being destroyed with unresolved branches pending.
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ASSERT(!IsLinked());
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}
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// Returns the position for bound and linked labels. Cannot be used
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// for unused labels.
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intptr_t Position() const {
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ASSERT(!IsUnused());
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return IsBound() ? -position_ - kWordSize : position_ - kWordSize;
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}
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bool IsBound() const { return position_ < 0; }
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bool IsUnused() const { return position_ == 0; }
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bool IsLinked() const { return position_ > 0; }
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private:
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intptr_t position_;
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void Reinitialize() {
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position_ = 0;
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}
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void BindTo(intptr_t position) {
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ASSERT(!IsBound());
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position_ = -position - kWordSize;
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ASSERT(IsBound());
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}
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void LinkTo(intptr_t position) {
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ASSERT(!IsBound());
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position_ = position + kWordSize;
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ASSERT(IsLinked());
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}
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friend class Assembler;
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DISALLOW_COPY_AND_ASSIGN(Label);
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};
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// Encodes Addressing Mode 1 - Data-processing operands.
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class Operand : public ValueObject {
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public:
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// Data-processing operands - Uninitialized.
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Operand() : type_(-1), encoding_(-1) { }
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// Data-processing operands - Copy constructor.
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Operand(const Operand& other)
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: ValueObject(), type_(other.type_), encoding_(other.encoding_) { }
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// Data-processing operands - Assignment operator.
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Operand& operator=(const Operand& other) {
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type_ = other.type_;
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encoding_ = other.encoding_;
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return *this;
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}
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// Data-processing operands - Immediate.
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explicit Operand(uint32_t immediate) {
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ASSERT(immediate < (1 << kImmed8Bits));
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type_ = 1;
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encoding_ = immediate;
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}
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// Data-processing operands - Rotated immediate.
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Operand(uint32_t rotate, uint32_t immed8) {
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ASSERT((rotate < (1 << kRotateBits)) && (immed8 < (1 << kImmed8Bits)));
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type_ = 1;
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encoding_ = (rotate << kRotateShift) | (immed8 << kImmed8Shift);
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}
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// Data-processing operands - Register.
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explicit Operand(Register rm) {
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type_ = 0;
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encoding_ = static_cast<uint32_t>(rm);
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}
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// Data-processing operands - Logical shift/rotate by immediate.
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Operand(Register rm, Shift shift, uint32_t shift_imm) {
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ASSERT(shift_imm < (1 << kShiftImmBits));
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type_ = 0;
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encoding_ = shift_imm << kShiftImmShift |
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static_cast<uint32_t>(shift) << kShiftShift |
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static_cast<uint32_t>(rm);
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}
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// Data-processing operands - Logical shift/rotate by register.
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Operand(Register rm, Shift shift, Register rs) {
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type_ = 0;
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encoding_ = static_cast<uint32_t>(rs) << kShiftRegisterShift |
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static_cast<uint32_t>(shift) << kShiftShift | (1 << 4) |
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static_cast<uint32_t>(rm);
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}
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static bool CanHold(uint32_t immediate, Operand* o) {
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// Avoid the more expensive test for frequent small immediate values.
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if (immediate < (1 << kImmed8Bits)) {
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o->type_ = 1;
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o->encoding_ = (0 << kRotateShift) | (immediate << kImmed8Shift);
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return true;
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}
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// Note that immediate must be unsigned for the test to work correctly.
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for (int rot = 0; rot < 16; rot++) {
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uint32_t imm8 = (immediate << 2*rot) | (immediate >> (32 - 2*rot));
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if (imm8 < (1 << kImmed8Bits)) {
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o->type_ = 1;
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o->encoding_ = (rot << kRotateShift) | (imm8 << kImmed8Shift);
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return true;
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}
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}
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return false;
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}
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private:
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bool is_valid() const { return (type_ == 0) || (type_ == 1); }
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uint32_t type() const {
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ASSERT(is_valid());
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return type_;
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}
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uint32_t encoding() const {
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ASSERT(is_valid());
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return encoding_;
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}
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uint32_t type_; // Encodes the type field (bits 27-25) in the instruction.
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uint32_t encoding_;
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friend class Assembler;
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friend class Address;
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};
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enum OperandSize {
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kByte,
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kUnsignedByte,
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kHalfword,
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kUnsignedHalfword,
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kWord,
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kUnsignedWord,
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kWordPair,
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kSWord,
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kDWord,
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kRegList,
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};
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// Load/store multiple addressing mode.
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enum BlockAddressMode {
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// bit encoding P U W
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DA = (0|0|0) << 21, // decrement after
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IA = (0|4|0) << 21, // increment after
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DB = (8|0|0) << 21, // decrement before
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IB = (8|4|0) << 21, // increment before
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DA_W = (0|0|1) << 21, // decrement after with writeback to base
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IA_W = (0|4|1) << 21, // increment after with writeback to base
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DB_W = (8|0|1) << 21, // decrement before with writeback to base
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IB_W = (8|4|1) << 21 // increment before with writeback to base
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};
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class Address : public ValueObject {
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public:
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enum OffsetKind {
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Immediate,
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IndexRegister,
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ScaledIndexRegister,
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};
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// Memory operand addressing mode
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enum Mode {
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kModeMask = (8|4|1) << 21,
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// bit encoding P U W
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Offset = (8|4|0) << 21, // offset (w/o writeback to base)
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PreIndex = (8|4|1) << 21, // pre-indexed addressing with writeback
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PostIndex = (0|4|0) << 21, // post-indexed addressing with writeback
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NegOffset = (8|0|0) << 21, // negative offset (w/o writeback to base)
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NegPreIndex = (8|0|1) << 21, // negative pre-indexed with writeback
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NegPostIndex = (0|0|0) << 21 // negative post-indexed with writeback
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};
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Address(const Address& other)
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: ValueObject(), encoding_(other.encoding_), kind_(other.kind_) {
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}
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Address& operator=(const Address& other) {
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encoding_ = other.encoding_;
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kind_ = other.kind_;
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return *this;
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}
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bool Equals(const Address& other) const {
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return (encoding_ == other.encoding_) && (kind_ == other.kind_);
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}
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explicit Address(Register rn, int32_t offset = 0, Mode am = Offset) {
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ASSERT(Utils::IsAbsoluteUint(12, offset));
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kind_ = Immediate;
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if (offset < 0) {
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encoding_ = (am ^ (1 << kUShift)) | -offset; // Flip U to adjust sign.
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} else {
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encoding_ = am | offset;
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}
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encoding_ |= static_cast<uint32_t>(rn) << kRnShift;
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}
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// There is no register offset mode unless Mode is Offset, in which case the
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// shifted register case below should be used.
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Address(Register rn, Register r, Mode am);
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Address(Register rn, Register rm,
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Shift shift = LSL, uint32_t shift_imm = 0, Mode am = Offset) {
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Operand o(rm, shift, shift_imm);
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if ((shift == LSL) && (shift_imm == 0)) {
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kind_ = IndexRegister;
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} else {
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kind_ = ScaledIndexRegister;
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}
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encoding_ = o.encoding() | am | (static_cast<uint32_t>(rn) << kRnShift);
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}
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// There is no shifted register mode with a register shift.
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Address(Register rn, Register rm, Shift shift, Register r, Mode am = Offset);
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static OperandSize OperandSizeFor(intptr_t cid);
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static bool CanHoldLoadOffset(OperandSize size,
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int32_t offset,
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int32_t* offset_mask);
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static bool CanHoldStoreOffset(OperandSize size,
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int32_t offset,
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int32_t* offset_mask);
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static bool CanHoldImmediateOffset(bool is_load,
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intptr_t cid,
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int64_t offset);
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private:
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Register rn() const {
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return Instr::At(reinterpret_cast<uword>(&encoding_))->RnField();
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}
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Register rm() const {
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return ((kind() == IndexRegister) || (kind() == ScaledIndexRegister)) ?
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Instr::At(reinterpret_cast<uword>(&encoding_))->RmField() :
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kNoRegister;
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}
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Mode mode() const { return static_cast<Mode>(encoding() & kModeMask); }
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uint32_t encoding() const { return encoding_; }
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// Encoding for addressing mode 3.
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uint32_t encoding3() const;
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// Encoding for vfp load/store addressing.
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uint32_t vencoding() const;
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OffsetKind kind() const { return kind_; }
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uint32_t encoding_;
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OffsetKind kind_;
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friend class Assembler;
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};
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class FieldAddress : public Address {
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public:
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FieldAddress(Register base, int32_t disp)
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: Address(base, disp - kHeapObjectTag) { }
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// This addressing mode does not exist.
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FieldAddress(Register base, Register r);
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FieldAddress(const FieldAddress& other) : Address(other) { }
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FieldAddress& operator=(const FieldAddress& other) {
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Address::operator=(other);
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return *this;
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}
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};
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class Assembler : public ValueObject {
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public:
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explicit Assembler(bool use_far_branches = false)
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: buffer_(),
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prologue_offset_(-1),
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use_far_branches_(use_far_branches),
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comments_(),
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allow_constant_pool_(true) { }
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~Assembler() { }
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void PopRegister(Register r) { Pop(r); }
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void Bind(Label* label);
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void Jump(Label* label) { b(label); }
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// Misc. functionality
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intptr_t CodeSize() const { return buffer_.Size(); }
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intptr_t prologue_offset() const { return prologue_offset_; }
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// Count the fixups that produce a pointer offset, without processing
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// the fixups. On ARM there are no pointers in code.
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intptr_t CountPointerOffsets() const { return 0; }
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const ZoneGrowableArray<intptr_t>& GetPointerOffsets() const {
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ASSERT(buffer_.pointer_offsets().length() == 0); // No pointers in code.
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return buffer_.pointer_offsets();
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}
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const GrowableObjectArray& object_pool_data() const {
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return object_pool_.data();
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}
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ObjectPool& object_pool() { return object_pool_; }
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bool use_far_branches() const {
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return FLAG_use_far_branches || use_far_branches_;
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}
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#if defined(TESTING) || defined(DEBUG)
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// Used in unit tests and to ensure predictable verification code size in
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// FlowGraphCompiler::EmitEdgeCounter.
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void set_use_far_branches(bool b) {
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use_far_branches_ = b;
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}
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#endif // TESTING || DEBUG
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void FinalizeInstructions(const MemoryRegion& region) {
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buffer_.FinalizeInstructions(region);
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}
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// Debugging and bringup support.
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void Stop(const char* message);
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void Unimplemented(const char* message);
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void Untested(const char* message);
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void Unreachable(const char* message);
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static void InitializeMemoryWithBreakpoints(uword data, intptr_t length);
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void Comment(const char* format, ...) PRINTF_ATTRIBUTE(2, 3);
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static bool EmittingComments();
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const Code::Comments& GetCodeComments() const;
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static const char* RegisterName(Register reg);
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static const char* FpuRegisterName(FpuRegister reg);
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// Data-processing instructions.
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void and_(Register rd, Register rn, Operand o, Condition cond = AL);
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void eor(Register rd, Register rn, Operand o, Condition cond = AL);
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void sub(Register rd, Register rn, Operand o, Condition cond = AL);
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void subs(Register rd, Register rn, Operand o, Condition cond = AL);
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void rsb(Register rd, Register rn, Operand o, Condition cond = AL);
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void rsbs(Register rd, Register rn, Operand o, Condition cond = AL);
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void add(Register rd, Register rn, Operand o, Condition cond = AL);
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void adds(Register rd, Register rn, Operand o, Condition cond = AL);
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void adc(Register rd, Register rn, Operand o, Condition cond = AL);
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void adcs(Register rd, Register rn, Operand o, Condition cond = AL);
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void sbc(Register rd, Register rn, Operand o, Condition cond = AL);
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void sbcs(Register rd, Register rn, Operand o, Condition cond = AL);
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void rsc(Register rd, Register rn, Operand o, Condition cond = AL);
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void tst(Register rn, Operand o, Condition cond = AL);
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void teq(Register rn, Operand o, Condition cond = AL);
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void cmp(Register rn, Operand o, Condition cond = AL);
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void cmn(Register rn, Operand o, Condition cond = AL);
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void orr(Register rd, Register rn, Operand o, Condition cond = AL);
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void orrs(Register rd, Register rn, Operand o, Condition cond = AL);
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void mov(Register rd, Operand o, Condition cond = AL);
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void movs(Register rd, Operand o, Condition cond = AL);
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void bic(Register rd, Register rn, Operand o, Condition cond = AL);
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void bics(Register rd, Register rn, Operand o, Condition cond = AL);
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void mvn(Register rd, Operand o, Condition cond = AL);
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void mvns(Register rd, Operand o, Condition cond = AL);
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// Miscellaneous data-processing instructions.
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void clz(Register rd, Register rm, Condition cond = AL);
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// Multiply instructions.
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void mul(Register rd, Register rn, Register rm, Condition cond = AL);
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void muls(Register rd, Register rn, Register rm, Condition cond = AL);
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void mla(Register rd, Register rn, Register rm, Register ra,
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Condition cond = AL);
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void mls(Register rd, Register rn, Register rm, Register ra,
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Condition cond = AL);
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void smull(Register rd_lo, Register rd_hi, Register rn, Register rm,
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Condition cond = AL);
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void umull(Register rd_lo, Register rd_hi, Register rn, Register rm,
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Condition cond = AL);
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void smlal(Register rd_lo, Register rd_hi, Register rn, Register rm,
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Condition cond = AL);
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void umlal(Register rd_lo, Register rd_hi, Register rn, Register rm,
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Condition cond = AL);
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// Emulation of this instruction uses IP and the condition codes. Therefore,
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// none of the registers can be IP, and the instruction can only be used
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// unconditionally.
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void umaal(Register rd_lo, Register rd_hi, Register rn, Register rm);
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// Division instructions.
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void sdiv(Register rd, Register rn, Register rm, Condition cond = AL);
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void udiv(Register rd, Register rn, Register rm, Condition cond = AL);
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// Load/store instructions.
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void ldr(Register rd, Address ad, Condition cond = AL);
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void str(Register rd, Address ad, Condition cond = AL);
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void ldrb(Register rd, Address ad, Condition cond = AL);
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void strb(Register rd, Address ad, Condition cond = AL);
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void ldrh(Register rd, Address ad, Condition cond = AL);
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void strh(Register rd, Address ad, Condition cond = AL);
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void ldrsb(Register rd, Address ad, Condition cond = AL);
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void ldrsh(Register rd, Address ad, Condition cond = AL);
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// ldrd and strd actually support the full range of addressing modes, but
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// we don't use them, and we need to split them up into two instructions for
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// ARMv5TE, so we only support the base + offset mode.
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void ldrd(Register rd, Register rn, int32_t offset, Condition cond = AL);
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void strd(Register rd, Register rn, int32_t offset, Condition cond = AL);
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void ldm(BlockAddressMode am, Register base,
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RegList regs, Condition cond = AL);
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void stm(BlockAddressMode am, Register base,
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RegList regs, Condition cond = AL);
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void ldrex(Register rd, Register rn, Condition cond = AL);
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void strex(Register rd, Register rt, Register rn, Condition cond = AL);
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// Miscellaneous instructions.
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void clrex();
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void nop(Condition cond = AL);
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// Note that gdb sets breakpoints using the undefined instruction 0xe7f001f0.
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void bkpt(uint16_t imm16);
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void svc(uint32_t imm24, Condition cond = AL);
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// Floating point instructions (VFPv3-D16 and VFPv3-D32 profiles).
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void vmovsr(SRegister sn, Register rt, Condition cond = AL);
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void vmovrs(Register rt, SRegister sn, Condition cond = AL);
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void vmovsrr(SRegister sm, Register rt, Register rt2, Condition cond = AL);
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void vmovrrs(Register rt, Register rt2, SRegister sm, Condition cond = AL);
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void vmovdrr(DRegister dm, Register rt, Register rt2, Condition cond = AL);
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void vmovrrd(Register rt, Register rt2, DRegister dm, Condition cond = AL);
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void vmovdr(DRegister dd, int i, Register rt, Condition cond = AL);
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void vmovs(SRegister sd, SRegister sm, Condition cond = AL);
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void vmovd(DRegister dd, DRegister dm, Condition cond = AL);
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|
void vmovq(QRegister qd, QRegister qm);
|
|
|
|
// Returns false if the immediate cannot be encoded.
|
|
bool vmovs(SRegister sd, float s_imm, Condition cond = AL);
|
|
bool vmovd(DRegister dd, double d_imm, Condition cond = AL);
|
|
|
|
void vldrs(SRegister sd, Address ad, Condition cond = AL);
|
|
void vstrs(SRegister sd, Address ad, Condition cond = AL);
|
|
void vldrd(DRegister dd, Address ad, Condition cond = AL);
|
|
void vstrd(DRegister dd, Address ad, Condition cond = AL);
|
|
|
|
void vldms(BlockAddressMode am, Register base,
|
|
SRegister first, SRegister last, Condition cond = AL);
|
|
void vstms(BlockAddressMode am, Register base,
|
|
SRegister first, SRegister last, Condition cond = AL);
|
|
|
|
void vldmd(BlockAddressMode am, Register base,
|
|
DRegister first, intptr_t count, Condition cond = AL);
|
|
void vstmd(BlockAddressMode am, Register base,
|
|
DRegister first, intptr_t count, Condition cond = AL);
|
|
|
|
void vadds(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL);
|
|
void vaddd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL);
|
|
void vaddqi(OperandSize sz, QRegister qd, QRegister qn, QRegister qm);
|
|
void vaddqs(QRegister qd, QRegister qn, QRegister qm);
|
|
void vsubs(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL);
|
|
void vsubd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL);
|
|
void vsubqi(OperandSize sz, QRegister qd, QRegister qn, QRegister qm);
|
|
void vsubqs(QRegister qd, QRegister qn, QRegister qm);
|
|
void vmuls(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL);
|
|
void vmuld(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL);
|
|
void vmulqi(OperandSize sz, QRegister qd, QRegister qn, QRegister qm);
|
|
void vmulqs(QRegister qd, QRegister qn, QRegister qm);
|
|
void vshlqi(OperandSize sz, QRegister qd, QRegister qm, QRegister qn);
|
|
void vshlqu(OperandSize sz, QRegister qd, QRegister qm, QRegister qn);
|
|
void vmlas(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL);
|
|
void vmlad(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL);
|
|
void vmlss(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL);
|
|
void vmlsd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL);
|
|
void vdivs(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL);
|
|
void vdivd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL);
|
|
void vminqs(QRegister qd, QRegister qn, QRegister qm);
|
|
void vmaxqs(QRegister qd, QRegister qn, QRegister qm);
|
|
void vrecpeqs(QRegister qd, QRegister qm);
|
|
void vrecpsqs(QRegister qd, QRegister qn, QRegister qm);
|
|
void vrsqrteqs(QRegister qd, QRegister qm);
|
|
void vrsqrtsqs(QRegister qd, QRegister qn, QRegister qm);
|
|
|
|
void veorq(QRegister qd, QRegister qn, QRegister qm);
|
|
void vorrq(QRegister qd, QRegister qn, QRegister qm);
|
|
void vornq(QRegister qd, QRegister qn, QRegister qm);
|
|
void vandq(QRegister qd, QRegister qn, QRegister qm);
|
|
void vmvnq(QRegister qd, QRegister qm);
|
|
|
|
void vceqqi(OperandSize sz, QRegister qd, QRegister qn, QRegister qm);
|
|
void vceqqs(QRegister qd, QRegister qn, QRegister qm);
|
|
void vcgeqi(OperandSize sz, QRegister qd, QRegister qn, QRegister qm);
|
|
void vcugeqi(OperandSize sz, QRegister qd, QRegister qn, QRegister qm);
|
|
void vcgeqs(QRegister qd, QRegister qn, QRegister qm);
|
|
void vcgtqi(OperandSize sz, QRegister qd, QRegister qn, QRegister qm);
|
|
void vcugtqi(OperandSize sz, QRegister qd, QRegister qn, QRegister qm);
|
|
void vcgtqs(QRegister qd, QRegister qn, QRegister qm);
|
|
|
|
void vabss(SRegister sd, SRegister sm, Condition cond = AL);
|
|
void vabsd(DRegister dd, DRegister dm, Condition cond = AL);
|
|
void vabsqs(QRegister qd, QRegister qm);
|
|
void vnegs(SRegister sd, SRegister sm, Condition cond = AL);
|
|
void vnegd(DRegister dd, DRegister dm, Condition cond = AL);
|
|
void vnegqs(QRegister qd, QRegister qm);
|
|
void vsqrts(SRegister sd, SRegister sm, Condition cond = AL);
|
|
void vsqrtd(DRegister dd, DRegister dm, Condition cond = AL);
|
|
|
|
void vcvtsd(SRegister sd, DRegister dm, Condition cond = AL);
|
|
void vcvtds(DRegister dd, SRegister sm, Condition cond = AL);
|
|
void vcvtis(SRegister sd, SRegister sm, Condition cond = AL);
|
|
void vcvtid(SRegister sd, DRegister dm, Condition cond = AL);
|
|
void vcvtsi(SRegister sd, SRegister sm, Condition cond = AL);
|
|
void vcvtdi(DRegister dd, SRegister sm, Condition cond = AL);
|
|
void vcvtus(SRegister sd, SRegister sm, Condition cond = AL);
|
|
void vcvtud(SRegister sd, DRegister dm, Condition cond = AL);
|
|
void vcvtsu(SRegister sd, SRegister sm, Condition cond = AL);
|
|
void vcvtdu(DRegister dd, SRegister sm, Condition cond = AL);
|
|
|
|
void vcmps(SRegister sd, SRegister sm, Condition cond = AL);
|
|
void vcmpd(DRegister dd, DRegister dm, Condition cond = AL);
|
|
void vcmpsz(SRegister sd, Condition cond = AL);
|
|
void vcmpdz(DRegister dd, Condition cond = AL);
|
|
void vmrs(Register rd, Condition cond = AL);
|
|
void vmstat(Condition cond = AL);
|
|
|
|
// Duplicates the operand of size sz at index idx from dm to all elements of
|
|
// qd. This is a special case of vtbl.
|
|
void vdup(OperandSize sz, QRegister qd, DRegister dm, int idx);
|
|
|
|
// Each byte of dm is an index into the table of bytes formed by concatenating
|
|
// a list of 'length' registers starting with dn. The result is placed in dd.
|
|
void vtbl(DRegister dd, DRegister dn, int length, DRegister dm);
|
|
|
|
// The words of qd and qm are interleaved with the low words of the result
|
|
// in qd and the high words in qm.
|
|
void vzipqw(QRegister qd, QRegister qm);
|
|
|
|
// Branch instructions.
|
|
void b(Label* label, Condition cond = AL);
|
|
void bl(Label* label, Condition cond = AL);
|
|
void bx(Register rm, Condition cond = AL);
|
|
void blx(Register rm, Condition cond = AL);
|
|
|
|
// Macros.
|
|
// Branch to an entry address. Call sequence is never patched.
|
|
void Branch(const ExternalLabel* label, Condition cond = AL);
|
|
|
|
// Branch to an entry address. Call sequence can be patched or even replaced.
|
|
void BranchPatchable(const ExternalLabel* label);
|
|
|
|
// Branch and link to an entry address. Call sequence is never patched.
|
|
void BranchLink(const ExternalLabel* label);
|
|
|
|
// Branch and link to an entry address. Call sequence can be patched.
|
|
void BranchLinkPatchable(const ExternalLabel* label);
|
|
|
|
// Branch and link to [base + offset]. Call sequence is never patched.
|
|
void BranchLinkOffset(Register base, int32_t offset);
|
|
|
|
// Add signed immediate value to rd. May clobber IP.
|
|
void AddImmediate(Register rd, int32_t value, Condition cond = AL);
|
|
void AddImmediate(Register rd, Register rn, int32_t value,
|
|
Condition cond = AL);
|
|
void AddImmediateSetFlags(Register rd, Register rn, int32_t value,
|
|
Condition cond = AL);
|
|
void SubImmediateSetFlags(Register rd, Register rn, int32_t value,
|
|
Condition cond = AL);
|
|
void AndImmediate(Register rd, Register rs, int32_t imm, Condition cond = AL);
|
|
|
|
// Test rn and immediate. May clobber IP.
|
|
void TestImmediate(Register rn, int32_t imm, Condition cond = AL);
|
|
|
|
// Compare rn with signed immediate value. May clobber IP.
|
|
void CompareImmediate(Register rn, int32_t value, Condition cond = AL);
|
|
|
|
|
|
// Signed integer division of left by right. Checks to see if integer
|
|
// division is supported. If not, uses the FPU for division with
|
|
// temporary registers tmpl and tmpr. tmpl and tmpr must be different
|
|
// registers.
|
|
void IntegerDivide(Register result, Register left, Register right,
|
|
DRegister tmpl, DRegister tmpr);
|
|
|
|
// Load and Store.
|
|
// These three do not clobber IP.
|
|
void LoadPatchableImmediate(Register rd, int32_t value, Condition cond = AL);
|
|
void LoadDecodableImmediate(Register rd, int32_t value, Condition cond = AL);
|
|
void LoadImmediate(Register rd, int32_t value, Condition cond = AL);
|
|
// These two may clobber IP.
|
|
void LoadSImmediate(SRegister sd, float value, Condition cond = AL);
|
|
void LoadDImmediate(DRegister dd, double value,
|
|
Register scratch, Condition cond = AL);
|
|
|
|
void MarkExceptionHandler(Label* label);
|
|
|
|
void Drop(intptr_t stack_elements);
|
|
|
|
void LoadPoolPointer();
|
|
|
|
void LoadIsolate(Register rd);
|
|
|
|
void LoadObject(Register rd, const Object& object, Condition cond = AL);
|
|
void PushObject(const Object& object);
|
|
void CompareObject(Register rn, const Object& object);
|
|
|
|
// When storing into a heap object field, knowledge of the previous content
|
|
// is expressed through these constants.
|
|
enum FieldContent {
|
|
kEmptyOrSmiOrNull, // Empty = garbage/zapped in release/debug mode.
|
|
kHeapObjectOrSmi,
|
|
kOnlySmi,
|
|
};
|
|
|
|
void StoreIntoObject(Register object, // Object we are storing into.
|
|
const Address& dest, // Where we are storing into.
|
|
Register value, // Value we are storing.
|
|
bool can_value_be_smi = true);
|
|
void StoreIntoObjectOffset(Register object,
|
|
int32_t offset,
|
|
Register value,
|
|
bool can_value_be_smi = true);
|
|
|
|
void StoreIntoObjectNoBarrier(Register object,
|
|
const Address& dest,
|
|
Register value,
|
|
FieldContent old_content = kHeapObjectOrSmi);
|
|
void InitializeFieldNoBarrier(Register object,
|
|
const Address& dest,
|
|
Register value) {
|
|
StoreIntoObjectNoBarrier(object, dest, value, kEmptyOrSmiOrNull);
|
|
}
|
|
void StoreIntoObjectNoBarrierOffset(
|
|
Register object,
|
|
int32_t offset,
|
|
Register value,
|
|
FieldContent old_content = kHeapObjectOrSmi);
|
|
void StoreIntoObjectNoBarrier(Register object,
|
|
const Address& dest,
|
|
const Object& value,
|
|
FieldContent old_content = kHeapObjectOrSmi);
|
|
void StoreIntoObjectNoBarrierOffset(
|
|
Register object,
|
|
int32_t offset,
|
|
const Object& value,
|
|
FieldContent old_content = kHeapObjectOrSmi);
|
|
|
|
// Store value_even, value_odd, value_even, ... into the words in the address
|
|
// range [begin, end), assumed to be uninitialized fields in object (tagged).
|
|
// The stores must not need a generational store barrier (e.g., smi/null),
|
|
// and (value_even, value_odd) must be a valid register pair.
|
|
// Destroys register 'begin'.
|
|
void InitializeFieldsNoBarrier(Register object,
|
|
Register begin,
|
|
Register end,
|
|
Register value_even,
|
|
Register value_odd);
|
|
// Like above, for the range [base+begin_offset, base+end_offset), unrolled.
|
|
void InitializeFieldsNoBarrierUnrolled(Register object,
|
|
Register base,
|
|
intptr_t begin_offset,
|
|
intptr_t end_offset,
|
|
Register value_even,
|
|
Register value_odd);
|
|
|
|
// Stores a Smi value into a heap object field that always contains a Smi.
|
|
void StoreIntoSmiField(const Address& dest, Register value);
|
|
|
|
void LoadClassId(Register result, Register object, Condition cond = AL);
|
|
void LoadClassById(Register result, Register class_id);
|
|
void LoadClass(Register result, Register object, Register scratch);
|
|
void CompareClassId(Register object, intptr_t class_id, Register scratch);
|
|
void LoadTaggedClassIdMayBeSmi(Register result, Register object);
|
|
|
|
void ComputeRange(Register result,
|
|
Register value,
|
|
Register scratch,
|
|
Label* miss);
|
|
|
|
void UpdateRangeFeedback(Register value,
|
|
intptr_t idx,
|
|
Register ic_data,
|
|
Register scratch1,
|
|
Register scratch2,
|
|
Label* miss);
|
|
|
|
void LoadWordFromPoolOffset(Register rd, int32_t offset, Condition cond = AL);
|
|
void LoadFromOffset(OperandSize type,
|
|
Register reg,
|
|
Register base,
|
|
int32_t offset,
|
|
Condition cond = AL);
|
|
void LoadFieldFromOffset(OperandSize type,
|
|
Register reg,
|
|
Register base,
|
|
int32_t offset,
|
|
Condition cond = AL) {
|
|
LoadFromOffset(type, reg, base, offset - kHeapObjectTag, cond);
|
|
}
|
|
void StoreToOffset(OperandSize type,
|
|
Register reg,
|
|
Register base,
|
|
int32_t offset,
|
|
Condition cond = AL);
|
|
void LoadSFromOffset(SRegister reg,
|
|
Register base,
|
|
int32_t offset,
|
|
Condition cond = AL);
|
|
void StoreSToOffset(SRegister reg,
|
|
Register base,
|
|
int32_t offset,
|
|
Condition cond = AL);
|
|
void LoadDFromOffset(DRegister reg,
|
|
Register base,
|
|
int32_t offset,
|
|
Condition cond = AL);
|
|
void StoreDToOffset(DRegister reg,
|
|
Register base,
|
|
int32_t offset,
|
|
Condition cond = AL);
|
|
|
|
void LoadMultipleDFromOffset(DRegister first,
|
|
intptr_t count,
|
|
Register base,
|
|
int32_t offset);
|
|
void StoreMultipleDToOffset(DRegister first,
|
|
intptr_t count,
|
|
Register base,
|
|
int32_t offset);
|
|
|
|
void CopyDoubleField(Register dst, Register src,
|
|
Register tmp1, Register tmp2, DRegister dtmp);
|
|
void CopyFloat32x4Field(Register dst, Register src,
|
|
Register tmp1, Register tmp2, DRegister dtmp);
|
|
void CopyFloat64x2Field(Register dst, Register src,
|
|
Register tmp1, Register tmp2, DRegister dtmp);
|
|
|
|
void Push(Register rd, Condition cond = AL);
|
|
void Pop(Register rd, Condition cond = AL);
|
|
|
|
void PushList(RegList regs, Condition cond = AL);
|
|
void PopList(RegList regs, Condition cond = AL);
|
|
|
|
void MoveRegister(Register rd, Register rm, Condition cond = AL);
|
|
|
|
// Convenience shift instructions. Use mov instruction with shifter operand
|
|
// for variants setting the status flags.
|
|
void Lsl(Register rd, Register rm, const Operand& shift_imm,
|
|
Condition cond = AL);
|
|
void Lsl(Register rd, Register rm, Register rs, Condition cond = AL);
|
|
void Lsr(Register rd, Register rm, const Operand& shift_imm,
|
|
Condition cond = AL);
|
|
void Lsr(Register rd, Register rm, Register rs, Condition cond = AL);
|
|
void Asr(Register rd, Register rm, const Operand& shift_imm,
|
|
Condition cond = AL);
|
|
void Asr(Register rd, Register rm, Register rs, Condition cond = AL);
|
|
void Asrs(Register rd, Register rm, const Operand& shift_imm,
|
|
Condition cond = AL);
|
|
void Ror(Register rd, Register rm, const Operand& shift_imm,
|
|
Condition cond = AL);
|
|
void Ror(Register rd, Register rm, Register rs, Condition cond = AL);
|
|
void Rrx(Register rd, Register rm, Condition cond = AL);
|
|
|
|
// Fill rd with the sign of rm.
|
|
void SignFill(Register rd, Register rm, Condition cond = AL);
|
|
|
|
void Vreciprocalqs(QRegister qd, QRegister qm);
|
|
void VreciprocalSqrtqs(QRegister qd, QRegister qm);
|
|
// If qm must be preserved, then provide a (non-QTMP) temporary.
|
|
void Vsqrtqs(QRegister qd, QRegister qm, QRegister temp);
|
|
void Vdivqs(QRegister qd, QRegister qn, QRegister qm);
|
|
|
|
void SmiTag(Register reg, Condition cond = AL) {
|
|
Lsl(reg, reg, Operand(kSmiTagSize), cond);
|
|
}
|
|
|
|
void SmiTag(Register dst, Register src, Condition cond = AL) {
|
|
Lsl(dst, src, Operand(kSmiTagSize), cond);
|
|
}
|
|
|
|
void SmiUntag(Register reg, Condition cond = AL) {
|
|
Asr(reg, reg, Operand(kSmiTagSize), cond);
|
|
}
|
|
|
|
void SmiUntag(Register dst, Register src, Condition cond = AL) {
|
|
Asr(dst, src, Operand(kSmiTagSize), cond);
|
|
}
|
|
|
|
// Untag the value in the register assuming it is a smi.
|
|
// Untagging shifts tag bit into the carry flag - if carry is clear
|
|
// assumption was correct. In this case jump to the is_smi label.
|
|
// Otherwise fall-through.
|
|
void SmiUntag(Register dst, Register src, Label* is_smi) {
|
|
ASSERT(kSmiTagSize == 1);
|
|
Asrs(dst, src, Operand(kSmiTagSize));
|
|
b(is_smi, CC);
|
|
}
|
|
|
|
// Function frame setup and tear down.
|
|
void EnterFrame(RegList regs, intptr_t frame_space);
|
|
void LeaveFrame(RegList regs);
|
|
void Ret();
|
|
void ReserveAlignedFrameSpace(intptr_t frame_space);
|
|
|
|
// Create a frame for calling into runtime that preserves all volatile
|
|
// registers. Frame's SP is guaranteed to be correctly aligned and
|
|
// frame_space bytes are reserved under it.
|
|
void EnterCallRuntimeFrame(intptr_t frame_space);
|
|
void LeaveCallRuntimeFrame();
|
|
|
|
void CallRuntime(const RuntimeEntry& entry, intptr_t argument_count);
|
|
|
|
// Set up a Dart frame on entry with a frame pointer and PC information to
|
|
// enable easy access to the RawInstruction object of code corresponding
|
|
// to this frame.
|
|
void EnterDartFrame(intptr_t frame_size);
|
|
void LeaveDartFrame();
|
|
|
|
// Set up a Dart frame for a function compiled for on-stack replacement.
|
|
// The frame layout is a normal Dart frame, but the frame is partially set
|
|
// up on entry (it is the frame of the unoptimized code).
|
|
void EnterOsrFrame(intptr_t extra_size);
|
|
|
|
// Set up a stub frame so that the stack traversal code can easily identify
|
|
// a stub frame.
|
|
void EnterStubFrame(bool load_pp = false);
|
|
void LeaveStubFrame();
|
|
|
|
// Instruction pattern from entrypoint is used in Dart frame prologs
|
|
// to set up the frame and save a PC which can be used to figure out the
|
|
// RawInstruction object corresponding to the code running in the frame.
|
|
static intptr_t EntryPointToPcMarkerOffset() {
|
|
return TargetCPUFeatures::store_pc_read_offset();
|
|
}
|
|
|
|
// The register into which the allocation stats table is loaded with
|
|
// LoadAllocationStatsAddress should be passed to
|
|
// IncrementAllocationStats(WithSize) as stats_addr_reg to update the
|
|
// allocation stats. These are separate assembler macros so we can
|
|
// avoid a dependent load too nearby the load of the table address.
|
|
void LoadAllocationStatsAddress(Register dest,
|
|
intptr_t cid,
|
|
Heap::Space space);
|
|
void IncrementAllocationStats(Register stats_addr,
|
|
intptr_t cid,
|
|
Heap::Space space);
|
|
void IncrementAllocationStatsWithSize(Register stats_addr_reg,
|
|
Register size_reg,
|
|
intptr_t cid,
|
|
Heap::Space space);
|
|
|
|
Address ElementAddressForIntIndex(bool is_load,
|
|
bool is_external,
|
|
intptr_t cid,
|
|
intptr_t index_scale,
|
|
Register array,
|
|
intptr_t index,
|
|
Register temp);
|
|
|
|
Address ElementAddressForRegIndex(bool is_load,
|
|
bool is_external,
|
|
intptr_t cid,
|
|
intptr_t index_scale,
|
|
Register array,
|
|
Register index);
|
|
|
|
// Inlined allocation of an instance of class 'cls', code has no runtime
|
|
// calls. Jump to 'failure' if the instance cannot be allocated here.
|
|
// Allocated instance is returned in 'instance_reg'.
|
|
// Only the tags field of the object is initialized.
|
|
void TryAllocate(const Class& cls,
|
|
Label* failure,
|
|
Register instance_reg,
|
|
Register temp_reg);
|
|
|
|
void TryAllocateArray(intptr_t cid,
|
|
intptr_t instance_size,
|
|
Label* failure,
|
|
Register instance,
|
|
Register end_address,
|
|
Register temp1,
|
|
Register temp2);
|
|
|
|
// Emit data (e.g encoded instruction or immediate) in instruction stream.
|
|
void Emit(int32_t value);
|
|
|
|
// On some other platforms, we draw a distinction between safe and unsafe
|
|
// smis.
|
|
static bool IsSafe(const Object& object) { return true; }
|
|
static bool IsSafeSmi(const Object& object) { return object.IsSmi(); }
|
|
|
|
bool allow_constant_pool() const {
|
|
return allow_constant_pool_;
|
|
}
|
|
void set_allow_constant_pool(bool b) {
|
|
allow_constant_pool_ = b;
|
|
}
|
|
|
|
private:
|
|
AssemblerBuffer buffer_; // Contains position independent code.
|
|
ObjectPool object_pool_; // Objects and patchable jump targets.
|
|
|
|
int32_t prologue_offset_;
|
|
|
|
bool use_far_branches_;
|
|
|
|
// If you are thinking of using one or both of these instructions directly,
|
|
// instead LoadImmediate should probably be used.
|
|
void movw(Register rd, uint16_t imm16, Condition cond = AL);
|
|
void movt(Register rd, uint16_t imm16, Condition cond = AL);
|
|
|
|
void BindARMv6(Label* label);
|
|
void BindARMv7(Label* label);
|
|
|
|
class CodeComment : public ZoneAllocated {
|
|
public:
|
|
CodeComment(intptr_t pc_offset, const String& comment)
|
|
: pc_offset_(pc_offset), comment_(comment) { }
|
|
|
|
intptr_t pc_offset() const { return pc_offset_; }
|
|
const String& comment() const { return comment_; }
|
|
|
|
private:
|
|
intptr_t pc_offset_;
|
|
const String& comment_;
|
|
|
|
DISALLOW_COPY_AND_ASSIGN(CodeComment);
|
|
};
|
|
|
|
GrowableArray<CodeComment*> comments_;
|
|
|
|
bool allow_constant_pool_;
|
|
|
|
void EmitType01(Condition cond,
|
|
int type,
|
|
Opcode opcode,
|
|
int set_cc,
|
|
Register rn,
|
|
Register rd,
|
|
Operand o);
|
|
|
|
void EmitType5(Condition cond, int32_t offset, bool link);
|
|
|
|
void EmitMemOp(Condition cond,
|
|
bool load,
|
|
bool byte,
|
|
Register rd,
|
|
Address ad);
|
|
|
|
void EmitMemOpAddressMode3(Condition cond,
|
|
int32_t mode,
|
|
Register rd,
|
|
Address ad);
|
|
|
|
void EmitMultiMemOp(Condition cond,
|
|
BlockAddressMode am,
|
|
bool load,
|
|
Register base,
|
|
RegList regs);
|
|
|
|
void EmitShiftImmediate(Condition cond,
|
|
Shift opcode,
|
|
Register rd,
|
|
Register rm,
|
|
Operand o);
|
|
|
|
void EmitShiftRegister(Condition cond,
|
|
Shift opcode,
|
|
Register rd,
|
|
Register rm,
|
|
Operand o);
|
|
|
|
void EmitMulOp(Condition cond,
|
|
int32_t opcode,
|
|
Register rd,
|
|
Register rn,
|
|
Register rm,
|
|
Register rs);
|
|
|
|
void EmitDivOp(Condition cond,
|
|
int32_t opcode,
|
|
Register rd,
|
|
Register rn,
|
|
Register rm);
|
|
|
|
void EmitMultiVSMemOp(Condition cond,
|
|
BlockAddressMode am,
|
|
bool load,
|
|
Register base,
|
|
SRegister start,
|
|
uint32_t count);
|
|
|
|
void EmitMultiVDMemOp(Condition cond,
|
|
BlockAddressMode am,
|
|
bool load,
|
|
Register base,
|
|
DRegister start,
|
|
int32_t count);
|
|
|
|
void EmitVFPsss(Condition cond,
|
|
int32_t opcode,
|
|
SRegister sd,
|
|
SRegister sn,
|
|
SRegister sm);
|
|
|
|
void EmitVFPddd(Condition cond,
|
|
int32_t opcode,
|
|
DRegister dd,
|
|
DRegister dn,
|
|
DRegister dm);
|
|
|
|
void EmitVFPsd(Condition cond,
|
|
int32_t opcode,
|
|
SRegister sd,
|
|
DRegister dm);
|
|
|
|
void EmitVFPds(Condition cond,
|
|
int32_t opcode,
|
|
DRegister dd,
|
|
SRegister sm);
|
|
|
|
void EmitSIMDqqq(int32_t opcode, OperandSize sz,
|
|
QRegister qd, QRegister qn, QRegister qm);
|
|
|
|
void EmitSIMDddd(int32_t opcode, OperandSize sz,
|
|
DRegister dd, DRegister dn, DRegister dm);
|
|
|
|
void EmitFarBranch(Condition cond, int32_t offset, bool link);
|
|
void EmitBranch(Condition cond, Label* label, bool link);
|
|
int32_t EncodeBranchOffset(int32_t offset, int32_t inst);
|
|
static int32_t DecodeBranchOffset(int32_t inst);
|
|
int32_t EncodeTstOffset(int32_t offset, int32_t inst);
|
|
int32_t DecodeTstOffset(int32_t inst);
|
|
|
|
void StoreIntoObjectFilter(Register object, Register value, Label* no_update);
|
|
|
|
// Shorter filtering sequence that assumes that value is not a smi.
|
|
void StoreIntoObjectFilterNoSmi(Register object,
|
|
Register value,
|
|
Label* no_update);
|
|
|
|
// Helpers for write-barrier verification.
|
|
|
|
// Returns VerifiedMemory::offset() as an Operand.
|
|
Operand GetVerifiedMemoryShadow();
|
|
// Writes value to [base + offset] and also its shadow location, if enabled.
|
|
void WriteShadowedField(Register base,
|
|
intptr_t offset,
|
|
Register value,
|
|
Condition cond = AL);
|
|
void WriteShadowedFieldPair(Register base,
|
|
intptr_t offset,
|
|
Register value_even,
|
|
Register value_odd,
|
|
Condition cond = AL);
|
|
// Writes new_value to address and its shadow location, if enabled, after
|
|
// verifying that its old value matches its shadow.
|
|
void VerifiedWrite(const Address& address,
|
|
Register new_value,
|
|
FieldContent old_content);
|
|
|
|
DISALLOW_ALLOCATION();
|
|
DISALLOW_COPY_AND_ASSIGN(Assembler);
|
|
};
|
|
|
|
} // namespace dart
|
|
|
|
#endif // VM_ASSEMBLER_ARM_H_
|