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fc919001c5
emission of comparison code. Improve instruction tracing in all simulators. R=zra@google.com Review URL: https://codereview.chromium.org//817593002 git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@42555 260f80e4-7a28-3924-810f-c04153c831b5
281 lines
9.6 KiB
C++
281 lines
9.6 KiB
C++
// Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
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// for details. All rights reserved. Use of this source code is governed by a
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// BSD-style license that can be found in the LICENSE file.
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// Declares a Simulator for ARM instructions if we are not generating a native
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// ARM binary. This Simulator allows us to run and debug ARM code generation on
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// regular desktop machines.
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// Dart calls into generated code by "calling" the InvokeDartCode stub,
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// which will start execution in the Simulator or forwards to the real entry
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// on a ARM HW platform.
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#ifndef VM_SIMULATOR_ARM_H_
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#define VM_SIMULATOR_ARM_H_
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#ifndef VM_SIMULATOR_H_
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#error Do not include simulator_arm.h directly; use simulator.h.
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#endif
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#include "vm/constants_arm.h"
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namespace dart {
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class Isolate;
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class Mutex;
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class RawObject;
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class SimulatorSetjmpBuffer;
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typedef struct {
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union {
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uint32_t u;
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float f;
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} data_[4];
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} simd_value_t;
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class Simulator {
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public:
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static const uword kSimulatorStackUnderflowSize = 64;
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Simulator();
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~Simulator();
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// The currently executing Simulator instance, which is associated to the
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// current isolate
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static Simulator* Current();
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// Accessors for register state. Reading the pc value adheres to the ARM
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// architecture specification and is off by 8 from the currently executing
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// instruction.
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void set_register(Register reg, int32_t value);
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int32_t get_register(Register reg) const;
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// Special case of set_register and get_register to access the raw PC value.
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void set_pc(int32_t value);
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int32_t get_pc() const;
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// Accessors for VFP register state.
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void set_sregister(SRegister reg, float value);
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float get_sregister(SRegister reg) const;
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void set_dregister(DRegister reg, double value);
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double get_dregister(DRegister reg) const;
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void set_qregister(QRegister reg, const simd_value_t& value);
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void get_qregister(QRegister reg, simd_value_t* value) const;
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// When moving integer (rather than floating point) values to/from
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// the FPU registers, use the _bits calls to avoid gcc taking liberties with
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// integers that map to such things as NaN floating point values.
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void set_sregister_bits(SRegister reg, int32_t value);
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int32_t get_sregister_bits(SRegister reg) const;
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void set_dregister_bits(DRegister reg, int64_t value);
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int64_t get_dregister_bits(DRegister reg) const;
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// Accessor to the internal simulator stack top.
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uword StackTop() const;
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// Accessor to the instruction counter.
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intptr_t get_icount() const { return icount_; }
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// The isolate's top_exit_frame_info refers to a Dart frame in the simulator
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// stack. The simulator's top_exit_frame_info refers to a C++ frame in the
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// native stack.
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uword top_exit_frame_info() const { return top_exit_frame_info_; }
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void set_top_exit_frame_info(uword value) { top_exit_frame_info_ = value; }
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// Call on program start.
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static void InitOnce();
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// Dart generally calls into generated code with 5 parameters. This is a
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// convenience function, which sets up the simulator state and grabs the
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// result on return. When fp_return is true the return value is the D0
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// floating point register. Otherwise, the return value is R1:R0.
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// If fp_args is true, the parameters0-3 are placed in S0-3. Otherwise, they
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// are placed in R0-3.
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int64_t Call(int32_t entry,
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int32_t parameter0,
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int32_t parameter1,
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int32_t parameter2,
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int32_t parameter3,
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bool fp_return = false,
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bool fp_args = false);
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// Implementation of atomic compare and exchange in the same synchronization
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// domain as other synchronization primitive instructions (e.g. ldrex, strex).
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static uword CompareExchange(uword* address,
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uword compare_value,
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uword new_value);
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// Runtime and native call support.
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enum CallKind {
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kRuntimeCall,
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kLeafRuntimeCall,
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kLeafFloatRuntimeCall,
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kBootstrapNativeCall,
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kNativeCall
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};
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static uword RedirectExternalReference(uword function,
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CallKind call_kind,
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int argument_count);
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static uword FunctionForRedirect(uword redirect);
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void Longjmp(uword pc,
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uword sp,
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uword fp,
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RawObject* raw_exception,
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RawObject* raw_stacktrace,
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Isolate* isolate);
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private:
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// Known bad pc value to ensure that the simulator does not execute
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// without being properly setup.
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static const uword kBadLR = -1;
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// A pc value used to signal the simulator to stop execution. Generally
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// the lr is set to this value on transition from native C code to
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// simulated execution, so that the simulator can "return" to the native
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// C code.
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static const uword kEndSimulatingPC = -2;
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// CPU state.
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int32_t registers_[kNumberOfCpuRegisters];
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bool n_flag_;
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bool z_flag_;
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bool c_flag_;
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bool v_flag_;
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// VFP state.
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union { // S, D, and Q register banks are overlapping.
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int32_t sregisters_[kNumberOfSRegisters];
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int64_t dregisters_[kNumberOfDRegisters];
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simd_value_t qregisters_[kNumberOfQRegisters];
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};
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bool fp_n_flag_;
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bool fp_z_flag_;
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bool fp_c_flag_;
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bool fp_v_flag_;
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// Simulator support.
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char* stack_;
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bool pc_modified_;
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intptr_t icount_;
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static int32_t flag_stop_sim_at_;
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SimulatorSetjmpBuffer* last_setjmp_buffer_;
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uword top_exit_frame_info_;
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// Registered breakpoints.
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Instr* break_pc_;
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int32_t break_instr_;
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// Illegal memory access support.
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static bool IsIllegalAddress(uword addr) {
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return addr < 64*1024;
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}
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void HandleIllegalAccess(uword addr, Instr* instr);
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// Handles a legal instruction that the simulator does not implement.
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void UnimplementedInstruction(Instr* instr);
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// Unsupported instructions use Format to print an error and stop execution.
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void Format(Instr* instr, const char* format);
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// Checks if the current instruction should be executed based on its
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// condition bits.
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bool ConditionallyExecute(Instr* instr);
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// Helper functions to set the conditional flags in the architecture state.
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void SetNZFlags(int32_t val);
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void SetCFlag(bool val);
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void SetVFlag(bool val);
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bool CarryFrom(int32_t left, int32_t right, int32_t carry);
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bool OverflowFrom(int32_t left, int32_t right, int32_t carry);
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// Helper functions to decode common "addressing" modes.
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int32_t GetShiftRm(Instr* instr, bool* carry_out);
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int32_t GetImm(Instr* instr, bool* carry_out);
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void HandleRList(Instr* instr, bool load);
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void SupervisorCall(Instr* instr);
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// Read and write memory.
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void UnalignedAccess(const char* msg, uword addr, Instr* instr);
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// Perform a division.
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void DoDivision(Instr* instr);
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inline uint8_t ReadBU(uword addr);
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inline int8_t ReadB(uword addr);
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inline void WriteB(uword addr, uint8_t value);
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inline uint16_t ReadHU(uword addr, Instr* instr);
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inline int16_t ReadH(uword addr, Instr* instr);
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inline void WriteH(uword addr, uint16_t value, Instr* instr);
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inline intptr_t ReadW(uword addr, Instr* instr);
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inline void WriteW(uword addr, intptr_t value, Instr* instr);
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// Synchronization primitives support.
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void ClearExclusive();
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intptr_t ReadExclusiveW(uword addr, Instr* instr);
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intptr_t WriteExclusiveW(uword addr, intptr_t value, Instr* instr);
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// In Dart, there is at most one thread per isolate.
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// We keep track of 16 exclusive access address tags across all isolates.
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// Since we cannot simulate a native context switch, which clears
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// the exclusive access state of the local monitor (using the CLREX
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// instruction), we associate the isolate requesting exclusive access to the
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// address tag. Multiple isolates requesting exclusive access (using the LDREX
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// instruction) to the same address will result in multiple address tags being
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// created for the same address, one per isolate.
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// At any given time, each isolate is associated to at most one address tag.
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static Mutex* exclusive_access_lock_;
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static const int kNumAddressTags = 16;
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static struct AddressTag {
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Isolate* isolate;
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uword addr;
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} exclusive_access_state_[kNumAddressTags];
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static int next_address_tag_;
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// Set access to given address to 'exclusive state' for current isolate.
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static void SetExclusiveAccess(uword addr);
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// Returns true if the current isolate has exclusive access to given address,
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// returns false otherwise. In either case, set access to given address to
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// 'open state' for all isolates.
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// If given addr is NULL, set access to 'open state' for current
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// isolate (CLREX).
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static bool HasExclusiveAccessAndOpen(uword addr);
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// Executing is handled based on the instruction type.
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void DecodeType01(Instr* instr); // Both type 0 and type 1 rolled into one.
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void DecodeType2(Instr* instr);
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void DecodeType3(Instr* instr);
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void DecodeType4(Instr* instr);
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void DecodeType5(Instr* instr);
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void DecodeType6(Instr* instr);
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void DecodeType7(Instr* instr);
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void DecodeSIMDDataProcessing(Instr* instr);
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// Executes one instruction.
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void InstructionDecode(Instr* instr);
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// Executes ARM instructions until the PC reaches kEndSimulatingPC.
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void Execute();
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// Returns true if tracing of executed instructions is enabled.
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bool IsTracingExecution() const;
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// Longjmp support for exceptions.
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SimulatorSetjmpBuffer* last_setjmp_buffer() {
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return last_setjmp_buffer_;
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}
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void set_last_setjmp_buffer(SimulatorSetjmpBuffer* buffer) {
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last_setjmp_buffer_ = buffer;
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}
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friend class SimulatorDebugger;
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friend class SimulatorSetjmpBuffer;
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DISALLOW_COPY_AND_ASSIGN(Simulator);
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};
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} // namespace dart
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#endif // VM_SIMULATOR_ARM_H_
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