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[vm] Some pieces for Windows ARM support.
TEST=ci Bug: https://github.com/dart-lang/sdk/issues/47824 Change-Id: Iaf401f4d25fc5bf171170728d4a5d3ae6ef17527 Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/239369 Reviewed-by: Alexander Aprelev <aam@google.com> Commit-Queue: Ryan Macnak <rmacnak@google.com>
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@ -200,10 +200,10 @@ struct simd128_value_t {
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#elif defined(_M_IX86) || defined(__i386__)
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#define HOST_ARCH_IA32 1
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#define ARCH_IS_32_BIT 1
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#elif defined(__ARMEL__)
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#elif defined(_M_ARM) || defined(__ARMEL__)
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#define HOST_ARCH_ARM 1
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#define ARCH_IS_32_BIT 1
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#elif defined(__aarch64__)
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#elif defined(_M_ARM64) || defined(__aarch64__)
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#define HOST_ARCH_ARM64 1
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#define ARCH_IS_64_BIT 1
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#elif defined(__riscv)
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@ -1610,6 +1610,10 @@ void Assembler::SetupCSPFromThread(Register thr) {
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// frames before doing an overflow check.)
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ldr(TMP, Address(thr, target::Thread::saved_stack_limit_offset()));
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AddImmediate(CSP, TMP, -4096);
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// TODO(47824): This will probably cause signal handlers on Windows to crash.
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// Windows requires the stack to grow in order, one page at a time, but
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// pushing CSP to near the stack limit likely skips over many pages.
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}
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void Assembler::RestoreCSP() {
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@ -49,7 +49,7 @@ namespace dart {
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// The Linux/Android ABI and the iOS ABI differ in their choice of frame
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// pointer, their treatment of R9, and the interprocedural stack alignment.
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// EABI (Linux, Android)
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// EABI (Linux, Android, Windows)
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// See "Procedure Call Standard for the ARM Architecture".
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// R0-R1: Argument / result / volatile
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// R2-R3: Argument / volatile
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@ -61,9 +61,10 @@ namespace dart {
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// R15: Program counter
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// Stack alignment: 4 bytes always, 8 bytes at public interfaces
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// Linux (Debian armhf) and Android also differ in whether floating point
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// arguments are passed in floating point registers. Linux uses hardfp and
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// Android uses softfp. See TargetCPUFeatures::hardfp_supported().
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// Linux (Debian armhf), Windows and Android also differ in whether floating
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// point arguments are passed in floating point registers. Linux and Windows
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// use hardfp and Android uses softfp. See
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// TargetCPUFeatures::hardfp_supported().
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// iOS ABI
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// See "iOS ABI Function Call Guide"
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@ -92,7 +93,7 @@ enum Register {
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R8 = 8,
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R9 = 9,
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R10 = 10, // THR
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R11 = 11, // Linux FP
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R11 = 11, // Linux/Android/Windows FP
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R12 = 12, // IP aka TMP
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R13 = 13, // SP
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R14 = 14, // LR
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@ -49,7 +49,7 @@ enum Register {
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R15 = 15, // SP in Dart code.
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R16 = 16, // IP0 aka TMP
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R17 = 17, // IP1 aka TMP2
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R18 = 18, // reserved on iOS, shadow call stack on Fuchsia.
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R18 = 18, // reserved on iOS, shadow call stack on Fuchsia, TEB on Windows.
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R19 = 19,
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R20 = 20,
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R21 = 21, // DISPATCH_TABLE_REG
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@ -16,6 +16,8 @@
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#if defined(DART_HOST_OS_IOS)
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#include <libkern/OSCacheControl.h>
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#elif defined(DART_HOST_OS_WINDOWS)
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#include <processthreadsapi.h>
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#endif
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#if !defined(TARGET_HOST_MISMATCH)
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@ -88,6 +90,10 @@ void CPU::FlushICache(uword start, uword size) {
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__builtin___clear_cache(beg, end);
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#elif defined(DART_HOST_OS_ANDROID)
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cacheflush(start, start + size, 0);
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#elif defined(DART_HOST_OS_WINDOWS)
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BOOL result = FlushInstructionCache(
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GetCurrentProcess(), reinterpret_cast<const void*>(start), size);
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ASSERT(result != 0);
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#else
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#error FlushICache only tested/supported on Linux, Android and iOS
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#endif
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@ -126,6 +132,16 @@ void HostCPUFeatures::Init() {
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initialized_ = true;
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#endif
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}
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#elif DART_HOST_OS_WINDOWS
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void HostCPUFeatures::Init() {
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hardware_ = "";
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integer_division_supported_ = true;
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neon_supported_ = true;
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hardfp_supported_ = true;
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#if defined(DEBUG)
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initialized_ = true;
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#endif
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}
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#else // DART_HOST_OS_IOS
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void HostCPUFeatures::Init() {
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bool is_arm64 = false;
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@ -22,6 +22,8 @@
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#if defined(DART_HOST_OS_MACOS) || defined(DART_HOST_OS_IOS)
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#include <libkern/OSCacheControl.h>
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#elif defined(DART_HOST_OS_WINDOWS)
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#include <processthreadsapi.h>
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#endif
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namespace dart {
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@ -52,6 +54,10 @@ void CPU::FlushICache(uword start, uword size) {
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zx_status_t result = zx_cache_flush(reinterpret_cast<const void*>(start),
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size, ZX_CACHE_FLUSH_INSN);
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ASSERT(result == ZX_OK);
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#elif defined(DART_HOST_OS_WINDOWS)
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BOOL result = FlushInstructionCache(
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GetCurrentProcess(), reinterpret_cast<const void*>(start), size);
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ASSERT(result != 0);
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#else
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#error FlushICache not implemented for this OS
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#endif
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@ -172,14 +172,10 @@ bool OSThread::Compare(ThreadId a, ThreadId b) {
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}
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bool OSThread::GetCurrentStackBounds(uword* lower, uword* upper) {
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// On Windows stack limits for the current thread are available in
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// the thread information block (TIB). Its fields can be accessed through
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// FS segment register on x86 and GS segment register on x86_64.
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#ifdef _WIN64
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*upper = static_cast<uword>(__readgsqword(offsetof(NT_TIB64, StackBase)));
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#else
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*upper = static_cast<uword>(__readfsdword(offsetof(NT_TIB, StackBase)));
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#endif
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// On Windows stack limits for the current thread are available in
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// the thread information block (TIB).
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NT_TIB* tib = reinterpret_cast<NT_TIB*>(NtCurrentTeb());
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*upper = reinterpret_cast<uword>(tib->StackBase);
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// Notice that we cannot use the TIB's StackLimit for the stack end, as it
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// tracks the end of the committed range. We're after the end of the reserved
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// stack area (most of which will be uncommitted, most times).
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