diff --git a/pkg/dev_compiler/tool/ddc b/pkg/dev_compiler/tool/ddc
index 493f53120c3..4fff33d1b43 100755
--- a/pkg/dev_compiler/tool/ddc
+++ b/pkg/dev_compiler/tool/ddc
@@ -30,8 +30,7 @@ then
   DIRS=$( ls "$OUT_DIR" )
   # list of possible configurations in decreasing desirability
   CONFIGS=("ReleaseX64" "ReleaseIA32" "DebugX64" "DebugIA32"
-    "ReleaseARM"    "ReleaseARM64"    "ReleaseARMV5TE"
-    "DebugARM"      "DebugARM64"      "DebugARMV5TE")
+    "ReleaseARM" "ReleaseARM64" "DebugARM" "DebugARM64")
   DART_CONFIGURATION="None"
   for CONFIG in ${CONFIGS[*]}
   do
diff --git a/pkg/pkg.status b/pkg/pkg.status
index 5b741e216e2..738bd38ce43 100644
--- a/pkg/pkg.status
+++ b/pkg/pkg.status
@@ -210,7 +210,7 @@ analyzer/test/src/task/strong/front_end_inference_test: Slow
 
 # Timeout. These tests do not run efficiently on our simulator or low-end
 # devices.
-[ $runtime == vm && ($arch == armv5te || $arch == armv6 || $arch == simarm || $arch == simarm64 || $arch == simarmv5te || $arch == simarmv6 || $arch == simdbc64) ]
+[ $runtime == vm && ($arch == armv6 || $arch == simarm || $arch == simarm64 || $arch == simarmv6 || $arch == simdbc64) ]
 *: Skip
 
 [ $arch != x64 || $compiler != none || $mode != release || $runtime != vm ]
diff --git a/pkg/smith/lib/configuration.dart b/pkg/smith/lib/configuration.dart
index ac3df99eac7..9ead7e0d42f 100644
--- a/pkg/smith/lib/configuration.dart
+++ b/pkg/smith/lib/configuration.dart
@@ -553,11 +553,9 @@ class Architecture extends NamedEnum {
   static const arm = Architecture._('arm');
   static const arm_x64 = Architecture._('arm_x64');
   static const armv6 = Architecture._('armv6');
-  static const armv5te = Architecture._('armv5te');
   static const arm64 = Architecture._('arm64');
   static const simarm = Architecture._('simarm');
   static const simarmv6 = Architecture._('simarmv6');
-  static const simarmv5te = Architecture._('simarmv5te');
   static const simarm64 = Architecture._('simarm64');
   static const simdbc = Architecture._('simdbc');
   static const simdbc64 = Architecture._('simdbc64');
@@ -569,12 +567,10 @@ class Architecture extends NamedEnum {
     x64,
     arm,
     armv6,
-    armv5te,
     arm_x64,
     arm64,
     simarm,
     simarmv6,
-    simarmv5te,
     simarm64,
     simdbc,
     simdbc64
diff --git a/pkg/status_file/test/data/vm.status b/pkg/status_file/test/data/vm.status
index 5cb581de754..f62053eb694 100644
--- a/pkg/status_file/test/data/vm.status
+++ b/pkg/status_file/test/data/vm.status
@@ -51,7 +51,7 @@ cc/Read: Fail  # TODO(zra): Investigate, ../../dart/runtime/bin/file_test.cc: 34
 # On the simluator stack traces produced by the Profiler do not match
 # up with the real Dart stack trace and hence we don't get correct
 # symbol names.
-[ $arch == simarm || $arch == simarmv6 || $arch == simarmv5te || $arch == simarm64 || $arch == simdbc  || $arch == simdbc64 ]
+[ $arch == simarm || $arch == simarmv6 || $arch == simarm64 || $arch == simdbc  || $arch == simdbc64 ]
 cc/Service_Profile: Skip
 cc/Profiler_AllocationSampleTest: Skip
 cc/Profiler_ArrayAllocation: Skip
diff --git a/pkg/test_runner/lib/src/options.dart b/pkg/test_runner/lib/src/options.dart
index eaec1c55d15..3a4352bfba3 100644
--- a/pkg/test_runner/lib/src/options.dart
+++ b/pkg/test_runner/lib/src/options.dart
@@ -141,8 +141,8 @@ none:             No runtime, compile only.''',
 Allowed values are:
 all
 ia32, x64
-arm, armv6, armv5te, arm64,
-simarm, simarmv6, simarmv5te, simarm64,
+arm, armv6, arm64,
+simarm, simarmv6, simarm64,
 simdbc, simdbc64, arm_x64''',
         abbr: 'a',
         values: ['all']..addAll(Architecture.names),
diff --git a/pkg/test_runner/lib/src/runtime_configuration.dart b/pkg/test_runner/lib/src/runtime_configuration.dart
index 7cb3cda1d55..839137568d6 100644
--- a/pkg/test_runner/lib/src/runtime_configuration.dart
+++ b/pkg/test_runner/lib/src/runtime_configuration.dart
@@ -233,8 +233,6 @@ class DartVmRuntimeConfiguration extends RuntimeConfiguration {
       case Architecture.arm64:
       case Architecture.simarmv6:
       case Architecture.armv6:
-      case Architecture.simarmv5te:
-      case Architecture.armv5te:
       case Architecture.simarm64:
       case Architecture.simdbc:
       case Architecture.simdbc64:
diff --git a/runtime/BUILD.gn b/runtime/BUILD.gn
index 2968ee6719b..2e65496ea34 100644
--- a/runtime/BUILD.gn
+++ b/runtime/BUILD.gn
@@ -100,9 +100,6 @@ config("dart_arch_config") {
   } else if (dart_target_arch == "armv6") {
     defines += [ "TARGET_ARCH_ARM" ]
     defines += [ "TARGET_ARCH_ARM_6" ]
-  } else if (dart_target_arch == "armv5te") {
-    defines += [ "TARGET_ARCH_ARM" ]
-    defines += [ "TARGET_ARCH_ARM_5TE" ]
   } else if (dart_target_arch == "arm64") {
     defines += [ "TARGET_ARCH_ARM64" ]
   } else if (dart_target_arch == "x64") {
diff --git a/runtime/platform/globals.h b/runtime/platform/globals.h
index d754abfcdbd..7e368fecfd4 100644
--- a/runtime/platform/globals.h
+++ b/runtime/platform/globals.h
@@ -419,12 +419,6 @@ typedef simd128_value_t fpu_register_t;
 #define DUAL_MAPPING_SUPPORTED 1
 #endif
 
-// Disable background threads by default on armv5te. The relevant
-// implementations are uniprocessors.
-#if !defined(TARGET_ARCH_ARM_5TE)
-#define ARCH_IS_MULTI_CORE 1
-#endif
-
 // Short form printf format specifiers
 #define Pd PRIdPTR
 #define Pu PRIuPTR
diff --git a/runtime/tests/vm/vm.status b/runtime/tests/vm/vm.status
index 9962efee4e0..c91d02ea116 100644
--- a/runtime/tests/vm/vm.status
+++ b/runtime/tests/vm/vm.status
@@ -192,7 +192,7 @@ cc/GenKernelKernelReadAllBytecode: SkipByDesign # No interpreter support.
 # On the simluator stack traces produced by the Profiler do not match
 # up with the real Dart stack trace and hence we don't get correct
 # symbol names.
-[ $arch == simarm || $arch == simarm64 || $arch == simarmv5te || $arch == simarmv6 || $arch == simdbc || $arch == simdbc64 ]
+[ $arch == simarm || $arch == simarm64 || $arch == simarmv6 || $arch == simdbc || $arch == simdbc64 ]
 cc/LargeMap: SkipByDesign
 cc/Profiler_AllocationSampleTest: SkipByDesign
 cc/Profiler_ArrayAllocation: SkipByDesign
diff --git a/runtime/vm/compiler/assembler/assembler_arm.cc b/runtime/vm/compiler/assembler/assembler_arm.cc
index e2e07a3ae8e..b5732507351 100644
--- a/runtime/vm/compiler/assembler/assembler_arm.cc
+++ b/runtime/vm/compiler/assembler/assembler_arm.cc
@@ -418,15 +418,8 @@ void Assembler::umaal(Register rd_lo,
   ASSERT(rd_hi != IP);
   ASSERT(rn != IP);
   ASSERT(rm != IP);
-  if (TargetCPUFeatures::arm_version() != ARMv5TE) {
-    // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
-    EmitMulOp(AL, B22, rd_lo, rd_hi, rn, rm);
-  } else {
-    mov(IP, Operand(0));
-    umlal(rd_lo, IP, rn, rm);
-    adds(rd_lo, rd_lo, Operand(rd_hi));
-    adc(rd_hi, IP, Operand(0));
-  }
+  // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
+  EmitMulOp(AL, B22, rd_lo, rd_hi, rn, rm);
 }
 
 void Assembler::EmitDivOp(Condition cond,
@@ -493,12 +486,7 @@ void Assembler::ldrd(Register rd,
                      Condition cond) {
   ASSERT((rd % 2) == 0);
   ASSERT(rd2 == rd + 1);
-  if (TargetCPUFeatures::arm_version() == ARMv5TE) {
-    ldr(rd, Address(rn, offset), cond);
-    ldr(rd2, Address(rn, offset + target::kWordSize), cond);
-  } else {
-    EmitMemOpAddressMode3(cond, B7 | B6 | B4, rd, Address(rn, offset));
-  }
+  EmitMemOpAddressMode3(cond, B7 | B6 | B4, rd, Address(rn, offset));
 }
 
 void Assembler::strd(Register rd,
@@ -508,12 +496,7 @@ void Assembler::strd(Register rd,
                      Condition cond) {
   ASSERT((rd % 2) == 0);
   ASSERT(rd2 == rd + 1);
-  if (TargetCPUFeatures::arm_version() == ARMv5TE) {
-    str(rd, Address(rn, offset), cond);
-    str(rd2, Address(rn, offset + target::kWordSize), cond);
-  } else {
-    EmitMemOpAddressMode3(cond, B7 | B6 | B5 | B4, rd, Address(rn, offset));
-  }
+  EmitMemOpAddressMode3(cond, B7 | B6 | B5 | B4, rd, Address(rn, offset));
 }
 
 void Assembler::ldm(BlockAddressMode am,
@@ -533,7 +516,6 @@ void Assembler::stm(BlockAddressMode am,
 }
 
 void Assembler::ldrex(Register rt, Register rn, Condition cond) {
-  ASSERT(TargetCPUFeatures::arm_version() != ARMv5TE);
   ASSERT(rn != kNoRegister);
   ASSERT(rt != kNoRegister);
   ASSERT(cond != kNoCondition);
@@ -545,7 +527,6 @@ void Assembler::ldrex(Register rt, Register rn, Condition cond) {
 }
 
 void Assembler::strex(Register rd, Register rt, Register rn, Condition cond) {
-  ASSERT(TargetCPUFeatures::arm_version() != ARMv5TE);
   ASSERT(rn != kNoRegister);
   ASSERT(rd != kNoRegister);
   ASSERT(rt != kNoRegister);
@@ -562,7 +543,7 @@ void Assembler::EnterSafepoint(Register addr, Register state) {
   // We generate the same number of instructions whether or not the slow-path is
   // forced. This simplifies GenerateJitCallbackTrampolines.
   Label slow_path, done, retry;
-  if (FLAG_use_slow_path || TargetCPUFeatures::arm_version() == ARMv5TE) {
+  if (FLAG_use_slow_path) {
     b(&slow_path);
   }
 
@@ -578,7 +559,7 @@ void Assembler::EnterSafepoint(Register addr, Register state) {
   cmp(TMP, Operand(0));  // 0 means strex was successful.
   b(&done, EQ);
 
-  if (!FLAG_use_slow_path && TargetCPUFeatures::arm_version() != ARMv5TE) {
+  if (!FLAG_use_slow_path) {
     b(&retry);
   }
 
@@ -614,7 +595,7 @@ void Assembler::ExitSafepoint(Register addr, Register state) {
   // We generate the same number of instructions whether or not the slow-path is
   // forced, for consistency with EnterSafepoint.
   Label slow_path, done, retry;
-  if (FLAG_use_slow_path || TargetCPUFeatures::arm_version() == ARMv5TE) {
+  if (FLAG_use_slow_path) {
     b(&slow_path);
   }
 
@@ -630,7 +611,7 @@ void Assembler::ExitSafepoint(Register addr, Register state) {
   cmp(TMP, Operand(0));  // 0 means strex was successful.
   b(&done, EQ);
 
-  if (!FLAG_use_slow_path && TargetCPUFeatures::arm_version() != ARMv5TE) {
+  if (!FLAG_use_slow_path) {
     b(&retry);
   }
 
@@ -673,7 +654,6 @@ void Assembler::TransitionNativeToGenerated(Register addr,
 }
 
 void Assembler::clrex() {
-  ASSERT(TargetCPUFeatures::arm_version() != ARMv5TE);
   int32_t encoding = (kSpecialCondition << kConditionShift) | B26 | B24 | B22 |
                      B21 | B20 | (0xff << 12) | B4 | 0xf;
   Emit(encoding);
@@ -894,13 +874,13 @@ void Assembler::EmitMultiVDMemOp(Condition cond,
   ASSERT(cond != kNoCondition);
   ASSERT(start != kNoDRegister);
   ASSERT(static_cast<int32_t>(start) + count <= kNumberOfDRegisters);
-  const int armv5te = TargetCPUFeatures::arm_version() == ARMv5TE ? 1 : 0;
+  const int notArmv5te = 0;
 
   int32_t encoding =
       (static_cast<int32_t>(cond) << kConditionShift) | B27 | B26 | B11 | B9 |
       B8 | am | (load ? L : 0) | ArmEncode::Rn(base) |
       ((static_cast<int32_t>(start) & 0x10) ? D : 0) |
-      ((static_cast<int32_t>(start) & 0xf) << 12) | (count << 1) | armv5te;
+      ((static_cast<int32_t>(start) & 0xf) << 12) | (count << 1) | notArmv5te;
   Emit(encoding);
 }
 
@@ -2075,7 +2055,7 @@ class PatchFarBranch : public AssemblerFixup {
 
   void Process(const MemoryRegion& region, intptr_t position) {
     const ARMVersion version = TargetCPUFeatures::arm_version();
-    if ((version == ARMv5TE) || (version == ARMv6)) {
+    if (version == ARMv6) {
       ProcessARMv6(region, position);
     } else {
       ASSERT(version == ARMv7);
@@ -2329,7 +2309,7 @@ void Assembler::BindARMv7(Label* label) {
 
 void Assembler::Bind(Label* label) {
   const ARMVersion version = TargetCPUFeatures::arm_version();
-  if ((version == ARMv5TE) || (version == ARMv6)) {
+  if (version == ARMv6) {
     BindARMv6(label);
   } else {
     ASSERT(version == ARMv7);
@@ -2788,7 +2768,7 @@ void Assembler::LoadPatchableImmediate(Register rd,
                                        int32_t value,
                                        Condition cond) {
   const ARMVersion version = TargetCPUFeatures::arm_version();
-  if ((version == ARMv5TE) || (version == ARMv6)) {
+  if (version == ARMv6) {
     // This sequence is patched in a few places, and should remain fixed.
     const uint32_t byte0 = (value & 0x000000ff);
     const uint32_t byte1 = (value & 0x0000ff00) >> 8;
@@ -2811,7 +2791,7 @@ void Assembler::LoadDecodableImmediate(Register rd,
                                        int32_t value,
                                        Condition cond) {
   const ARMVersion version = TargetCPUFeatures::arm_version();
-  if ((version == ARMv5TE) || (version == ARMv6)) {
+  if (version == ARMv6) {
     if (constant_pool_allowed()) {
       const int32_t offset =
           target::ObjectPool::element_offset(FindImmediate(value));
diff --git a/runtime/vm/compiler/assembler/assembler_arm.h b/runtime/vm/compiler/assembler/assembler_arm.h
index 1180d8bd3ec..cd26332f8cc 100644
--- a/runtime/vm/compiler/assembler/assembler_arm.h
+++ b/runtime/vm/compiler/assembler/assembler_arm.h
@@ -504,8 +504,7 @@ class Assembler : public AssemblerBase {
   void ldrsh(Register rd, Address ad, Condition cond = AL);
 
   // ldrd and strd actually support the full range of addressing modes, but
-  // we don't use them, and we need to split them up into two instructions for
-  // ARMv5TE, so we only support the base + offset mode.
+  // we don't use them, so we only support the base + offset mode.
   // rd must be an even register and rd2 must be rd + 1.
   void ldrd(Register rd,
             Register rd2,
diff --git a/runtime/vm/compiler/assembler/assembler_arm_test.cc b/runtime/vm/compiler/assembler/assembler_arm_test.cc
index 2a51064e5f6..b11603ff267 100644
--- a/runtime/vm/compiler/assembler/assembler_arm_test.cc
+++ b/runtime/vm/compiler/assembler/assembler_arm_test.cc
@@ -749,49 +749,41 @@ ASSEMBLER_TEST_RUN(LoadStore, test) {
 }
 
 ASSEMBLER_TEST_GENERATE(Semaphore, assembler) {
-  if (TargetCPUFeatures::arm_version() != ARMv5TE) {
-    __ mov(R0, Operand(40));
-    __ mov(R1, Operand(42));
-    __ Push(R0);
-    Label retry;
-    __ Bind(&retry);
-    __ ldrex(R0, SP);
-    __ strex(IP, R1, SP);  // IP == 0, success
-    __ tst(IP, Operand(0));
-    __ b(&retry, NE);  // NE if context switch occurred between ldrex and strex.
-    __ Pop(R0);        // 42
-  }
+  __ mov(R0, Operand(40));
+  __ mov(R1, Operand(42));
+  __ Push(R0);
+  Label retry;
+  __ Bind(&retry);
+  __ ldrex(R0, SP);
+  __ strex(IP, R1, SP);  // IP == 0, success
+  __ tst(IP, Operand(0));
+  __ b(&retry, NE);  // NE if context switch occurred between ldrex and strex.
+  __ Pop(R0);        // 42
   __ bx(LR);
 }
 
 ASSEMBLER_TEST_RUN(Semaphore, test) {
   EXPECT(test != NULL);
-  if (TargetCPUFeatures::arm_version() != ARMv5TE) {
-    typedef int (*Semaphore)() DART_UNUSED;
-    EXPECT_EQ(42, EXECUTE_TEST_CODE_INT32(Semaphore, test->entry()));
-  }
+  typedef int (*Semaphore)() DART_UNUSED;
+  EXPECT_EQ(42, EXECUTE_TEST_CODE_INT32(Semaphore, test->entry()));
 }
 
 ASSEMBLER_TEST_GENERATE(FailedSemaphore, assembler) {
-  if (TargetCPUFeatures::arm_version() != ARMv5TE) {
-    __ mov(R0, Operand(40));
-    __ mov(R1, Operand(42));
-    __ Push(R0);
-    __ ldrex(R0, SP);
-    __ clrex();            // Simulate a context switch.
-    __ strex(IP, R1, SP);  // IP == 1, failure
-    __ Pop(R0);            // 40
-    __ add(R0, R0, Operand(IP));
-  }
+  __ mov(R0, Operand(40));
+  __ mov(R1, Operand(42));
+  __ Push(R0);
+  __ ldrex(R0, SP);
+  __ clrex();            // Simulate a context switch.
+  __ strex(IP, R1, SP);  // IP == 1, failure
+  __ Pop(R0);            // 40
+  __ add(R0, R0, Operand(IP));
   __ bx(LR);
 }
 
 ASSEMBLER_TEST_RUN(FailedSemaphore, test) {
   EXPECT(test != NULL);
-  if (TargetCPUFeatures::arm_version() != ARMv5TE) {
-    typedef int (*FailedSemaphore)() DART_UNUSED;
-    EXPECT_EQ(41, EXECUTE_TEST_CODE_INT32(FailedSemaphore, test->entry()));
-  }
+  typedef int (*FailedSemaphore)() DART_UNUSED;
+  EXPECT_EQ(41, EXECUTE_TEST_CODE_INT32(FailedSemaphore, test->entry()));
 }
 
 ASSEMBLER_TEST_GENERATE(AddSub, assembler) {
diff --git a/runtime/vm/compiler/assembler/disassembler_arm.cc b/runtime/vm/compiler/assembler/disassembler_arm.cc
index b82632d6e37..50795497514 100644
--- a/runtime/vm/compiler/assembler/disassembler_arm.cc
+++ b/runtime/vm/compiler/assembler/disassembler_arm.cc
@@ -687,10 +687,6 @@ void ARMDecoder::DecodeType01(Instr* instr) {
             break;
           }
           case 2: {
-            if (TargetCPUFeatures::arm_version() == ARMv5TE) {
-              Unknown(instr);
-              return;
-            }
             // Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
             Format(instr, "umaal'cond's 'rd, 'rn, 'rm, 'rs");
             break;
@@ -725,11 +721,6 @@ void ARMDecoder::DecodeType01(Instr* instr) {
           }
         }
       } else {
-        if (TargetCPUFeatures::arm_version() == ARMv5TE) {
-          // strex and ldrex are only supported after ARMv6.
-          Unknown(instr);
-          return;
-        }
         // synchronization primitives
         switch (instr->Bits(20, 4)) {
           case 8: {
@@ -1433,8 +1424,7 @@ void ARMDecoder::InstructionDecode(uword pc) {
   Instr* instr = Instr::At(pc);
 
   if (instr->ConditionField() == kSpecialCondition) {
-    if ((instr->InstructionBits() == static_cast<int32_t>(0xf57ff01f)) &&
-        (TargetCPUFeatures::arm_version() != ARMv5TE)) {
+    if (instr->InstructionBits() == static_cast<int32_t>(0xf57ff01f)) {
       Format(instr, "clrex");
     } else {
       if (instr->IsSIMDDataProcessing()) {
diff --git a/runtime/vm/compiler/stub_code_compiler_arm.cc b/runtime/vm/compiler/stub_code_compiler_arm.cc
index fb8c1e883b8..f5069027192 100644
--- a/runtime/vm/compiler/stub_code_compiler_arm.cc
+++ b/runtime/vm/compiler/stub_code_compiler_arm.cc
@@ -1659,27 +1659,17 @@ static void GenerateWriteBarrierStubHelper(Assembler* assembler,
   // Save values being destroyed.
   __ PushList((1 << R2) | (1 << R3) | (1 << R4));
 
-  if (TargetCPUFeatures::arm_version() == ARMv5TE) {
-// TODO(21263): Implement 'swp' and use it below.
-#if !defined(USING_SIMULATOR)
-    ASSERT(OS::NumberOfAvailableProcessors() <= 1);
-#endif
-    __ ldr(R2, FieldAddress(R1, target::Object::tags_offset()));
-    __ bic(R2, R2, Operand(1 << target::RawObject::kOldAndNotRememberedBit));
-    __ str(R2, FieldAddress(R1, target::Object::tags_offset()));
-  } else {
-    // Atomically set the remembered bit of the object header.
-    ASSERT(target::Object::tags_offset() == 0);
-    __ sub(R3, R1, Operand(kHeapObjectTag));
-    // R3: Untagged address of header word (ldrex/strex do not support offsets).
-    Label retry;
-    __ Bind(&retry);
-    __ ldrex(R2, R3);
-    __ bic(R2, R2, Operand(1 << target::RawObject::kOldAndNotRememberedBit));
-    __ strex(R4, R2, R3);
-    __ cmp(R4, Operand(1));
-    __ b(&retry, EQ);
-  }
+  // Atomically set the remembered bit of the object header.
+  ASSERT(target::Object::tags_offset() == 0);
+  __ sub(R3, R1, Operand(kHeapObjectTag));
+  // R3: Untagged address of header word (ldrex/strex do not support offsets).
+  Label retry;
+  __ Bind(&retry);
+  __ ldrex(R2, R3);
+  __ bic(R2, R2, Operand(1 << target::RawObject::kOldAndNotRememberedBit));
+  __ strex(R4, R2, R3);
+  __ cmp(R4, Operand(1));
+  __ b(&retry, EQ);
 
   // Load the StoreBuffer block out of the thread. Then load top_ out of the
   // StoreBufferBlock and add the address to the pointers_.
@@ -1718,28 +1708,18 @@ static void GenerateWriteBarrierStubHelper(Assembler* assembler,
   __ PushList((1 << R2) | (1 << R3) | (1 << R4));  // Spill.
 
   Label marking_retry, lost_race, marking_overflow;
-  if (TargetCPUFeatures::arm_version() == ARMv5TE) {
-// TODO(21263): Implement 'swp' and use it below.
-#if !defined(USING_SIMULATOR)
-    ASSERT(OS::NumberOfAvailableProcessors() <= 1);
-#endif
-    __ ldr(R2, FieldAddress(R0, target::Object::tags_offset()));
-    __ bic(R2, R2, Operand(1 << target::RawObject::kOldAndNotMarkedBit));
-    __ str(R2, FieldAddress(R0, target::Object::tags_offset()));
-  } else {
-    // Atomically clear kOldAndNotMarkedBit.
-    ASSERT(target::Object::tags_offset() == 0);
-    __ sub(R3, R0, Operand(kHeapObjectTag));
-    // R3: Untagged address of header word (ldrex/strex do not support offsets).
-    __ Bind(&marking_retry);
-    __ ldrex(R2, R3);
-    __ tst(R2, Operand(1 << target::RawObject::kOldAndNotMarkedBit));
-    __ b(&lost_race, ZERO);
-    __ bic(R2, R2, Operand(1 << target::RawObject::kOldAndNotMarkedBit));
-    __ strex(R4, R2, R3);
-    __ cmp(R4, Operand(1));
-    __ b(&marking_retry, EQ);
-  }
+  // Atomically clear kOldAndNotMarkedBit.
+  ASSERT(target::Object::tags_offset() == 0);
+  __ sub(R3, R0, Operand(kHeapObjectTag));
+  // R3: Untagged address of header word (ldrex/strex do not support offsets).
+  __ Bind(&marking_retry);
+  __ ldrex(R2, R3);
+  __ tst(R2, Operand(1 << target::RawObject::kOldAndNotMarkedBit));
+  __ b(&lost_race, ZERO);
+  __ bic(R2, R2, Operand(1 << target::RawObject::kOldAndNotMarkedBit));
+  __ strex(R4, R2, R3);
+  __ cmp(R4, Operand(1));
+  __ b(&marking_retry, EQ);
 
   __ ldr(R4, Address(THR, target::Thread::marking_stack_block_offset()));
   __ ldr(R2, Address(R4, target::MarkingStackBlock::top_offset()));
diff --git a/runtime/vm/cpu_arm.cc b/runtime/vm/cpu_arm.cc
index b07435e4f01..c3d91d498ea 100644
--- a/runtime/vm/cpu_arm.cc
+++ b/runtime/vm/cpu_arm.cc
@@ -25,7 +25,7 @@
 #endif
 
 // ARM version differences.
-// We support three major 32-bit ARM ISA versions: ARMv5TE, ARMv6 and variants,
+// We support two major 32-bit ARM ISA versions: ARMv6 and variants,
 // and ARMv7 and variants. For each of these we detect the presence of vfp,
 // neon, and integer division instructions. Considering ARMv5TE as the baseline,
 // later versions add the following features/instructions that we use:
@@ -42,7 +42,7 @@
 //
 // If an aarch64 CPU is detected, we generate ARMv7 code.
 //
-// If an instruction is missing on ARMv5TE or ARMv6, we emulate it, if possible.
+// If an instruction is missing on ARMv6, we emulate it, if possible.
 // Where we are missing vfp, we do not unbox doubles, or generate intrinsics for
 // floating point operations. Where we are missing neon, we do not unbox SIMD
 // values, or inline operations on SIMD values. Where we are missing integer
@@ -52,24 +52,13 @@
 //
 // Alignment:
 //
-// Before ARMv6, that is only for ARMv5TE, unaligned accesses will cause a
-// crash. This includes the ldrd and strd instructions, which must use addresses
-// that are 8-byte aligned. Since we don't always guarantee that for our uses
-// of ldrd and strd, these instructions are emulated with two load or store
-// instructions on ARMv5TE. On ARMv6 and on, we assume that the kernel is
-// set up to fixup unaligned accesses. This can be verified by checking
-// /proc/cpu/alignment on modern Linux systems.
+// On ARMv6 and on, we assume that the kernel is set up to fixup unaligned
+// accesses. This can be verified by checking /proc/cpu/alignment on modern
+// Linux systems.
 
 namespace dart {
 
-#if defined(TARGET_ARCH_ARM_5TE)
-DEFINE_FLAG(bool, use_vfp, false, "Use vfp instructions if supported");
-DEFINE_FLAG(bool, use_neon, false, "Use neon instructions if supported");
-DEFINE_FLAG(bool,
-            use_integer_division,
-            false,
-            "Use integer division instruction if supported");
-#elif defined(TARGET_ARCH_ARM_6)
+#if defined(TARGET_ARCH_ARM_6)
 DEFINE_FLAG(bool, use_vfp, true, "Use vfp instructions if supported");
 DEFINE_FLAG(bool, use_neon, false, "Use neon instructions if supported");
 DEFINE_FLAG(bool,
@@ -86,8 +75,7 @@ DEFINE_FLAG(bool,
 #endif
 
 #if defined(TARGET_HOST_MISMATCH)
-#if defined(TARGET_ARCH_ARM_5TE) || defined(TARGET_OS_ANDROID) \
-    || defined(TARGET_OS_IOS)
+#if defined(TARGET_OS_ANDROID) || defined(TARGET_OS_IOS)
 DEFINE_FLAG(bool, sim_use_hardfp, false, "Use the hardfp ABI.");
 #else
 DEFINE_FLAG(bool, sim_use_hardfp, true, "Use the hardfp ABI.");
@@ -170,7 +158,7 @@ void HostCPUFeatures::Init() {
   CpuInfo::Init();
   hardware_ = CpuInfo::GetCpuModel();
 
-  // Check for ARMv5TE, ARMv6, ARMv7, or aarch64.
+  // Check for ARMv6, ARMv7, or aarch64.
   // It can be in either the Processor or Model information fields.
   if (CpuInfo::FieldContains(kCpuInfoProcessor, "aarch64") ||
       CpuInfo::FieldContains(kCpuInfoModel, "aarch64") ||
@@ -179,28 +167,15 @@ void HostCPUFeatures::Init() {
     // pretend that this arm64 cpu is really an ARMv7
     arm_version_ = ARMv7;
     is_arm64 = true;
-  } else if (CpuInfo::FieldContains(kCpuInfoProcessor, "ARM926EJ-S") ||
-             CpuInfo::FieldContains(kCpuInfoModel, "ARM926EJ-S")) {
-    // Lego Mindstorm EV3.
-    arm_version_ = ARMv5TE;
-    // On ARMv5, the PC read offset in an STR or STM instruction is either 8 or
-    // 12 bytes depending on the implementation. On the Mindstorm EV3 it is 12
-    // bytes.
-    store_pc_read_offset_ = 12;
-  } else if (CpuInfo::FieldContains(kCpuInfoProcessor, "Feroceon 88FR131") ||
-             CpuInfo::FieldContains(kCpuInfoModel, "Feroceon 88FR131")) {
-    // This is for the DGBox. For the time-being, assume it is similar to the
-    // Lego Mindstorm.
-    arm_version_ = ARMv5TE;
-    store_pc_read_offset_ = 12;
   } else if (CpuInfo::FieldContains(kCpuInfoProcessor, "ARMv6") ||
              CpuInfo::FieldContains(kCpuInfoModel, "ARMv6")) {
     // Raspberry Pi, etc.
     arm_version_ = ARMv6;
-  } else {
-    ASSERT(CpuInfo::FieldContains(kCpuInfoProcessor, "ARMv7") ||
-           CpuInfo::FieldContains(kCpuInfoModel, "ARMv7"));
+  } else if (CpuInfo::FieldContains(kCpuInfoProcessor, "ARMv7") ||
+             CpuInfo::FieldContains(kCpuInfoModel, "ARMv7")) {
     arm_version_ = ARMv7;
+  } else {
+    FATAL("Unsupported ARM CPU architecture.");
   }
 
   // Has floating point unit.
@@ -273,9 +248,7 @@ void HostCPUFeatures::Init() {
   CpuInfo::Init();
   hardware_ = CpuInfo::GetCpuModel();
 
-#if defined(TARGET_ARCH_ARM_5TE)
-  arm_version_ = ARMv5TE;
-#elif defined(TARGET_ARCH_ARM_6)
+#if defined(TARGET_ARCH_ARM_6)
   arm_version_ = ARMv6;
 #else
   arm_version_ = ARMv7;
diff --git a/runtime/vm/cpu_arm.h b/runtime/vm/cpu_arm.h
index 6f5b77456ba..18d55fcad7c 100644
--- a/runtime/vm/cpu_arm.h
+++ b/runtime/vm/cpu_arm.h
@@ -23,7 +23,6 @@ namespace dart {
 // they may be altered for testing.
 
 enum ARMVersion {
-  ARMv5TE,
   ARMv6,
   ARMv7,
   ARMvUnknown,
diff --git a/runtime/vm/flag_list.h b/runtime/vm/flag_list.h
index d7b0a9f5efc..be99782de29 100644
--- a/runtime/vm/flag_list.h
+++ b/runtime/vm/flag_list.h
@@ -12,13 +12,6 @@
 #define USING_DBC false
 #endif
 
-// Don't use USING_MULTICORE outside of this file.
-#if defined(ARCH_IS_MULTI_CORE)
-#define USING_MULTICORE true
-#else
-#define USING_MULTICORE false
-#endif
-
 // Don't use USING_PRODUCT outside of this file.
 #if defined(PRODUCT)
 #define USING_PRODUCT true
@@ -61,7 +54,7 @@ constexpr bool kDartUseBytecode = false;
     "Abort if memory allocation fails - use only with --old-gen-heap-size")    \
   C(async_debugger, false, false, bool, true,                                  \
     "Debugger support async functions.")                                       \
-  P(background_compilation, bool, USING_MULTICORE,                             \
+  P(background_compilation, bool, true,                                        \
     "Run optimizing compilation in background")                                \
   P(causal_async_stacks, bool, !USING_PRODUCT, "Improved async stacks")        \
   P(collect_code, bool, false, "Attempt to GC infrequently used code.")        \
@@ -72,10 +65,8 @@ constexpr bool kDartUseBytecode = false;
   P(compilation_counter_threshold, int, 10,                                    \
     "Function's usage-counter value before interpreted function is compiled, " \
     "-1 means never")                                                          \
-  P(concurrent_mark, bool, USING_MULTICORE,                                    \
-    "Concurrent mark for old generation.")                                     \
-  P(concurrent_sweep, bool, USING_MULTICORE,                                   \
-    "Concurrent sweep for old generation.")                                    \
+  P(concurrent_mark, bool, true, "Concurrent mark for old generation.")        \
+  P(concurrent_sweep, bool, true, "Concurrent sweep for old generation.")      \
   R(dedup_instructions, true, bool, false,                                     \
     "Canonicalize instructions when precompiling.")                            \
   C(deoptimize_alot, false, false, bool, false,                                \
@@ -118,7 +109,7 @@ constexpr bool kDartUseBytecode = false;
   P(link_natives_lazily, bool, false, "Link native calls lazily")              \
   R(log_marker_tasks, false, bool, false,                                      \
     "Log debugging information for old gen GC marking tasks.")                 \
-  P(marker_tasks, int, USING_MULTICORE ? 2 : 0,                                \
+  P(marker_tasks, int, 2,                                                      \
     "The number of tasks to spawn during old gen GC marking (0 means "         \
     "perform all marking on main thread).")                                    \
   P(max_polymorphic_checks, int, 4,                                            \
diff --git a/runtime/vm/instructions_arm.cc b/runtime/vm/instructions_arm.cc
index c2be95ce2ac..2dab06936c6 100644
--- a/runtime/vm/instructions_arm.cc
+++ b/runtime/vm/instructions_arm.cc
@@ -121,7 +121,7 @@ uword InstructionPattern::DecodeLoadWordImmediate(uword end,
   int32_t instr = Instr::At(start)->InstructionBits();
   intptr_t imm = 0;
   const ARMVersion version = TargetCPUFeatures::arm_version();
-  if ((version == ARMv5TE) || (version == ARMv6)) {
+  if (version == ARMv6) {
     ASSERT((instr & 0xfff00000) == 0xe3800000);  // orr rd, rd, byte0
     imm |= (instr & 0x000000ff);
 
@@ -370,7 +370,7 @@ bool ReturnPattern::IsValid() const {
                         B21 | (0xfff << 8) | B4 |
                         (static_cast<int32_t>(LR) << kRmShift);
   const ARMVersion version = TargetCPUFeatures::arm_version();
-  if ((version == ARMv5TE) || (version == ARMv6)) {
+  if (version == ARMv6) {
     return bx_lr->InstructionBits() == instruction;
   } else {
     ASSERT(version == ARMv7);
diff --git a/runtime/vm/profiler.cc b/runtime/vm/profiler.cc
index 4a0181d7252..6034052fc90 100644
--- a/runtime/vm/profiler.cc
+++ b/runtime/vm/profiler.cc
@@ -32,7 +32,7 @@ static const intptr_t kMaxSamplesPerTick = 16;
 
 DEFINE_FLAG(bool, trace_profiled_isolates, false, "Trace profiled isolates.");
 
-#if defined(TARGET_ARCH_ARM_6) || defined(TARGET_ARCH_ARM_5TE)
+#if defined(TARGET_ARCH_ARM_6)
 DEFINE_FLAG(int,
             profile_period,
             10000,
diff --git a/runtime/vm/simulator_arm.cc b/runtime/vm/simulator_arm.cc
index dbc7eb2a97c..1c5db001486 100644
--- a/runtime/vm/simulator_arm.cc
+++ b/runtime/vm/simulator_arm.cc
@@ -1639,14 +1639,11 @@ DART_FORCE_INLINE void Simulator::DecodeType01(Instr* instr) {
           case 2:
             // Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
             // Format(instr, "umaal'cond's 'rd, 'rn, 'rm, 'rs");
-            if (TargetCPUFeatures::arm_version() == ARMv5TE) {
-              // umaal is only in ARMv6 and above.
-              UnimplementedInstruction(instr);
-            }
             FALL_THROUGH;
           case 5:
-          // Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
-          // Format(instr, "umlal'cond's 'rd, 'rn, 'rm, 'rs");
+            // Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
+            // Format(instr, "umlal'cond's 'rd, 'rn, 'rm, 'rs");
+            FALL_THROUGH;
           case 7: {
             // Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
             // Format(instr, "smlal'cond's 'rd, 'rn, 'rm, 'rs");
@@ -1694,10 +1691,6 @@ DART_FORCE_INLINE void Simulator::DecodeType01(Instr* instr) {
           }
         }
       } else {
-        if (TargetCPUFeatures::arm_version() == ARMv5TE) {
-          UnimplementedInstruction(instr);
-          return;
-        }
         // synchronization primitives
         Register rd = instr->RdField();
         Register rn = instr->RnField();
diff --git a/sdk/bin/dart b/sdk/bin/dart
index f50184bf44d..34cb80b8d7e 100755
--- a/sdk/bin/dart
+++ b/sdk/bin/dart
@@ -30,8 +30,7 @@ then
   DIRS=$( ls "$OUT_DIR" )
   # list of possible configurations in decreasing desirability
   CONFIGS=("ReleaseX64" "ReleaseIA32" "DebugX64" "DebugIA32"
-    "ReleaseARM"    "ReleaseARM64"    "ReleaseARMV5TE"
-    "DebugARM"      "DebugARM64"      "DebugARMV5TE")
+    "ReleaseARM" "ReleaseARM64" "DebugARM" "DebugARM64" )
   DART_CONFIGURATION="None"
   for CONFIG in ${CONFIGS[*]}
   do
diff --git a/sdk/bin/pub b/sdk/bin/pub
index 5dda6113ec7..85ad5d6b0eb 100755
--- a/sdk/bin/pub
+++ b/sdk/bin/pub
@@ -47,8 +47,7 @@ then
   DIRS=$( ls "$OUT_DIR" )
   # list of possible configurations in decreasing desirability
   CONFIGS=("ReleaseX64" "ReleaseIA32" "DebugX64" "DebugIA32"
-    "ReleaseARM"    "ReleaseARM64"    "ReleaseARMV5TE"
-    "DebugARM"      "DebugARM64"      "DebugARMV5TE")
+    "ReleaseARM" "ReleaseARM64" "DebugARM" "DebugARM64" )
   DART_CONFIGURATION="None"
   for CONFIG in ${CONFIGS[*]}
   do
diff --git a/sdk_nnbd/bin/dart b/sdk_nnbd/bin/dart
index f50184bf44d..34cb80b8d7e 100755
--- a/sdk_nnbd/bin/dart
+++ b/sdk_nnbd/bin/dart
@@ -30,8 +30,7 @@ then
   DIRS=$( ls "$OUT_DIR" )
   # list of possible configurations in decreasing desirability
   CONFIGS=("ReleaseX64" "ReleaseIA32" "DebugX64" "DebugIA32"
-    "ReleaseARM"    "ReleaseARM64"    "ReleaseARMV5TE"
-    "DebugARM"      "DebugARM64"      "DebugARMV5TE")
+    "ReleaseARM" "ReleaseARM64" "DebugARM" "DebugARM64" )
   DART_CONFIGURATION="None"
   for CONFIG in ${CONFIGS[*]}
   do
diff --git a/sdk_nnbd/bin/pub b/sdk_nnbd/bin/pub
index 5dda6113ec7..85ad5d6b0eb 100755
--- a/sdk_nnbd/bin/pub
+++ b/sdk_nnbd/bin/pub
@@ -47,8 +47,7 @@ then
   DIRS=$( ls "$OUT_DIR" )
   # list of possible configurations in decreasing desirability
   CONFIGS=("ReleaseX64" "ReleaseIA32" "DebugX64" "DebugIA32"
-    "ReleaseARM"    "ReleaseARM64"    "ReleaseARMV5TE"
-    "DebugARM"      "DebugARM64"      "DebugARMV5TE")
+    "ReleaseARM" "ReleaseARM64" "DebugARM" "DebugARM64" )
   DART_CONFIGURATION="None"
   for CONFIG in ${CONFIGS[*]}
   do
diff --git a/tests/corelib_2/corelib_2.status b/tests/corelib_2/corelib_2.status
index 2d8824e0221..ed4ecb1513d 100644
--- a/tests/corelib_2/corelib_2.status
+++ b/tests/corelib_2/corelib_2.status
@@ -8,10 +8,6 @@ regexp/lookbehind_test/01: Skip # Flaky in uncatchable way.  Issue 36280
 [ $mode == debug ]
 regexp/pcre_test: Slow # Issue 22008
 
-[ $arch == simarmv5te && ($runtime == dart_precompiled || $runtime == vm) ]
-int_parse_radix_test/*: Slow
-integer_parsed_mul_div_vm_test: Slow
-
 [ $arch == x64 && $system == windows ]
 stopwatch_test: Skip # Flaky test due to expected performance behaviour.
 
diff --git a/tests/lib_2/lib_2.status b/tests/lib_2/lib_2.status
index cde9329d0b3..6d06af785d7 100644
--- a/tests/lib_2/lib_2.status
+++ b/tests/lib_2/lib_2.status
@@ -7,9 +7,6 @@ wasm/*: Skip # dart:wasm is currently behind a Dart SDK build flag.
 [ $arch == simarm64 ]
 convert/utf85_test: Skip # Pass, Slow Issue 20111.
 
-[ $arch == simarmv5te ]
-mirrors/mirrors_reader_test: Slow
-
 [ $mode == product ]
 developer/timeline_test: Skip # Not supported
 isolate/issue_24243_parent_isolate_test: Skip # Requires checked mode
@@ -46,7 +43,7 @@ html/transition_event_test: Skip # Times out. Issue 22167
 [ $runtime != dart_precompiled && ($runtime != vm || $compiler != dartk && $compiler != none) ]
 isolate/vm_rehash_test: SkipByDesign
 
-[ $arch == simarm || $arch == simarmv5te || $arch == simarmv6 ]
+[ $arch == simarm || $arch == simarmv6 ]
 convert/utf85_test: Skip # Pass, Slow Issue 12644.
 
 [ $arch != x64 || $compiler == dartkb || $runtime != vm ]
diff --git a/tests/lib_2/lib_2_vm.status b/tests/lib_2/lib_2_vm.status
index 305c37144f7..aba92fff37f 100644
--- a/tests/lib_2/lib_2_vm.status
+++ b/tests/lib_2/lib_2_vm.status
@@ -11,7 +11,7 @@ mirrors/immutable_collections_test: Pass, Slow # http://dartbug.com/33057
 [ $arch == ia32 && $mode == debug && $runtime == vm && $system == windows ]
 convert/streamed_conversion_json_utf8_decode_test: Skip # Verification OOM.
 
-[ $arch != ia32 && $arch != simarm && $arch != simarmv5te && $arch != simarmv6 && $arch != x64 && $mode == debug && $runtime == vm ]
+[ $arch != ia32 && $arch != simarm && $arch != simarmv6 && $arch != x64 && $mode == debug && $runtime == vm ]
 convert/streamed_conversion_json_utf8_decode_test: Skip # Verification not yet implemented.
 
 [ $arch == simarm64 && $runtime == vm ]
@@ -79,8 +79,8 @@ mirrors/invocation_fuzz_test: Crash
 mirrors/library_uri_io_test: RuntimeError
 mirrors/library_uri_package_test: RuntimeError
 
-[ $runtime == vm && ($arch == simarm || $arch == simarmv5te || $arch == simarmv6) ]
+[ $runtime == vm && ($arch == simarm || $arch == simarmv6) ]
 convert/utf85_test: Skip # Pass, Slow Issue 12644.
 
-[ $arch == simarmv5te || $arch == simarmv6 || $arch == simarm && $runtime == vm ]
+[ $arch == simarmv6 || $arch == simarm && $runtime == vm ]
 convert/chunked_conversion_utf88_test: Skip # Pass, Slow Issue 12644.
diff --git a/third_party/pkg_tested/pkg_tested.status b/third_party/pkg_tested/pkg_tested.status
index b3d8b475ed0..47ab2541f4f 100644
--- a/third_party/pkg_tested/pkg_tested.status
+++ b/third_party/pkg_tested/pkg_tested.status
@@ -28,7 +28,7 @@ pub/*: SkipByDesign
 pub/test/run/app_can_read_from_stdin_test: Fail # Issue 19448
 pub/test/run/forwards_signal_posix_test: SkipByDesign
 
-[ $runtime == vm && ($arch == simarm || $arch == simarm64 || $arch == simarmv5te || $arch == simarmv6 || $builder_tag == asan || $mode == debug) ]
+[ $runtime == vm && ($arch == simarm || $arch == simarm64 || $arch == simarmv6 || $builder_tag == asan || $mode == debug) ]
 dart_style/test/command_line_test: Skip # The test controller does not take into account that tests take much longer in debug mode or on simulators.
 dart_style/test/formatter_test: Skip # The test controller does not take into account that tests take much longer in debug mode or on simulators.
 
diff --git a/tools/build.py b/tools/build.py
index 4ff1a1840ad..b862d5dd03e 100755
--- a/tools/build.py
+++ b/tools/build.py
@@ -17,9 +17,8 @@ HOST_CPUS = utils.GuessCpus()
 SCRIPT_DIR = os.path.dirname(sys.argv[0])
 DART_ROOT = os.path.realpath(os.path.join(SCRIPT_DIR, '..'))
 AVAILABLE_ARCHS = [
-    'ia32', 'x64', 'simarm', 'arm', 'arm_x64', 'simarmv6', 'armv6', 'simarmv5te',
-    'armv5te', 'simarm64', 'arm64', 'simdbc', 'simdbc64', 'armsimdbc',
-    'armsimdbc64', 'simarm_x64'
+    'ia32', 'x64', 'simarm', 'arm', 'arm_x64', 'simarmv6', 'armv6', 'simarm64',
+    'arm64', 'simdbc', 'simdbc64', 'armsimdbc', 'armsimdbc64', 'simarm_x64'
 ]
 
 usage = """\
@@ -117,7 +116,7 @@ def ProcessOptions(options, args):
                       % (os_name, HOST_OS))
                 return False
             if not arch in [
-                    'ia32', 'x64', 'arm', 'arm_x64', 'armv6', 'armv5te', 'arm64', 'simdbc',
+                    'ia32', 'x64', 'arm', 'arm_x64', 'armv6', 'arm64', 'simdbc',
                     'simdbc64'
             ]:
                 print(
diff --git a/tools/gardening/lib/src/results/configurations.dart b/tools/gardening/lib/src/results/configurations.dart
index 6bde17ad33c..999273f89f9 100644
--- a/tools/gardening/lib/src/results/configurations.dart
+++ b/tools/gardening/lib/src/results/configurations.dart
@@ -15,11 +15,9 @@ class Architecture {
   static const x64 = const Architecture._('x64');
   static const arm = const Architecture._('arm');
   static const armv6 = const Architecture._('armv6');
-  static const armv5te = const Architecture._('armv5te');
   static const arm64 = const Architecture._('arm64');
   static const simarm = const Architecture._('simarm');
   static const simarmv6 = const Architecture._('simarmv6');
-  static const simarmv5te = const Architecture._('simarmv5te');
   static const simarm64 = const Architecture._('simarm64');
   static const simdbc = const Architecture._('simdbc');
   static const simdbc64 = const Architecture._('simdbc64');
@@ -31,11 +29,9 @@ class Architecture {
     x64,
     arm,
     armv6,
-    armv5te,
     arm64,
     simarm,
     simarmv6,
-    simarmv5te,
     simarm64,
     simdbc,
     simdbc64
diff --git a/tools/gn.py b/tools/gn.py
index 158651cc4f8..e245561ce22 100755
--- a/tools/gn.py
+++ b/tools/gn.py
@@ -95,8 +95,8 @@ def ToCommandLine(gn_args):
 
 def HostCpuForArch(arch):
     if arch in [
-            'ia32', 'arm', 'armv6', 'armv5te', 'simarm', 'simarmv6',
-            'simarmv5te', 'simdbc', 'armsimdbc', 'simarm_x64'
+            'ia32', 'arm', 'armv6', 'simarm', 'simarmv6', 'simdbc', 'armsimdbc',
+            'simarm_x64'
     ]:
         return 'x86'
     if arch in [
@@ -107,7 +107,7 @@ def HostCpuForArch(arch):
 
 # The C compiler's target.
 def TargetCpuForArch(arch, target_os):
-    if arch in ['ia32', 'simarm', 'simarmv6', 'simarmv5te']:
+    if arch in ['ia32', 'simarm', 'simarmv6']:
         return 'x86'
     if arch in ['x64', 'simarm64', 'simarm_x64']:
         return 'x64'
@@ -134,8 +134,6 @@ def DartTargetCpuForArch(arch):
         return 'arm'
     if arch in ['armv6', 'simarmv6']:
         return 'armv6'
-    if arch in ['armv5te', 'simarmv5te']:
-        return 'armv5te'
     if arch in ['arm64', 'simarm64']:
         return 'arm64'
     if arch in ['simdbc', 'simdbc64', 'armsimdbc', 'armsimdbc64']:
@@ -233,8 +231,6 @@ def ToGnArgs(args, mode, arch, target_os, use_nnbd):
             gn_args['target_cpu'] = 'arm'
             gn_args['arm_version'] = 6
             gn_args['arm_float_abi'] = floatabi
-        elif gn_args['target_cpu'] == 'armv5te':
-            raise Exception("GN support for armv5te unimplemented")
 
     gn_args['is_debug'] = mode == 'debug'
     gn_args['is_release'] = mode == 'release'
@@ -329,8 +325,8 @@ def ProcessOptions(args):
             return False
     for arch in args.arch:
         archs = [
-            'ia32', 'x64', 'simarm', 'arm', 'arm_x64', 'simarmv6', 'armv6', 'simarmv5te',
-            'armv5te', 'simarm64', 'arm64', 'simdbc', 'simdbc64', 'armsimdbc',
+            'ia32', 'x64', 'simarm', 'arm', 'arm_x64', 'simarmv6', 'armv6',
+            'simarm64', 'arm64', 'simdbc', 'simdbc64', 'armsimdbc',
             'armsimdbc64', 'simarm_x64'
         ]
         if not arch in archs:
@@ -350,7 +346,7 @@ def ProcessOptions(args):
                       % (os_name, HOST_OS))
                 return False
             if not arch in [
-                    'ia32', 'x64', 'arm', 'arm_x64', 'armv6', 'armv5te', 'arm64', 'simdbc',
+                    'ia32', 'x64', 'arm', 'arm_x64', 'armv6', 'arm64', 'simdbc',
                     'simdbc64'
             ]:
                 print(
@@ -389,7 +385,7 @@ def parse_args(args):
         '-a',
         type=str,
         help='Target architectures (comma-separated).',
-        metavar='[all,ia32,x64,simarm,arm,arm_x64,simarmv6,armv6,simarmv5te,armv5te,'
+        metavar='[all,ia32,x64,simarm,arm,arm_x64,simarmv6,armv6,'
         'simarm64,arm64,simdbc,armsimdbc,simarm_x64]',
         default='x64')
     common_group.add_argument(
diff --git a/tools/utils.py b/tools/utils.py
index 085236ae93f..9cda434768b 100644
--- a/tools/utils.py
+++ b/tools/utils.py
@@ -79,9 +79,7 @@ def GuessOS():
 # Try to guess the host architecture.
 def GuessArchitecture():
     os_id = platform.machine()
-    if os_id.startswith('armv5te'):
-        return 'armv5te'
-    elif os_id.startswith('armv6'):
+    if os_id.startswith('armv6'):
         return 'armv6'
     elif os_id.startswith('arm'):
         return 'arm'
@@ -268,11 +266,9 @@ ARCH_FAMILY = {
     'x64': 'ia32',
     'arm': 'arm',
     'armv6': 'arm',
-    'armv5te': 'arm',
     'arm64': 'arm',
     'simarm': 'ia32',
     'simarmv6': 'ia32',
-    'simarmv5te': 'ia32',
     'simarm64': 'ia32',
     'simdbc': 'ia32',
     'simdbc64': 'ia32',