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[vm, ffi] Distinguish the Dart names for registers from their standard ABI names.
TEST=ci Change-Id: I7e3f5b407370aecba49049965071d7409c38177c Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/232481 Reviewed-by: Daco Harkes <dacoharkes@google.com> Commit-Queue: Ryan Macnak <rmacnak@google.com>
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@ -510,8 +510,8 @@ ASSEMBLER_TEST_RUN(Cmpb, test) {
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EXPECT_EQ(1, reinterpret_cast<CmpbCode>(test->entry())());
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EXPECT_DISASSEMBLY(
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"movl rax,1\n"
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"movl r11,0xffffff11\n"
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"push r11\n"
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"movl tmp,0xffffff11\n"
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"push tmp\n"
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"cmpb [rsp],0x11\n"
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"jz +7\n"
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"movl rax,0\n"
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@ -542,8 +542,8 @@ ASSEMBLER_TEST_RUN(Testb, test) {
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EXPECT_DISASSEMBLY(
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"movl rax,1\n"
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"movl rcx,0\n"
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"movl r11,0xffffff11\n"
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"push r11\n"
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"movl tmp,0xffffff11\n"
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"push tmp\n"
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"testb [rsp],0x10\n"
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"cmovzq rax,rcx\n"
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"testb [rsp],0x20\n"
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@ -951,8 +951,8 @@ ASSEMBLER_TEST_GENERATE(SignedMultiply64, assembler) {
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__ addq(RAX, R8);
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__ movq(R10, Immediate(2));
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__ movq(R11, Immediate(4));
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__ imulq(R10, R11);
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__ movq(TMP, Immediate(4));
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__ imulq(R10, TMP);
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__ addq(RAX, R10);
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__ movq(R15, Immediate(2));
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@ -977,8 +977,8 @@ ASSEMBLER_TEST_RUN(SignedMultiply64, test) {
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"pop r9\n"
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"addq rax,r8\n"
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"movl r10,2\n"
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"movl r11,4\n"
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"imulq r10,r11\n"
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"movl tmp,4\n"
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"imulq r10,tmp\n"
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"addq rax,r10\n"
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"movl pp,2\n"
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"imulq pp,pp,4\n"
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@ -1012,8 +1012,8 @@ ASSEMBLER_TEST_RUN(SignedMultiplyLong, test) {
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"movq rax,0x1234567887654321\n"
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"movq rcx,0x0db4da5f7ef412b1\n"
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"imulq rax,rcx\n"
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"movq r11,0x1234567887654321\n"
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"imulq rcx,r11\n"
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"movq tmp,0x1234567887654321\n"
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"imulq rcx,tmp\n"
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"cmpq rax,rcx\n"
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"jz +7\n"
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"int3\n"
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@ -1327,8 +1327,8 @@ ASSEMBLER_TEST_RUN(MoveExtend32Memory, test) {
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typedef intptr_t (*MoveExtend)();
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EXPECT_EQ(0x7ffffffe, reinterpret_cast<MoveExtend>(test->entry())());
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EXPECT_DISASSEMBLY(
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"movl r11,0xffffffff\n"
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"push r11\n"
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"movl tmp,0xffffffff\n"
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"push tmp\n"
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"push 0x7fffffff\n"
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"movsxdq rdx,[rsp+0x8]\n"
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"movsxdq rax,[rsp]\n"
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@ -1770,10 +1770,10 @@ ASSEMBLER_TEST_RUN(AddAddress, test) {
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"addq r10,[rsp+0x10]\n"
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"movq rax,[rsp+0x8]\n"
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"adcq rax,[rsp+0x18]\n"
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"pop r11\n"
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"pop r11\n"
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"pop r11\n"
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"pop r11\n"
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"pop tmp\n"
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"pop tmp\n"
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"pop tmp\n"
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"pop tmp\n"
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"ret\n");
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}
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@ -1866,10 +1866,10 @@ ASSEMBLER_TEST_RUN(SubAddress, test) {
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"subq r10,[rsp+0x10]\n"
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"movq rax,[rsp+0x8]\n"
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"sbbq rax,[rsp+0x18]\n"
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"pop r11\n"
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"pop r11\n"
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"pop r11\n"
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"pop r11\n"
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"pop tmp\n"
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"pop tmp\n"
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"pop tmp\n"
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"pop tmp\n"
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"ret\n");
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}
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@ -2391,8 +2391,8 @@ ASSEMBLER_TEST_RUN(LogicalOps, test) {
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"movl rcx,2\n"
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"shlq rdx,cl\n"
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"shldq rdx,r8,2\n"
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"movq r11,0xf000000000000003\n"
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"cmpq rdx,r11\n"
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"movq tmp,0xf000000000000003\n"
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"cmpq rdx,tmp\n"
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"jz +7\n"
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"int3\n"
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"movq rdx,0xff00000000000000\n"
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@ -2400,8 +2400,8 @@ ASSEMBLER_TEST_RUN(LogicalOps, test) {
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"movl rcx,2\n"
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"shlq rdx,cl\n"
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"shldq rdx,r8,cl\n"
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"movq r11,0xf000000000000003\n"
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"cmpq rdx,r11\n"
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"movq tmp,0xf000000000000003\n"
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"cmpq rdx,tmp\n"
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"jz +7\n"
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"int3\n"
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"movq rdx,0xff00000000000000\n"
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@ -2409,8 +2409,8 @@ ASSEMBLER_TEST_RUN(LogicalOps, test) {
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"movl rcx,2\n"
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"shrq rdx,cl\n"
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"shrdq rdx,r8,cl\n"
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"movq r11,0xcff0000000000000\n"
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"cmpq rdx,r11\n"
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"movq tmp,0xcff0000000000000\n"
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"cmpq rdx,tmp\n"
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"jz +7\n"
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"int3\n"
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"movl rax,0\n"
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@ -2697,31 +2697,31 @@ ASSEMBLER_TEST_RUN(LogicalOps64, test) {
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"movl rax,1\n"
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"shlq rax,63\n"
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"sarq rax,3\n"
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"movq r11,0xf000000000000000\n"
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"cmpq rax,r11\n"
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"movq tmp,0xf000000000000000\n"
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"cmpq rax,tmp\n"
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"jz +7\n"
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"int3\n"
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"movl rax,1\n"
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"movl rcx,3\n"
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"shlq rax,63\n"
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"sarq rax,cl\n"
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"movq r11,0xf000000000000000\n"
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"cmpq rax,r11\n"
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"movq tmp,0xf000000000000000\n"
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"cmpq rax,tmp\n"
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"jz +7\n"
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"int3\n"
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"push pp\n"
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"movq pp,0xf000000000000001\n"
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"andq pp,-1\n"
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"movq r11,0x8000000000000001\n"
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"andq pp,r11\n"
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"movq tmp,0x8000000000000001\n"
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"andq pp,tmp\n"
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"orq pp,2\n"
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"movq r11,0xf800000000000000\n"
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"orq pp,r11\n"
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"movq tmp,0xf800000000000000\n"
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"orq pp,tmp\n"
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"xorq pp,1\n"
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"movq r11,0x0800000000000000\n"
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"xorq pp,r11\n"
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"movq r11,0xf000000000000002\n"
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"cmpq pp,r11\n"
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"movq tmp,0x0800000000000000\n"
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"xorq pp,tmp\n"
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"movq tmp,0xf000000000000002\n"
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"cmpq pp,tmp\n"
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"jz +7\n"
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"int3\n"
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"andl pp,2\n"
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@ -3080,7 +3080,7 @@ ASSEMBLER_TEST_RUN(CallSimpleLeaf, test) {
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typedef int (*CallSimpleLeafCode)();
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EXPECT_EQ(42 + 87, reinterpret_cast<CallSimpleLeafCode>(test->entry())());
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EXPECT_DISASSEMBLY_ENDS_WITH(
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"call r11\n"
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"call tmp\n"
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"addq rsp,8\n"
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"ret\n");
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}
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@ -3100,7 +3100,7 @@ ASSEMBLER_TEST_GENERATE(JumpSimpleLeaf, assembler) {
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ASSEMBLER_TEST_RUN(JumpSimpleLeaf, test) {
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typedef int (*JumpSimpleLeafCode)();
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EXPECT_EQ(42, reinterpret_cast<JumpSimpleLeafCode>(test->entry())());
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EXPECT_DISASSEMBLY_ENDS_WITH("jmp r11\n");
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EXPECT_DISASSEMBLY_ENDS_WITH("jmp tmp\n");
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}
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ASSEMBLER_TEST_GENERATE(JumpIndirect, assembler) {
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@ -3185,7 +3185,7 @@ ASSEMBLER_TEST_RUN(SingleFPMoves, test) {
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"movss r8,xmm7\n"
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"movss r9,xmm8\n"
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"movss r10,xmm9\n"
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"movss r11,xmm10\n"
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"movss tmp,xmm10\n"
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"movss r12,xmm11\n"
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"movss r13,xmm12\n"
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"movss thr,xmm13\n"
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@ -3209,7 +3209,7 @@ ASSEMBLER_TEST_RUN(SingleFPMoves, test) {
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"movss thr,xmm15\n"
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"movss r13,xmm14\n"
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"movss r12,xmm13\n"
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"movss r11,xmm12\n"
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"movss tmp,xmm12\n"
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"movss r10,xmm11\n"
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"movss r9,xmm10\n"
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"movss r8,xmm9\n"
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@ -3384,8 +3384,8 @@ ASSEMBLER_TEST_RUN(PackedDoubleNegate, test) {
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EXPECT_FLOAT_EQ(-1.0, res, 0.000001f);
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EXPECT_DISASSEMBLY_NOT_WINDOWS_ENDS_WITH(
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"movups xmm10,[rax]\n"
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"movq r11,[thr+0x...]\n"
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"xorpd xmm10,[r11]\n"
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"movq tmp,[thr+0x...]\n"
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"xorpd xmm10,[tmp]\n"
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"movaps xmm0,xmm10\n"
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"pop thr\n"
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"pop pp\n"
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@ -3413,8 +3413,8 @@ ASSEMBLER_TEST_RUN(PackedDoubleAbsolute, test) {
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EXPECT_FLOAT_EQ(1.0, res, 0.000001f);
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EXPECT_DISASSEMBLY_NOT_WINDOWS_ENDS_WITH(
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"movups xmm10,[rax]\n"
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"movq r11,[thr+0x...]\n"
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"movups xmm0,[r11]\n"
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"movq tmp,[thr+0x...]\n"
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"movups xmm0,[tmp]\n"
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"andpd xmm0,xmm10\n"
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"pop thr\n"
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"pop pp\n"
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@ -4066,8 +4066,8 @@ ASSEMBLER_TEST_RUN(PackedNegate, test) {
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"movl rax,0x4144cccd\n"
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"movd xmm0,rax\n"
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"shufps xmm0,xmm0 [0]\n"
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"movq r11,[thr+0x...]\n"
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"xorps xmm0,[r11]\n"
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"movq tmp,[thr+0x...]\n"
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"xorps xmm0,[tmp]\n"
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"shufps xmm0,xmm0 [aa]\n"
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"pop thr\n"
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"pop pp\n"
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@ -4103,8 +4103,8 @@ ASSEMBLER_TEST_RUN(PackedAbsolute, test) {
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"movl rax,-0x3e8b3333\n"
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"movd xmm0,rax\n"
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"shufps xmm0,xmm0 [0]\n"
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"movq r11,[thr+0x...]\n"
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"andps xmm0,[r11]\n"
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"movq tmp,[thr+0x...]\n"
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"andps xmm0,[tmp]\n"
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"shufps xmm0,xmm0 [aa]\n"
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"pop thr\n"
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"pop pp\n"
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@ -4138,8 +4138,8 @@ ASSEMBLER_TEST_RUN(PackedSetWZero, test) {
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"movl rax,0x4144cccd\n"
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"movd xmm0,rax\n"
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"shufps xmm0,xmm0 [0]\n"
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"movq r11,[thr+0x...]\n"
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"andps xmm0,[r11]\n"
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"movq tmp,[thr+0x...]\n"
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"andps xmm0,[tmp]\n"
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"shufps xmm0,xmm0 [ff]\n"
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"pop thr\n"
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"pop pp\n"
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@ -4288,8 +4288,8 @@ ASSEMBLER_TEST_RUN(PackedLogicalNot, test) {
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EXPECT_EQ(static_cast<uword>(0x0), res);
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EXPECT_DISASSEMBLY_NOT_WINDOWS_ENDS_WITH(
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"movups xmm9,[rax]\n"
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"movq r11,[thr+0x...]\n"
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"movups xmm0,[r11]\n"
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"movq tmp,[thr+0x...]\n"
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"movups xmm0,[tmp]\n"
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"xorps xmm0,xmm9\n"
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"push rax\n"
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"movss [rsp],xmm0\n"
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@ -4756,10 +4756,10 @@ ASSEMBLER_TEST_RUN(Int32ToDoubleConversion, test) {
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double res = reinterpret_cast<Int32ToDoubleConversion>(test->entry())();
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EXPECT_FLOAT_EQ(-2.0, res, 0.001);
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EXPECT_DISASSEMBLY(
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"movq r11,0x1111111100000006\n"
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"cvtsi2sd xmm0,r11\n"
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"movq r11,0x2222222200000008\n"
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"cvtsi2sd xmm8,r11\n"
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"movq tmp,0x1111111100000006\n"
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"cvtsi2sd xmm0,tmp\n"
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"movq tmp,0x2222222200000008\n"
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"cvtsi2sd xmm8,tmp\n"
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"subsd xmm0,xmm8\n"
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"ret\n");
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}
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@ -4823,8 +4823,8 @@ ASSEMBLER_TEST_RUN(DoubleToInt64Conversion, test) {
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"movsd xmm9,[rsp]\n"
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"pop rax\n"
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"cvttsd2siq rax,xmm9\n"
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"movq r11,0x8000000000000000\n"
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"cmpq rax,r11\n"
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"movq tmp,0x8000000000000000\n"
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"cmpq rax,tmp\n"
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"jz +7\n"
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"int3\n"
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"movq rax,0x4258727cda000000\n"
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@ -4904,8 +4904,8 @@ ASSEMBLER_TEST_RUN(DoubleToInt32Conversion, test) {
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"movsd xmm9,[rsp]\n"
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"pop rax\n"
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"cvttsd2sil rax,xmm9\n"
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"movl r11,0x80000000\n"
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"cmpq rax,r11\n"
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"movl tmp,0x80000000\n"
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"cmpq rax,tmp\n"
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"jz +7\n"
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"int3\n"
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"movq rax,0xc045000000000000\n"
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@ -4914,8 +4914,8 @@ ASSEMBLER_TEST_RUN(DoubleToInt32Conversion, test) {
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"pop rax\n"
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"movq r10,-1\n"
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"cvttsd2sil r10,xmm9\n"
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"movl r11,0xffffffd6\n"
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"cmpq r10,r11\n"
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"movl tmp,0xffffffd6\n"
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"cmpq r10,tmp\n"
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"jz +7\n"
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"int3\n"
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"movq rax,0x4045000000000000\n"
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@ -4991,8 +4991,8 @@ ASSEMBLER_TEST_RUN(TestObjectCompare, test) {
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"cmpq rcx,0x1e\n"
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"jnz +63\n"
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"push rax\n"
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"movq r11,[pp+0xf]\n"
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"movq [rsp],r11\n"
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"movq tmp,[pp+0xf]\n"
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"movq [rsp],tmp\n"
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"pop rcx\n"
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"cmpq rcx,[pp+0xf]\n"
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"jnz +43\n"
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@ -5035,8 +5035,8 @@ ASSEMBLER_TEST_RUN(TestObjectCompare, test) {
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"cmpl rcx,0x1e\n"
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"jnz +62\n"
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"push rax\n"
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"movq r11,[pp+0xf]\n"
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"movq [rsp],r11\n"
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"movq tmp,[pp+0xf]\n"
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"movq [rsp],tmp\n"
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"pop rcx\n"
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"cmpl rcx,[pp+0xf]\n"
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"jnz +42\n"
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@ -5464,8 +5464,8 @@ ASSEMBLER_TEST_RUN(DoubleAbs, test) {
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"movq r12,[rdi+0x8]\n"
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"movq thr,rsi\n"
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"movq pp,[r12+0x27]\n"
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"movq r11,[thr+0x...]\n"
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"andpd xmm0,[r11]\n"
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"movq tmp,[thr+0x...]\n"
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"andpd xmm0,[tmp]\n"
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"pop thr\n"
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"pop pp\n"
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"pop r12\n"
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@ -5832,8 +5832,8 @@ ASSEMBLER_TEST_RUN(BitTestTest, test) {
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EXPECT_EQ(1, reinterpret_cast<BitTest>(test->entry())());
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EXPECT_DISASSEMBLY(
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"movl rax,4\n"
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"movl r11,2\n"
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"btq rax,r11\n"
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"movl tmp,2\n"
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"btq rax,tmp\n"
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"jc +7\n"
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"int3\n"
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"movl rax,1\n"
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@ -5855,8 +5855,8 @@ ASSEMBLER_TEST_RUN(BitTestImmediate, test) {
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typedef int (*BitTestImmediate)();
|
||||
EXPECT_EQ(1, reinterpret_cast<BitTestImmediate>(test->entry())());
|
||||
EXPECT_DISASSEMBLY(
|
||||
"movl r11,0x20\n"
|
||||
"bt r11,5\n"
|
||||
"movl tmp,0x20\n"
|
||||
"bt tmp,5\n"
|
||||
"jc +7\n"
|
||||
"int3\n"
|
||||
"movl rax,1\n"
|
||||
|
@ -6007,44 +6007,44 @@ ASSEMBLER_TEST_RUN(ImmediateMacros, test) {
|
|||
EXPECT_DISASSEMBLY(
|
||||
"movl rax,0x2a\n"
|
||||
"imulq rax,rax,0x3b9aca00\n"
|
||||
"movq r11,0x00000009c7652400\n"
|
||||
"cmpq rax,r11\n"
|
||||
"movq tmp,0x00000009c7652400\n"
|
||||
"cmpq rax,tmp\n"
|
||||
"jz +7\n"
|
||||
"int3\n"
|
||||
"movl rax,0x2a\n"
|
||||
"imull rax,rax,0x3b9aca00\n"
|
||||
"movl r11,0xc7652400\n"
|
||||
"cmpq rax,r11\n"
|
||||
"movl tmp,0xc7652400\n"
|
||||
"cmpq rax,tmp\n"
|
||||
"jz +7\n"
|
||||
"int3\n"
|
||||
"movl rax,0x3b9aca00\n"
|
||||
"movq r11,0x000000098bca5a00\n"
|
||||
"addq rax,r11\n"
|
||||
"movq r11,0x00000009c7652400\n"
|
||||
"cmpq rax,r11\n"
|
||||
"movq tmp,0x000000098bca5a00\n"
|
||||
"addq rax,tmp\n"
|
||||
"movq tmp,0x00000009c7652400\n"
|
||||
"cmpq rax,tmp\n"
|
||||
"jz +7\n"
|
||||
"int3\n"
|
||||
"movl rax,0x3b9aca00\n"
|
||||
"addl rax,0x3b9aca00\n"
|
||||
"addl rax,0x3b9aca00\n"
|
||||
"addl rax,0x3b9aca00\n"
|
||||
"movl r11,0xee6b2800\n"
|
||||
"cmpq rax,r11\n"
|
||||
"movl tmp,0xee6b2800\n"
|
||||
"cmpq rax,tmp\n"
|
||||
"jz +7\n"
|
||||
"int3\n"
|
||||
"movl rax,0x3b9aca00\n"
|
||||
"subl rax,0x4d2fa200\n"
|
||||
"addl rax,0x3b9aca00\n"
|
||||
"subl rax,0x3b9aca00\n"
|
||||
"movl r11,0xee6b2800\n"
|
||||
"cmpq rax,r11\n"
|
||||
"movl tmp,0xee6b2800\n"
|
||||
"cmpq rax,tmp\n"
|
||||
"jz +7\n"
|
||||
"int3\n"
|
||||
"movl rax,0x3b9aca00\n"
|
||||
"movq r11,0x0000000a02ffee00\n"
|
||||
"subq rax,r11\n"
|
||||
"movq r11,0xfffffff6389adc00\n"
|
||||
"cmpq rax,r11\n"
|
||||
"movq tmp,0x0000000a02ffee00\n"
|
||||
"subq rax,tmp\n"
|
||||
"movq tmp,0xfffffff6389adc00\n"
|
||||
"cmpq rax,tmp\n"
|
||||
"jz +7\n"
|
||||
"int3\n"
|
||||
"movq rax,-0x3b9aca00\n"
|
||||
|
@ -6058,8 +6058,8 @@ ASSEMBLER_TEST_RUN(ImmediateMacros, test) {
|
|||
"subl rax,0x4d2fa200\n"
|
||||
"subl rax,0x3b9aca00\n"
|
||||
"addl rax,0x3b9aca00\n"
|
||||
"movl r11,0xee6b2800\n"
|
||||
"cmpq rax,r11\n"
|
||||
"movl tmp,0xee6b2800\n"
|
||||
"cmpq rax,tmp\n"
|
||||
"jz +7\n"
|
||||
"int3\n"
|
||||
"movl rax,0x2a\n"
|
||||
|
|
|
@ -277,14 +277,14 @@ void NativeLocation::PrintTo(BaseTextBuffer* f) const {
|
|||
|
||||
void NativeRegistersLocation::PrintTo(BaseTextBuffer* f) const {
|
||||
if (num_regs() == 1) {
|
||||
f->Printf("%s", RegisterNames::RegisterName(regs_->At(0)));
|
||||
f->Printf("%s", RegisterNames::RegisterAbiName(regs_->At(0)));
|
||||
} else {
|
||||
f->AddString("(");
|
||||
for (intptr_t i = 0; i < num_regs(); i++) {
|
||||
if (i != 0) {
|
||||
f->Printf(", ");
|
||||
}
|
||||
f->Printf("%s", RegisterNames::RegisterName(regs_->At(i)));
|
||||
f->Printf("%s", RegisterNames::RegisterAbiName(regs_->At(i)));
|
||||
}
|
||||
f->AddString(")");
|
||||
}
|
||||
|
|
|
@ -7,8 +7,8 @@ fa5 double
|
|||
fa6 double
|
||||
fa7 double
|
||||
(a0, a1) int64[double]
|
||||
(a2, tmp) int64[double]
|
||||
(tmp2, pp) int64[double]
|
||||
(a2, a3) int64[double]
|
||||
(a4, a5) int64[double]
|
||||
(a6, a7) int64[double]
|
||||
S+0 double
|
||||
S+8 double
|
||||
|
|
|
@ -9,9 +9,9 @@ fa7 double
|
|||
a0 int64[double]
|
||||
a1 int64[double]
|
||||
a2 int64[double]
|
||||
tmp int64[double]
|
||||
tmp2 int64[double]
|
||||
pp int64[double]
|
||||
a3 int64[double]
|
||||
a4 int64[double]
|
||||
a5 int64[double]
|
||||
a6 int64[double]
|
||||
a7 int64[double]
|
||||
S+0 double
|
||||
|
|
|
@ -7,8 +7,8 @@ fa5 float
|
|||
fa6 float
|
||||
fa7 float
|
||||
(a0, a1) int64[float]
|
||||
(a2, tmp) int64[float]
|
||||
(tmp2, pp) int64[float]
|
||||
(a2, a3) int64[float]
|
||||
(a4, a5) int64[float]
|
||||
(a6, a7) int64[float]
|
||||
S+0 float
|
||||
S+4 float
|
||||
|
|
|
@ -9,9 +9,9 @@ fa7 float
|
|||
a0 int64[float]
|
||||
a1 int64[float]
|
||||
a2 int64[float]
|
||||
tmp int64[float]
|
||||
tmp2 int64[float]
|
||||
pp int64[float]
|
||||
a3 int64[float]
|
||||
a4 int64[float]
|
||||
a5 int64[float]
|
||||
a6 int64[float]
|
||||
a7 int64[float]
|
||||
S+0 float
|
||||
|
|
|
@ -1,9 +1,9 @@
|
|||
a0 int32[int8]
|
||||
a1 int32[int8]
|
||||
a2 int32[int8]
|
||||
tmp int32[int8]
|
||||
tmp2 int32[int8]
|
||||
pp int32[int8]
|
||||
a3 int32[int8]
|
||||
a4 int32[int8]
|
||||
a5 int32[int8]
|
||||
a6 int32[int8]
|
||||
a7 int32[int8]
|
||||
S+0 int8
|
||||
|
|
|
@ -1,9 +1,9 @@
|
|||
a0 int32[int8]
|
||||
a1 int32[int8]
|
||||
a2 int32[int8]
|
||||
tmp int32[int8]
|
||||
tmp2 int32[int8]
|
||||
pp int32[int8]
|
||||
a3 int32[int8]
|
||||
a4 int32[int8]
|
||||
a5 int32[int8]
|
||||
a6 int32[int8]
|
||||
a7 int32[int8]
|
||||
S+0 int8
|
||||
|
|
|
@ -1,8 +1,8 @@
|
|||
P(a0 uint32) Struct(size: 12)
|
||||
P(a1 uint32) Struct(size: 12)
|
||||
P(a2 uint32) Struct(size: 12)
|
||||
P(tmp uint32) Struct(size: 12)
|
||||
P(tmp2 uint32) Struct(size: 12)
|
||||
P(pp uint32) Struct(size: 12)
|
||||
P(a3 uint32) Struct(size: 12)
|
||||
P(a4 uint32) Struct(size: 12)
|
||||
P(a5 uint32) Struct(size: 12)
|
||||
=>
|
||||
(a0, a1) int64
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
M(a0 int64, a1 int64) Struct(size: 12)
|
||||
M(a2 int64, tmp int64) Struct(size: 12)
|
||||
M(tmp2 int64, pp int64) Struct(size: 12)
|
||||
M(a2 int64, a3 int64) Struct(size: 12)
|
||||
M(a4 int64, a5 int64) Struct(size: 12)
|
||||
M(a6 int64, a7 int64) Struct(size: 12)
|
||||
M(S+0 int64, S+8 int64) Struct(size: 12)
|
||||
M(S+16 int64, S+24 int64) Struct(size: 12)
|
||||
|
|
|
@ -1,9 +1,9 @@
|
|||
P(a1 uint32) Struct(size: 16)
|
||||
fa0 float
|
||||
P(a2 uint32) Struct(size: 16)
|
||||
P(tmp uint32) Struct(size: 16)
|
||||
P(tmp2 uint32) Struct(size: 16)
|
||||
P(pp uint32) Struct(size: 16)
|
||||
P(a3 uint32) Struct(size: 16)
|
||||
P(a4 uint32) Struct(size: 16)
|
||||
P(a5 uint32) Struct(size: 16)
|
||||
P(a6 uint32) Struct(size: 16)
|
||||
P(a7 uint32) Struct(size: 16)
|
||||
P(S+0 uint32) Struct(size: 16)
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
M(a0 int64, a1 int64) Struct(size: 16)
|
||||
fa0 float
|
||||
M(a2 int64, tmp int64) Struct(size: 16)
|
||||
M(tmp2 int64, pp int64) Struct(size: 16)
|
||||
M(a2 int64, a3 int64) Struct(size: 16)
|
||||
M(a4 int64, a5 int64) Struct(size: 16)
|
||||
M(a6 int64, a7 int64) Struct(size: 16)
|
||||
M(S+0 int64, S+8 int64) Struct(size: 16)
|
||||
M(S+16 int64, S+24 int64) Struct(size: 16)
|
||||
|
|
|
@ -1,9 +1,9 @@
|
|||
M(a0 uint32) Struct(size: 3)
|
||||
M(a1 uint32) Struct(size: 3)
|
||||
M(a2 uint32) Struct(size: 3)
|
||||
M(tmp uint32) Struct(size: 3)
|
||||
M(tmp2 uint32) Struct(size: 3)
|
||||
M(pp uint32) Struct(size: 3)
|
||||
M(a3 uint32) Struct(size: 3)
|
||||
M(a4 uint32) Struct(size: 3)
|
||||
M(a5 uint32) Struct(size: 3)
|
||||
M(a6 uint32) Struct(size: 3)
|
||||
M(a7 uint32) Struct(size: 3)
|
||||
M(S+0 uint32) Struct(size: 3)
|
||||
|
|
|
@ -1,9 +1,9 @@
|
|||
M(a0 int64) Struct(size: 3)
|
||||
M(a1 int64) Struct(size: 3)
|
||||
M(a2 int64) Struct(size: 3)
|
||||
M(tmp int64) Struct(size: 3)
|
||||
M(tmp2 int64) Struct(size: 3)
|
||||
M(pp int64) Struct(size: 3)
|
||||
M(a3 int64) Struct(size: 3)
|
||||
M(a4 int64) Struct(size: 3)
|
||||
M(a5 int64) Struct(size: 3)
|
||||
M(a6 int64) Struct(size: 3)
|
||||
M(a7 int64) Struct(size: 3)
|
||||
M(S+0 int64) Struct(size: 3)
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
M(a0 uint32, a1 uint32) Struct(size: 8)
|
||||
M(a2 uint32, tmp uint32) Struct(size: 8)
|
||||
M(tmp2 uint32, pp uint32) Struct(size: 8)
|
||||
M(a2 uint32, a3 uint32) Struct(size: 8)
|
||||
M(a4 uint32, a5 uint32) Struct(size: 8)
|
||||
M(a6 uint32, a7 uint32) Struct(size: 8)
|
||||
M(S+0 uint32, S+4 uint32) Struct(size: 8)
|
||||
M(S+8 uint32, S+12 uint32) Struct(size: 8)
|
||||
|
|
|
@ -1,9 +1,9 @@
|
|||
M(a0 int64) Struct(size: 8)
|
||||
M(a1 int64) Struct(size: 8)
|
||||
M(a2 int64) Struct(size: 8)
|
||||
M(tmp int64) Struct(size: 8)
|
||||
M(tmp2 int64) Struct(size: 8)
|
||||
M(pp int64) Struct(size: 8)
|
||||
M(a3 int64) Struct(size: 8)
|
||||
M(a4 int64) Struct(size: 8)
|
||||
M(a5 int64) Struct(size: 8)
|
||||
M(a6 int64) Struct(size: 8)
|
||||
M(a7 int64) Struct(size: 8)
|
||||
M(S+0 int64) Struct(size: 8)
|
||||
|
|
|
@ -1,9 +1,9 @@
|
|||
M(a0 int32[int8], fa0 double) Struct(size: 9)
|
||||
M(a1 int32[int8], fa1 double) Struct(size: 9)
|
||||
M(a2 int32[int8], fa2 double) Struct(size: 9)
|
||||
M(tmp int32[int8], fa3 double) Struct(size: 9)
|
||||
M(tmp2 int32[int8], fa4 double) Struct(size: 9)
|
||||
M(pp int32[int8], fa5 double) Struct(size: 9)
|
||||
M(a3 int32[int8], fa3 double) Struct(size: 9)
|
||||
M(a4 int32[int8], fa4 double) Struct(size: 9)
|
||||
M(a5 int32[int8], fa5 double) Struct(size: 9)
|
||||
M(a6 int32[int8], fa6 double) Struct(size: 9)
|
||||
M(a7 int32[int8], fa7 double) Struct(size: 9)
|
||||
P(S+0 uint32) Struct(size: 9)
|
||||
|
|
|
@ -1,9 +1,9 @@
|
|||
M(a0 int32[int8], fa0 double) Struct(size: 9)
|
||||
M(a1 int32[int8], fa1 double) Struct(size: 9)
|
||||
M(a2 int32[int8], fa2 double) Struct(size: 9)
|
||||
M(tmp int32[int8], fa3 double) Struct(size: 9)
|
||||
M(tmp2 int32[int8], fa4 double) Struct(size: 9)
|
||||
M(pp int32[int8], fa5 double) Struct(size: 9)
|
||||
M(a3 int32[int8], fa3 double) Struct(size: 9)
|
||||
M(a4 int32[int8], fa4 double) Struct(size: 9)
|
||||
M(a5 int32[int8], fa5 double) Struct(size: 9)
|
||||
M(a6 int32[int8], fa6 double) Struct(size: 9)
|
||||
M(a7 int32[int8], fa7 double) Struct(size: 9)
|
||||
M(S+0 int64, S+8 int64) Struct(size: 9)
|
||||
|
|
|
@ -1,8 +1,8 @@
|
|||
P(a1 uint32) Union(size: 16)
|
||||
P(a2 uint32) Union(size: 16)
|
||||
P(tmp uint32) Union(size: 16)
|
||||
P(tmp2 uint32) Union(size: 16)
|
||||
P(pp uint32) Union(size: 16)
|
||||
P(a3 uint32) Union(size: 16)
|
||||
P(a4 uint32) Union(size: 16)
|
||||
P(a5 uint32) Union(size: 16)
|
||||
P(a6 uint32) Union(size: 16)
|
||||
P(a7 uint32) Union(size: 16)
|
||||
P(S+0 uint32) Union(size: 16)
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
M(a0 int64, a1 int64) Union(size: 16)
|
||||
M(a2 int64, tmp int64) Union(size: 16)
|
||||
M(tmp2 int64, pp int64) Union(size: 16)
|
||||
M(a2 int64, a3 int64) Union(size: 16)
|
||||
M(a4 int64, a5 int64) Union(size: 16)
|
||||
M(a6 int64, a7 int64) Union(size: 16)
|
||||
M(S+0 int64, S+8 int64) Union(size: 16)
|
||||
M(S+16 int64, S+24 int64) Union(size: 16)
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
M(a0 uint32, a1 uint32) Union(size: 5)
|
||||
M(a2 uint32, tmp uint32) Union(size: 5)
|
||||
M(tmp2 uint32, pp uint32) Union(size: 5)
|
||||
M(a2 uint32, a3 uint32) Union(size: 5)
|
||||
M(a4 uint32, a5 uint32) Union(size: 5)
|
||||
M(a6 uint32, a7 uint32) Union(size: 5)
|
||||
M(S+0 uint32, S+4 uint32) Union(size: 5)
|
||||
M(S+8 uint32, S+12 uint32) Union(size: 5)
|
||||
|
|
|
@ -1,9 +1,9 @@
|
|||
M(a0 int64) Union(size: 5)
|
||||
M(a1 int64) Union(size: 5)
|
||||
M(a2 int64) Union(size: 5)
|
||||
M(tmp int64) Union(size: 5)
|
||||
M(tmp2 int64) Union(size: 5)
|
||||
M(pp int64) Union(size: 5)
|
||||
M(a3 int64) Union(size: 5)
|
||||
M(a4 int64) Union(size: 5)
|
||||
M(a5 int64) Union(size: 5)
|
||||
M(a6 int64) Union(size: 5)
|
||||
M(a7 int64) Union(size: 5)
|
||||
M(S+0 int64) Union(size: 5)
|
||||
|
|
|
@ -41,6 +41,10 @@ class RegisterNames {
|
|||
ASSERT((0 <= reg) && (reg < kNumberOfCpuRegisters));
|
||||
return cpu_reg_names[reg];
|
||||
}
|
||||
static const char* RegisterAbiName(Register reg) {
|
||||
ASSERT((0 <= reg) && (reg < kNumberOfCpuRegisters));
|
||||
return cpu_reg_abi_names[reg];
|
||||
}
|
||||
static const char* FpuRegisterName(FpuRegister reg) {
|
||||
ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
|
||||
return fpu_reg_names[reg];
|
||||
|
|
|
@ -14,11 +14,21 @@ using dart::bit_cast;
|
|||
|
||||
const char* const cpu_reg_names[kNumberOfCpuRegisters] = {
|
||||
#if defined(DART_TARGET_OS_MACOS) || defined(DART_TARGET_OS_MACOS_IOS)
|
||||
"r0", "r1", "r2", "r3", "r4", "pp", "r6", "fp",
|
||||
"r8", "r9", "thr", "r11", "ip", "sp", "lr", "pc",
|
||||
"r0", "r1", "r2", "r3", "r4", "pp", "r6", "fp",
|
||||
"r8", "r9", "thr", "r11", "tmp", "sp", "lr", "pc",
|
||||
#else
|
||||
"r0", "r1", "r2", "r3", "r4", "pp", "r6", "r7",
|
||||
"r8", "r9", "thr", "fp", "ip", "sp", "lr", "pc",
|
||||
"r0", "r1", "r2", "r3", "r4", "pp", "r6", "r7",
|
||||
"r8", "r9", "thr", "fp", "tmp", "sp", "lr", "pc",
|
||||
#endif
|
||||
};
|
||||
|
||||
const char* const cpu_reg_abi_names[kNumberOfCpuRegisters] = {
|
||||
#if defined(DART_TARGET_OS_MACOS) || defined(DART_TARGET_OS_MACOS_IOS)
|
||||
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "fp",
|
||||
"r8", "r9", "r10", "r11", "ip", "sp", "lr", "pc",
|
||||
#else
|
||||
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
|
||||
"r8", "r9", "r10", "fp", "ip", "sp", "lr", "pc",
|
||||
#endif
|
||||
};
|
||||
|
||||
|
|
|
@ -294,6 +294,7 @@ const int kNumberOfFpuRegisters = kNumberOfQRegisters;
|
|||
const FpuRegister kNoFpuRegister = kNoQRegister;
|
||||
|
||||
extern const char* const cpu_reg_names[kNumberOfCpuRegisters];
|
||||
extern const char* const cpu_reg_abi_names[kNumberOfCpuRegisters];
|
||||
extern const char* const fpu_reg_names[kNumberOfFpuRegisters];
|
||||
extern const char* const fpu_s_reg_names[kNumberOfSRegisters];
|
||||
extern const char* const fpu_d_reg_names[kNumberOfDRegisters];
|
||||
|
|
|
@ -11,9 +11,16 @@
|
|||
namespace dart {
|
||||
|
||||
const char* const cpu_reg_names[kNumberOfCpuRegisters] = {
|
||||
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
|
||||
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "sp",
|
||||
"tmp", "tmp2", "r18", "r19", "r20", "r21", "nr", "r23",
|
||||
"r24", "r25", "thr", "pp", "mask", "fp", "lr", "csp",
|
||||
};
|
||||
|
||||
const char* const cpu_reg_abi_names[kNumberOfCpuRegisters] = {
|
||||
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
|
||||
"r11", "r12", "r13", "r14", "r15", "ip0", "ip1", "r18", "r19", "r20", "r21",
|
||||
"nr", "r23", "r24", "r25", "r26", "pp", "r28", "fp", "lr", "r31",
|
||||
"r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21",
|
||||
"r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "sp",
|
||||
};
|
||||
|
||||
const char* const fpu_reg_names[kNumberOfFpuRegisters] = {
|
||||
|
|
|
@ -129,6 +129,7 @@ const int kNumberOfFpuRegisters = kNumberOfVRegisters;
|
|||
const FpuRegister kNoFpuRegister = kNoVRegister;
|
||||
|
||||
extern const char* const cpu_reg_names[kNumberOfCpuRegisters];
|
||||
extern const char* const cpu_reg_abi_names[kNumberOfCpuRegisters];
|
||||
extern const char* const fpu_reg_names[kNumberOfFpuRegisters];
|
||||
|
||||
// Register aliases.
|
||||
|
|
|
@ -13,6 +13,9 @@ namespace dart {
|
|||
const char* const cpu_reg_names[kNumberOfCpuRegisters] = {
|
||||
"eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi"};
|
||||
|
||||
const char* const cpu_reg_abi_names[kNumberOfCpuRegisters] = {
|
||||
"eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi"};
|
||||
|
||||
const char* const fpu_reg_names[kNumberOfXmmRegisters] = {
|
||||
"xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7"};
|
||||
|
||||
|
|
|
@ -67,6 +67,7 @@ const int kNumberOfFpuRegisters = kNumberOfXmmRegisters;
|
|||
const FpuRegister kNoFpuRegister = kNoXmmRegister;
|
||||
|
||||
extern const char* const cpu_reg_names[kNumberOfCpuRegisters];
|
||||
extern const char* const cpu_reg_abi_names[kNumberOfCpuRegisters];
|
||||
extern const char* const fpu_reg_names[kNumberOfXmmRegisters];
|
||||
|
||||
// Register aliases.
|
||||
|
|
|
@ -23,6 +23,12 @@ const char* const cpu_reg_names[kNumberOfCpuRegisters] = {
|
|||
"s6", "s7", "s8", "s9", "null", "mask", "t3", "t4", "t5", "t6",
|
||||
};
|
||||
|
||||
const char* const cpu_reg_abi_names[kNumberOfCpuRegisters] = {
|
||||
"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0",
|
||||
"a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5",
|
||||
"s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6",
|
||||
};
|
||||
|
||||
const char* const fpu_reg_names[kNumberOfFpuRegisters] = {
|
||||
"ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",
|
||||
"fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",
|
||||
|
|
|
@ -143,6 +143,7 @@ const int kFpuRegisterSize = 8;
|
|||
typedef double fpu_register_t;
|
||||
|
||||
extern const char* const cpu_reg_names[kNumberOfCpuRegisters];
|
||||
extern const char* const cpu_reg_abi_names[kNumberOfCpuRegisters];
|
||||
extern const char* const fpu_reg_names[kNumberOfFpuRegisters];
|
||||
|
||||
// Register aliases.
|
||||
|
|
|
@ -12,7 +12,11 @@ namespace dart {
|
|||
|
||||
const char* const cpu_reg_names[kNumberOfCpuRegisters] = {
|
||||
"rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
|
||||
"r8", "r9", "r10", "r11", "r12", "r13", "thr", "pp"};
|
||||
"r8", "r9", "r10", "tmp", "r12", "r13", "thr", "pp"};
|
||||
|
||||
const char* const cpu_reg_abi_names[kNumberOfCpuRegisters] = {
|
||||
"rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
|
||||
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"};
|
||||
|
||||
const char* const fpu_reg_names[kNumberOfXmmRegisters] = {
|
||||
"xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
|
||||
|
|
|
@ -99,6 +99,7 @@ const int kNumberOfFpuRegisters = kNumberOfXmmRegisters;
|
|||
const FpuRegister kNoFpuRegister = kNoXmmRegister;
|
||||
|
||||
extern const char* const cpu_reg_names[kNumberOfCpuRegisters];
|
||||
extern const char* const cpu_reg_abi_names[kNumberOfCpuRegisters];
|
||||
extern const char* const fpu_reg_names[kNumberOfXmmRegisters];
|
||||
|
||||
enum RexBits {
|
||||
|
|
Loading…
Reference in a new issue