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Switchable call scheduling.

Browse source 
R=fschneider@google.com

Review URL: https://codereview.chromium.org/2404973002 .
This commit is contained in:
Ryan Macnak 2016-10-13 12:44:25 -07:00
parent 6f7696dfc9
commit d8cc8644b1
8 changed files with 28 additions and 28 deletions
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6
runtime/vm/code_patcher_x64.cc
View file

@ -207,9 +207,9 @@ class SwitchableCall : public ValueObject {
bool IsValid() const {
static int16_t pattern[kCallPatternSize] = {
0x49, 0x8b, 0x9f, -1, -1, -1, -1, // movq rbx, [PP + cache_offs]
0x4d, 0x8b, 0xa7, -1, -1, -1, -1, // movq r12, [PP + code_offs]
0x49, 0x8b, 0x4c, 0x24, 0x0f, // movq rcx, [r12 + entrypoint_off]
0x49, 0x8b, 0x9f, -1, -1, -1, -1, // movq rbx, [PP + cache_offs]
0xff, 0xd1, // call rcx
};
ASSERT(ARRAY_SIZE(pattern) == kCallPatternSize);
@ -217,10 +217,10 @@ class SwitchableCall : public ValueObject {
}
intptr_t data_index() const {
return IndexFromPPLoad(start_ + 3);
return IndexFromPPLoad(start_ + 15);
}
intptr_t target_index() const {
return IndexFromPPLoad(start_ + 10);
return IndexFromPPLoad(start_ + 3);
}
RawObject* data() const {

2
runtime/vm/flow_graph_compiler_arm.cc
View file

@ -1354,9 +1354,9 @@ void FlowGraphCompiler::EmitSwitchableInstanceCall(
__ Comment("SwitchableCall");
__ LoadFromOffset(kWord, R0, SP, (argument_count - 1) * kWordSize);
__ LoadUniqueObject(R9, ic_data);
__ LoadUniqueObject(CODE_REG, initial_stub);
__ ldr(LR, FieldAddress(CODE_REG, Code::checked_entry_point_offset()));
__ LoadUniqueObject(R9, ic_data);
__ blx(LR);
AddCurrentDescriptor(RawPcDescriptors::kOther, Thread::kNoDeoptId, token_pos);

2
runtime/vm/flow_graph_compiler_arm64.cc
View file

@ -1334,9 +1334,9 @@ void FlowGraphCompiler::EmitSwitchableInstanceCall(
__ Comment("SwitchableCall");
__ LoadFromOffset(R0, SP, (argument_count - 1) * kWordSize);
__ LoadUniqueObject(R5, ic_data);
__ LoadUniqueObject(CODE_REG, initial_stub);
__ ldr(TMP, FieldAddress(CODE_REG, Code::checked_entry_point_offset()));
__ LoadUniqueObject(R5, ic_data);
__ blr(TMP);
AddCurrentDescriptor(RawPcDescriptors::kOther,

2
runtime/vm/flow_graph_compiler_mips.cc
View file

@ -1358,9 +1358,9 @@ void FlowGraphCompiler::EmitSwitchableInstanceCall(
__ Comment("SwitchableCall");
__ lw(T0, Address(SP, (argument_count - 1) * kWordSize));
__ LoadUniqueObject(S5, ic_data);
__ LoadUniqueObject(CODE_REG, initial_stub);
__ lw(T9, FieldAddress(CODE_REG, Code::checked_entry_point_offset()));
__ LoadUniqueObject(S5, ic_data);
__ jalr(T9);
AddCurrentDescriptor(RawPcDescriptors::kOther,

2
runtime/vm/flow_graph_compiler_x64.cc
View file

@ -1360,9 +1360,9 @@ void FlowGraphCompiler::EmitSwitchableInstanceCall(
__ Comment("SwitchableCall");
__ movq(RDI, Address(RSP, (argument_count - 1) * kWordSize));
__ LoadUniqueObject(RBX, ic_data);
__ LoadUniqueObject(CODE_REG, initial_stub);
__ movq(RCX, FieldAddress(CODE_REG, Code::checked_entry_point_offset()));
__ LoadUniqueObject(RBX, ic_data);
__ call(RCX);
AddCurrentDescriptor(RawPcDescriptors::kOther,

14
runtime/vm/instructions_arm.cc
View file

@ -258,15 +258,15 @@ SwitchableCallPattern::SwitchableCallPattern(uword pc, const Code& code)
ASSERT(*(reinterpret_cast<uword*>(pc) - 1) == 0xe12fff3e);
Register reg;
uword stub_load_end =
InstructionPattern::DecodeLoadWordFromPool(pc - 2 * Instr::kInstrSize,
uword data_load_end =
InstructionPattern::DecodeLoadWordFromPool(pc - Instr::kInstrSize,
&reg,
&target_pool_index_);
ASSERT(reg == CODE_REG);
InstructionPattern::DecodeLoadWordFromPool(stub_load_end,
&reg,
&data_pool_index_);
&data_pool_index_);
ASSERT(reg == R9);
InstructionPattern::DecodeLoadWordFromPool(data_load_end - Instr::kInstrSize,
&reg,
&target_pool_index_);
ASSERT(reg == CODE_REG);
}

14
runtime/vm/instructions_arm64.cc
View file

@ -342,15 +342,15 @@ SwitchableCallPattern::SwitchableCallPattern(uword pc, const Code& code)
ASSERT(*(reinterpret_cast<uint32_t*>(pc) - 1) == 0xd63f0200);
Register reg;
uword stub_load_end =
InstructionPattern::DecodeLoadWordFromPool(pc - 2 * Instr::kInstrSize,
uword data_load_end =
InstructionPattern::DecodeLoadWordFromPool(pc - Instr::kInstrSize,
&reg,
&target_pool_index_);
ASSERT(reg == CODE_REG);
InstructionPattern::DecodeLoadWordFromPool(stub_load_end,
&reg,
&data_pool_index_);
&data_pool_index_);
ASSERT(reg == R5);
InstructionPattern::DecodeLoadWordFromPool(data_load_end - Instr::kInstrSize,
&reg,
&target_pool_index_);
ASSERT(reg == CODE_REG);
}

14
runtime/vm/instructions_mips.cc
View file

@ -227,15 +227,15 @@ SwitchableCallPattern::SwitchableCallPattern(uword pc, const Code& code)
ASSERT(*(reinterpret_cast<uword*>(pc) - 2) == 0x0320f809);
Register reg;
uword stub_load_end =
InstructionPattern::DecodeLoadWordFromPool(pc - 3 * Instr::kInstrSize,
uword data_load_end =
InstructionPattern::DecodeLoadWordFromPool(pc - 2 * Instr::kInstrSize,
&reg,
&target_pool_index_);
ASSERT(reg == CODE_REG);
InstructionPattern::DecodeLoadWordFromPool(stub_load_end,
&reg,
&data_pool_index_);
&data_pool_index_);
ASSERT(reg == S5);
InstructionPattern::DecodeLoadWordFromPool(data_load_end - Instr::kInstrSize,
&reg,
&target_pool_index_);
ASSERT(reg == CODE_REG);
}