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[ VM ] Fix asserts in ARM64 simulator
https://dart-review.googlesource.com/c/sdk/+/148539 hoisted an assert out of a conditional block and started causing failures for DebugSIMARM64 fuzzing runs as `stxr` does not have `Rs = 31`. Change-Id: Ibbcc1ba105567ca1142843261756b8ee6a8e119f Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/149483 Reviewed-by: Ryan Macnak <rmacnak@google.com>
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@ -2171,7 +2171,6 @@ void Simulator::DecodeLoadStoreExclusive(Instr* instr) {
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UNIMPLEMENTED();
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}
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const Register rs = instr->RsField();
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ASSERT(rs == R31); // Should-Be-One
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const Register rn = instr->RnField();
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const Register rt = instr->RtField();
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ASSERT(instr->Rt2Field() == R31); // Should-Be-One
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@ -2181,12 +2180,14 @@ void Simulator::DecodeLoadStoreExclusive(Instr* instr) {
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if (is_load) {
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const bool is_load_acquire = !is_exclusive && is_ordered;
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if (is_load_acquire) {
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ASSERT(rs == R31); // Should-Be-One
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// Format(instr, "ldar 'rt, 'rn");
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const int64_t addr = get_register(rn, R31IsSP);
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const intptr_t value =
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(size == 3) ? ReadAcquire(addr, instr) : ReadAcquireW(addr, instr);
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set_register(instr, rt, value, R31IsSP);
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} else {
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ASSERT(rs == R31); // Should-Be-One
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// Format(instr, "ldxr 'rt, 'rn");
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const int64_t addr = get_register(rn, R31IsSP);
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const intptr_t value = (size == 3) ? ReadExclusiveX(addr, instr)
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@ -2196,6 +2197,7 @@ void Simulator::DecodeLoadStoreExclusive(Instr* instr) {
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} else {
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const bool is_store_release = !is_exclusive && is_ordered;
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if (is_store_release) {
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ASSERT(rs == R31); // Should-Be-One
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// Format(instr, "stlr 'rt, 'rn");
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const uword value = get_register(rt, R31IsSP);
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const uword addr = get_register(rn, R31IsSP);
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