Adds missing case in mips double comparison.

Also, adds mips and simmips to runtime benchmark script,
and fixes up a status file.

R=regis@google.com

Review URL: https://codereview.chromium.org//18123003

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@24541 260f80e4-7a28-3924-810f-c04153c831b5
This commit is contained in:
zra@google.com 2013-06-27 19:03:04 +00:00
parent f48d70cec2
commit 55d97a6d56
3 changed files with 18 additions and 6 deletions

View file

@ -54,7 +54,7 @@ def BuildOptions():
default=False, action="store_true")
result.add_option("--arch",
help='Target architectures (comma-separated).',
metavar='[all,ia32,x64,simarm,arm,dartc]',
metavar='[all,ia32,x64,simarm,simmips,arm,mips,dartc]',
default=utils.GuessArchitecture())
result.add_option("--executable",
help='Virtual machine to execute.',
@ -68,7 +68,7 @@ def BuildOptions():
def ProcessOptions(options):
if options.arch == 'all':
options.arch = 'ia32,x64,simarm,dartc'
options.arch = 'ia32,x64,simarm,simmips,dartc'
if options.mode == 'all':
options.mode = 'debug,release'
options.mode = options.mode.split(',')
@ -78,7 +78,7 @@ def ProcessOptions(options):
print "Unknown mode %s" % mode
return False
for arch in options.arch:
if not arch in ['ia32', 'x64', 'simarm', 'arm', 'dartc']:
if not arch in ['ia32', 'x64', 'simarm', 'simmips', 'arm', 'mips', 'dartc']:
print "Unknown arch %s" % arch
return False
return True

View file

@ -1597,6 +1597,7 @@ void FlowGraphCompiler::EmitDoubleCompareBranch(Condition true_condition,
switch (true_condition) {
case EQ: assembler()->ceqd(left, right); break;
case NE: assembler()->ceqd(left, right); break;
case LT: assembler()->coltd(left, right); break;
case LE: assembler()->coled(left, right); break;
case GT: assembler()->coltd(right, left); break;
@ -1609,8 +1610,13 @@ void FlowGraphCompiler::EmitDoubleCompareBranch(Condition true_condition,
}
assembler()->LoadImmediate(TMP, 1);
assembler()->movf(CMPRES, TMP);
assembler()->movt(CMPRES, ZR);
if (true_condition == NE) {
assembler()->movf(CMPRES, ZR);
assembler()->movt(CMPRES, TMP);
} else {
assembler()->movf(CMPRES, TMP);
assembler()->movt(CMPRES, ZR);
}
assembler()->mov(TMP, ZR);
// EmitBranchOnCondition expects ordering to be described by CMPRES, TMP1.
@ -1630,6 +1636,7 @@ void FlowGraphCompiler::EmitDoubleCompareBool(Condition true_condition,
switch (true_condition) {
case EQ: assembler()->ceqd(left, right); break;
case NE: assembler()->ceqd(left, right); break;
case LT: assembler()->coltd(left, right); break;
case LE: assembler()->coled(left, right); break;
case GT: assembler()->coltd(right, left); break;
@ -1641,7 +1648,11 @@ void FlowGraphCompiler::EmitDoubleCompareBool(Condition true_condition,
}
}
assembler()->bc1f(&done); // False is already in result.
if (true_condition == NE) {
assembler()->bc1t(&done); // False is already in result.
} else {
assembler()->bc1f(&done);
}
assembler()->LoadObject(result, Bool::True());
assembler()->Bind(&done);
}

View file

@ -168,6 +168,7 @@ out_of_memory_test: Crash
*: Skip
[ $arch == simmips ]
io/file_fuzz_test: Pass, Timeout
left_shift_bit_and_op_test: Fail
out_of_memory_test: Crash