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[vm, compiler] Remove surprising truncation from x64's LoadImmediate.
All other architectures have a LoadImmediate that works with any uword, but x64's truncated to 32-bit, causing surprising x64-only failures when LoadImmediate is used from architecture-independent parts of the compiler. TEST=ci Change-Id: Ia2b2cfd1df7396833e4508ed21b4995fc9af464b Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/268040 Commit-Queue: Ryan Macnak <rmacnak@google.com> Reviewed-by: Alexander Markov <alexmarkov@google.com>
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@ -1161,7 +1161,7 @@ void Assembler::AddImmediate(Register reg,
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}
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}
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void Assembler::AddImmediate(Register dest, Register src, int32_t value) {
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void Assembler::AddImmediate(Register dest, Register src, int64_t value) {
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if (dest == src) {
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AddImmediate(dest, value);
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return;
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@ -1170,7 +1170,12 @@ void Assembler::AddImmediate(Register dest, Register src, int32_t value) {
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MoveRegister(dest, src);
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return;
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}
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leaq(dest, Address(src, value));
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if (Utils::IsInt(32, value)) {
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leaq(dest, Address(src, value));
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return;
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}
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LoadImmediate(dest, value);
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addq(dest, src);
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}
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void Assembler::AddImmediate(const Address& address, const Immediate& imm) {
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@ -566,7 +566,7 @@ class Assembler : public AssemblerBase {
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const Immediate& imm,
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OperandSize width = kEightBytes);
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void CompareImmediate(Register reg,
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int32_t immediate,
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int64_t immediate,
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OperandSize width = kEightBytes) {
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return CompareImmediate(reg, Immediate(immediate), width);
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}
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@ -583,11 +583,11 @@ class Assembler : public AssemblerBase {
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OperandSize width = kEightBytes);
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void AndImmediate(Register dst, const Immediate& imm);
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void AndImmediate(Register dst, int32_t value) {
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void AndImmediate(Register dst, int64_t value) {
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AndImmediate(dst, Immediate(value));
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}
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void OrImmediate(Register dst, const Immediate& imm);
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void OrImmediate(Register dst, int32_t value) {
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void OrImmediate(Register dst, int64_t value) {
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OrImmediate(dst, Immediate(value));
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}
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void XorImmediate(Register dst, const Immediate& imm);
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@ -767,7 +767,7 @@ class Assembler : public AssemblerBase {
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const Immediate& imm,
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OperandSize width = kEightBytes);
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void AddImmediate(Register reg,
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int32_t value,
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int64_t value,
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OperandSize width = kEightBytes) {
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AddImmediate(reg, Immediate(value), width);
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}
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@ -780,7 +780,7 @@ class Assembler : public AssemblerBase {
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int32_t value) {
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leaq(dest, Address(src, scale, value));
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}
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void AddImmediate(Register dest, Register src, int32_t value);
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void AddImmediate(Register dest, Register src, int64_t value);
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void AddImmediate(const Address& address, const Immediate& imm);
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void SubImmediate(Register reg,
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const Immediate& imm,
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@ -797,7 +797,7 @@ class Assembler : public AssemblerBase {
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// Unlike movq this can affect the flags or use the constant pool.
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void LoadImmediate(Register reg, const Immediate& imm);
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void LoadImmediate(Register reg, int32_t immediate) {
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void LoadImmediate(Register reg, int64_t immediate) {
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LoadImmediate(reg, Immediate(immediate));
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}
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void LoadDImmediate(FpuRegister dst, double immediate);
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@ -6066,6 +6066,66 @@ ASSEMBLER_TEST_RUN(ImmediateMacros, test) {
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"ret\n");
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}
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ASSEMBLER_TEST_GENERATE(ImmediateMacros64, assembler) {
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const intptr_t kTrillion = 1000000000000;
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{
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__ LoadImmediate(RAX, kTrillion);
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Label ok;
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__ CompareImmediate(RAX, kTrillion);
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__ j(EQUAL, &ok);
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__ int3();
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__ Bind(&ok);
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}
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{
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__ LoadImmediate(RAX, 3);
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__ AddImmediate(RAX, kTrillion);
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Label ok;
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__ CompareImmediate(RAX, 3 + kTrillion);
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__ j(EQUAL, &ok);
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__ int3();
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__ Bind(&ok);
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}
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{
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__ LoadImmediate(RAX, 5);
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__ AddImmediate(RBX, RAX, kTrillion);
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Label ok;
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__ CompareImmediate(RBX, 5 + kTrillion);
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__ j(EQUAL, &ok);
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__ int3();
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__ Bind(&ok);
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}
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__ LoadImmediate(RAX, 42);
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__ ret();
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}
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ASSEMBLER_TEST_RUN(ImmediateMacros64, test) {
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typedef int (*ImmediateMacrosCode)();
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int res = reinterpret_cast<ImmediateMacrosCode>(test->entry())();
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EXPECT_EQ(42, res);
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EXPECT_DISASSEMBLY(
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"movq rax,0x000000e8d4a51000\n"
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"movq tmp,0x000000e8d4a51000\n"
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"cmpq rax,tmp\n"
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"jz +7\n"
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"int3\n"
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"movl rax,3\n"
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"movq tmp,0x000000e8d4a51000\n"
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"addq rax,tmp\n"
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"movq tmp,0x000000e8d4a51003\n"
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"cmpq rax,tmp\n"
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"jz +7\n"
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"int3\n"
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"movl rax,5\n"
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"movq rbx,0x000000e8d4a51000\n"
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"addq rbx,rax\n"
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"movq tmp,0x000000e8d4a51005\n"
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"cmpq rbx,tmp\n"
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"jz +7\n"
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"int3\n"
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"movl rax,0x2a\n"
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"ret\n");
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}
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// clang-format off
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#define ALU_TEST(NAME, WIDTH, INTRO, LHS, RHS, OUTRO) \
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ASSEMBLER_TEST_GENERATE(NAME, assembler) { \
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