[vm, compiler] Remove surprising truncation from x64's LoadImmediate.

All other architectures have a LoadImmediate that works with any uword, but x64's truncated to 32-bit, causing surprising x64-only failures when LoadImmediate is used from architecture-independent parts of the compiler.

TEST=ci
Change-Id: Ia2b2cfd1df7396833e4508ed21b4995fc9af464b
Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/268040
Commit-Queue: Ryan Macnak <rmacnak@google.com>
Reviewed-by: Alexander Markov <alexmarkov@google.com>
This commit is contained in:
Ryan Macnak 2022-11-04 21:42:27 +00:00 committed by Commit Queue
parent cc80ccfaa0
commit 48b2d7e0e9
3 changed files with 73 additions and 8 deletions

View file

@ -1161,7 +1161,7 @@ void Assembler::AddImmediate(Register reg,
}
}
void Assembler::AddImmediate(Register dest, Register src, int32_t value) {
void Assembler::AddImmediate(Register dest, Register src, int64_t value) {
if (dest == src) {
AddImmediate(dest, value);
return;
@ -1170,7 +1170,12 @@ void Assembler::AddImmediate(Register dest, Register src, int32_t value) {
MoveRegister(dest, src);
return;
}
leaq(dest, Address(src, value));
if (Utils::IsInt(32, value)) {
leaq(dest, Address(src, value));
return;
}
LoadImmediate(dest, value);
addq(dest, src);
}
void Assembler::AddImmediate(const Address& address, const Immediate& imm) {

View file

@ -566,7 +566,7 @@ class Assembler : public AssemblerBase {
const Immediate& imm,
OperandSize width = kEightBytes);
void CompareImmediate(Register reg,
int32_t immediate,
int64_t immediate,
OperandSize width = kEightBytes) {
return CompareImmediate(reg, Immediate(immediate), width);
}
@ -583,11 +583,11 @@ class Assembler : public AssemblerBase {
OperandSize width = kEightBytes);
void AndImmediate(Register dst, const Immediate& imm);
void AndImmediate(Register dst, int32_t value) {
void AndImmediate(Register dst, int64_t value) {
AndImmediate(dst, Immediate(value));
}
void OrImmediate(Register dst, const Immediate& imm);
void OrImmediate(Register dst, int32_t value) {
void OrImmediate(Register dst, int64_t value) {
OrImmediate(dst, Immediate(value));
}
void XorImmediate(Register dst, const Immediate& imm);
@ -767,7 +767,7 @@ class Assembler : public AssemblerBase {
const Immediate& imm,
OperandSize width = kEightBytes);
void AddImmediate(Register reg,
int32_t value,
int64_t value,
OperandSize width = kEightBytes) {
AddImmediate(reg, Immediate(value), width);
}
@ -780,7 +780,7 @@ class Assembler : public AssemblerBase {
int32_t value) {
leaq(dest, Address(src, scale, value));
}
void AddImmediate(Register dest, Register src, int32_t value);
void AddImmediate(Register dest, Register src, int64_t value);
void AddImmediate(const Address& address, const Immediate& imm);
void SubImmediate(Register reg,
const Immediate& imm,
@ -797,7 +797,7 @@ class Assembler : public AssemblerBase {
// Unlike movq this can affect the flags or use the constant pool.
void LoadImmediate(Register reg, const Immediate& imm);
void LoadImmediate(Register reg, int32_t immediate) {
void LoadImmediate(Register reg, int64_t immediate) {
LoadImmediate(reg, Immediate(immediate));
}
void LoadDImmediate(FpuRegister dst, double immediate);

View file

@ -6066,6 +6066,66 @@ ASSEMBLER_TEST_RUN(ImmediateMacros, test) {
"ret\n");
}
ASSEMBLER_TEST_GENERATE(ImmediateMacros64, assembler) {
const intptr_t kTrillion = 1000000000000;
{
__ LoadImmediate(RAX, kTrillion);
Label ok;
__ CompareImmediate(RAX, kTrillion);
__ j(EQUAL, &ok);
__ int3();
__ Bind(&ok);
}
{
__ LoadImmediate(RAX, 3);
__ AddImmediate(RAX, kTrillion);
Label ok;
__ CompareImmediate(RAX, 3 + kTrillion);
__ j(EQUAL, &ok);
__ int3();
__ Bind(&ok);
}
{
__ LoadImmediate(RAX, 5);
__ AddImmediate(RBX, RAX, kTrillion);
Label ok;
__ CompareImmediate(RBX, 5 + kTrillion);
__ j(EQUAL, &ok);
__ int3();
__ Bind(&ok);
}
__ LoadImmediate(RAX, 42);
__ ret();
}
ASSEMBLER_TEST_RUN(ImmediateMacros64, test) {
typedef int (*ImmediateMacrosCode)();
int res = reinterpret_cast<ImmediateMacrosCode>(test->entry())();
EXPECT_EQ(42, res);
EXPECT_DISASSEMBLY(
"movq rax,0x000000e8d4a51000\n"
"movq tmp,0x000000e8d4a51000\n"
"cmpq rax,tmp\n"
"jz +7\n"
"int3\n"
"movl rax,3\n"
"movq tmp,0x000000e8d4a51000\n"
"addq rax,tmp\n"
"movq tmp,0x000000e8d4a51003\n"
"cmpq rax,tmp\n"
"jz +7\n"
"int3\n"
"movl rax,5\n"
"movq rbx,0x000000e8d4a51000\n"
"addq rbx,rax\n"
"movq tmp,0x000000e8d4a51005\n"
"cmpq rbx,tmp\n"
"jz +7\n"
"int3\n"
"movl rax,0x2a\n"
"ret\n");
}
// clang-format off
#define ALU_TEST(NAME, WIDTH, INTRO, LHS, RHS, OUTRO) \
ASSEMBLER_TEST_GENERATE(NAME, assembler) { \