mirror of
https://github.com/dart-lang/sdk
synced 2024-09-04 16:03:44 +00:00
[vm] Enable clang-tidy for arm, arm64, riscv64, product, release, precompiler.
TEST=ci Change-Id: I319c932a6f4b6e18d7e53b66d69702bf017e4b93 Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/313060 Commit-Queue: Ryan Macnak <rmacnak@google.com> Reviewed-by: Alexander Aprelev <aam@google.com>
This commit is contained in:
parent
80a6670d5d
commit
453fce9e77
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@ -7,6 +7,8 @@
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#include <atomic>
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#include "platform/assert.h"
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namespace dart {
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namespace bin {
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@ -35,6 +35,13 @@ Future<void> generatePerfettoBuildFlags() async {
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const String clangTidy = './buildtools/linux-x64/clang/bin/clang-tidy';
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List<String> compilerFlagsForFile(String filepath) {
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String arch = "X64";
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if (filepath.contains("_arm.")) arch = "ARM";
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if (filepath.contains("_arm64.")) arch = "ARM64";
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if (filepath.contains("_riscv.")) arch = "RISCV64";
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// Skipping IA32 because it neither has a simulator nor works with crossword
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// and the host architecture is fixed.
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final flags = <String>[
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'-Iruntime',
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'-Ithird_party',
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@ -43,9 +50,7 @@ List<String> compilerFlagsForFile(String filepath) {
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'-Ithird_party/perfetto/include',
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'-Ithird_party/zlib',
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'-Iout/DebugX64/gen/third_party/perfetto/build_config',
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'-DTARGET_ARCH_X64',
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'-DDEBUG',
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'-DDART_TARGET_OS_LINUX',
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'-DTARGET_ARCH_$arch',
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'-DTESTING',
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'-std=c++17',
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'-x',
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@ -54,13 +59,6 @@ List<String> compilerFlagsForFile(String filepath) {
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return flags;
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}
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Future<ProcessResult> runClangTidyOn(String filepath) async {
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// The `runtime/.clang-tidy` file has the enabled checks in it.
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final args = <String>['-quiet', filepath, '--']
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..addAll(compilerFlagsForFile(filepath));
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return await Process.run(clangTidy, args);
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}
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final pool = new Pool(max(1, Platform.numberOfProcessors ~/ 2));
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// Exclude running the linter on those files.
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@ -84,6 +82,8 @@ final Set<String> excludedFiles = Set<String>.from([
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'runtime/bin/namespace_linux.h',
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'runtime/bin/namespace_macos.h',
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'runtime/bin/namespace_win.h',
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'runtime/bin/platform_macos.h',
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'runtime/bin/platform_macos_cocoa.h',
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'runtime/bin/socket_base_android.h',
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'runtime/bin/socket_base_fuchsia.h',
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'runtime/bin/socket_base_linux.h',
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@ -133,9 +133,10 @@ final Set<String> excludedFiles = Set<String>.from([
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'runtime/vm/os_thread_macos.h',
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'runtime/vm/os_thread_win.h',
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'runtime/vm/regexp_assembler_bytecode_inl.h',
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'runtime/vm/simulator_arm64.h',
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'runtime/vm/simulator_arm.h',
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'runtime/vm/simulator_arm64.h',
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'runtime/vm/simulator_riscv.h',
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'runtime/vm/simulator_x64.h',
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'runtime/vm/stack_frame_arm.h',
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'runtime/vm/stack_frame_arm64.h',
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'runtime/vm/stack_frame_ia32.h',
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@ -148,6 +149,32 @@ final Set<String> excludedFiles = Set<String>.from([
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'runtime/vm/compiler/backend/locations_helpers_arm.h',
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]);
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final defineSets = [
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[
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'-DDEBUG',
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],
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[
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'-DNDEBUG',
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],
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[
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'-DNDEBUG',
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'-DPRODUCT',
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],
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[
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'-DDART_PRECOMPILER',
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'-DDEBUG',
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],
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[
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'-DDART_PRECOMPILER',
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'-DNDEBUG',
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],
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[
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'-DDART_PRECOMPILER',
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'-DNDEBUG',
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'-DPRODUCT',
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],
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];
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main(List<String> files) async {
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await generatePerfettoBuildFlags();
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@ -156,32 +183,39 @@ main(List<String> files) async {
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files = files.where((filepath) => !excludedFiles.contains(filepath)).toList();
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// Analyze the [files] in parallel.
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await Future.wait(files.map((String filepath) async {
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final processResult =
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await pool.withResource(() => runClangTidyOn(filepath));
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for (List<String> defines in defineSets) {
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await Future.wait(files.map((String filepath) async {
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// The `runtime/.clang-tidy` file has the enabled checks in it.
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final args = <String>['-quiet', filepath, '--']
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..addAll(compilerFlagsForFile(filepath))
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..addAll(defines);
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final processResult =
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await pool.withResource(() => Process.run(clangTidy, args));
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final int exitCode = processResult.exitCode;
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final String stdout = processResult.stdout.trim();
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final String stderr = processResult.stderr.trim();
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final int exitCode = processResult.exitCode;
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final String stdout = processResult.stdout.trim();
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final String stderr = processResult.stderr.trim();
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if (exitCode != 0 || stdout.isNotEmpty) {
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if (!isFirstFailure) {
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print('');
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print('--------------------------------------------------------------');
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print('');
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if (exitCode != 0 || stdout.isNotEmpty) {
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if (!isFirstFailure) {
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print('');
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print('------------------------------------------------------------');
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print('');
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}
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isFirstFailure = false;
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}
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isFirstFailure = false;
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}
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if (exitCode != 0) {
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print('exit-code: $exitCode');
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print('stdout:');
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print('${stdout}');
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print('stderr:');
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print('${stderr}');
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} else if (stdout.isNotEmpty) {
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// The actual lints go to stdout.
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print(stdout);
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}
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}));
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if (exitCode != 0) {
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print('command: $clangTidy ${args.join(" ")}');
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print('exit-code: $exitCode');
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print('stdout:');
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print('${stdout}');
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print('stderr:');
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print('${stderr}');
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} else if (stdout.isNotEmpty) {
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// The actual lints go to stdout.
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print(stdout);
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}
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}));
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}
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}
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@ -7,6 +7,7 @@
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#include <type_traits>
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#include "platform/assert.h"
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#include "platform/atomic.h"
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#include "platform/globals.h"
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#include "platform/thread_sanitizer.h"
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@ -1061,13 +1061,13 @@ void ARMDecoder::DecodeType6(Instr* instr) {
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}
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} else if (instr->IsVFPMultipleLoadStore()) {
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if (instr->HasL()) { // vldm
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if (instr->Bit(8)) { // vldmd
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if (instr->Bit(8) != 0) { // vldmd
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Format(instr, "vldmd'cond'pu 'rn'w, 'dlist");
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} else { // vldms
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Format(instr, "vldms'cond'pu 'rn'w, 'slist");
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}
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} else { // vstm
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if (instr->Bit(8)) { // vstmd
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if (instr->Bit(8) != 0) { // vstmd
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Format(instr, "vstmd'cond'pu 'rn'w, 'dlist");
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} else { // vstms
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Format(instr, "vstms'cond'pu 'rn'w, 'slist");
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@ -1388,11 +1388,11 @@ void ARMDecoder::DecodeSIMDDataProcessing(Instr* instr) {
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(instr->Bits(20, 2) == 3) && (instr->Bits(23, 2) == 3) &&
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(instr->Bit(7) == 0)) {
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int32_t imm4 = instr->Bits(16, 4);
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if (imm4 & 1) {
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if ((imm4 & 1) != 0) {
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Format(instr, "vdupb 'qd, 'dm['imm4_vdup]");
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} else if (imm4 & 2) {
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} else if ((imm4 & 2) != 0) {
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Format(instr, "vduph 'qd, 'dm['imm4_vdup]");
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} else if (imm4 & 4) {
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} else if ((imm4 & 4) != 0) {
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Format(instr, "vdupw 'qd, 'dm['imm4_vdup]");
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} else {
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Unknown(instr);
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@ -1506,7 +1506,7 @@ void Disassembler::DecodeInstruction(char* hex_buffer,
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decoder.InstructionDecode(pc);
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int32_t instruction_bits = Instr::At(pc)->InstructionBits();
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Utils::SNPrint(hex_buffer, hex_size, "%08x", instruction_bits);
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if (out_instr_size) {
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if (out_instr_size != nullptr) {
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*out_instr_size = Instr::kInstrSize;
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}
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@ -380,13 +380,13 @@ int ARM64Decoder::FormatOption(Instr* instr, const char* format) {
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ASSERT(STRING_STARTS_WITH(format, "csz"));
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const int32_t imm5 = instr->Bits(16, 5);
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char const* typ = "??";
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if (imm5 & 0x1) {
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if ((imm5 & 0x1) != 0) {
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typ = "b";
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} else if (imm5 & 0x2) {
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} else if ((imm5 & 0x2) != 0) {
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typ = "h";
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} else if (imm5 & 0x4) {
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} else if ((imm5 & 0x4) != 0) {
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typ = "s";
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} else if (imm5 & 0x8) {
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} else if ((imm5 & 0x8) != 0) {
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typ = "d";
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}
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buffer_pos_ += Utils::SNPrint(current_position_in_buffer(),
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shift = 1;
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}
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int32_t idx = -1;
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if (imm5 & 0x1) {
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if ((imm5 & 0x1) != 0) {
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idx = imm >> shift;
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} else if (imm5 & 0x2) {
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} else if ((imm5 & 0x2) != 0) {
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idx = imm >> (shift + 1);
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} else if (imm5 & 0x4) {
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} else if ((imm5 & 0x4) != 0) {
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idx = imm >> (shift + 2);
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} else if (imm5 & 0x8) {
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} else if ((imm5 & 0x8) != 0) {
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idx = imm >> (shift + 3);
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}
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buffer_pos_ += Utils::SNPrint(current_position_in_buffer(),
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(instr->Bits(24, 3) != 0)) {
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Unknown(instr);
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}
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if (instr->Bit(30)) {
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if (instr->Bit(30) != 0) {
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Format(instr, "ldrx 'rt, 'pcldr");
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} else {
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Format(instr, "ldrw 'rt, 'pcldr");
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decoder.InstructionDecode(pc);
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int32_t instruction_bits = Instr::At(pc)->InstructionBits();
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Utils::SNPrint(hex_buffer, hex_size, "%08x", instruction_bits);
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if (out_instr_size) {
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if (out_instr_size != nullptr) {
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*out_instr_size = Instr::kInstrSize;
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}
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@ -259,7 +259,7 @@ void RISCVDisassembler::DisassembleInstruction(CInstr instr) {
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break;
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#endif
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case C_JR:
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if (instr.encoding() & (C_JALR ^ C_JR)) {
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if ((instr.encoding() & (C_JALR ^ C_JR)) != 0) {
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if ((instr.rs1() == ZR) && (instr.rs2() == ZR)) {
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Print("ebreak", instr, RV_C);
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} else if (instr.rs2() == ZR) {
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Utils::SNPrint(hex_buffer, hex_size, "%08x",
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LoadUnaligned(reinterpret_cast<uint32_t*>(pc)));
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}
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if (out_instr_size) {
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if (out_instr_size != nullptr) {
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*out_instr_size = instr_size;
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}
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@ -932,7 +932,9 @@ const intptr_t kReleaseShift = 25;
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const intptr_t kAcquireShift = 26;
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#define DEFINE_REG_ENCODING(type, name, shift) \
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inline uint32_t Is##name(type r) { return static_cast<uint32_t>(r) < 32; } \
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inline bool Is##name(type r) { \
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return static_cast<uint32_t>(r) < 32; \
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} \
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inline uint32_t Encode##name(type r) { \
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ASSERT(Is##name(r)); \
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return static_cast<uint32_t>(r) << shift; \
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@ -951,7 +953,9 @@ DEFINE_REG_ENCODING(FRegister, FRs3, 27)
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#undef DEFINE_REG_ENCODING
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#define DEFINE_FUNCT_ENCODING(type, name, shift, mask) \
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inline uint32_t Is##name(type f) { return (f & mask) == f; } \
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inline bool Is##name(type f) { \
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return (f & mask) == f; \
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} \
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inline uint32_t Encode##name(type f) { \
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ASSERT(Is##name(f)); \
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return f << shift; \
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@ -1125,7 +1129,9 @@ class Instr {
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};
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#define DEFINE_REG_ENCODING(type, name, shift) \
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inline uint32_t Is##name(type r) { return static_cast<uint32_t>(r) < 32; } \
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inline bool Is##name(type r) { \
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return static_cast<uint32_t>(r) < 32; \
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} \
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inline uint32_t Encode##name(type r) { \
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ASSERT(Is##name(r)); \
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return static_cast<uint32_t>(r) << shift; \
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@ -1135,7 +1141,9 @@ class Instr {
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}
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#define DEFINE_REG_PRIME_ENCODING(type, name, shift) \
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inline uint32_t Is##name(type r) { return (r >= 8) && (r < 16); } \
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inline bool Is##name(type r) { \
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return (r >= 8) && (r < 16); \
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} \
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inline uint32_t Encode##name(type r) { \
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ASSERT(Is##name(r)); \
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return (static_cast<uint32_t>(r) & 7) << shift; \
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@ -606,7 +606,7 @@ class LineNumberProgramWriter {
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intptr_t file_ = 1;
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intptr_t line_ = 1;
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intptr_t column_ = 0;
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intptr_t end_sequence_ = false;
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bool end_sequence_ = false;
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// Other info not stored in the state machine registers.
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intptr_t label_ = 0;
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@ -10,7 +10,8 @@
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#include <atomic>
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#include "include/dart_api.h"
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#include "vm/allocation.h"
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#include "vm/globals.h"
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namespace dart {
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@ -310,8 +310,8 @@ bool DecodeLoadObjectFromPoolOrThread(uword pc, const Code& code, Object* obj) {
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}
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if (instr->RnField() == instr->RtField()) {
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Instr* add = Instr::At(pc - Instr::kInstrSize);
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if (add->IsAddSubImmOp() && add->SFField() && (instr->Bit(22) == 1) &&
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(add->RdField() == add->RtField())) {
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if (add->IsAddSubImmOp() && (add->SFField() != 0) &&
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(instr->Bit(22) == 1) && (add->RdField() == add->RtField())) {
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offset = (add->Imm12Field() << 12) + offset;
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if (add->RnField() == PP) {
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// PP is untagged on ARM64.
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@ -326,7 +326,7 @@ bool DecodeLoadObjectFromPoolOrThread(uword pc, const Code& code, Object* obj) {
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// TODO(rmacnak): Loads with offsets beyond 24 bits.
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}
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if (instr->IsAddSubImmOp() && instr->SFField() &&
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if (instr->IsAddSubImmOp() && (instr->SFField() != 0) &&
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(instr->RnField() == NULL_REG)) {
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uint32_t imm = (instr->Bit(22) == 1) ? (instr->Imm12Field() << 12)
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: (instr->Imm12Field());
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|
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@ -676,10 +676,10 @@ void SimulatorDebugger::Debug() {
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}
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} else if (strcmp(cmd, "flags") == 0) {
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OS::PrintErr("APSR: ");
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OS::PrintErr("N flag: %d; ", sim_->n_flag_);
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OS::PrintErr("Z flag: %d; ", sim_->z_flag_);
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OS::PrintErr("C flag: %d; ", sim_->c_flag_);
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OS::PrintErr("V flag: %d\n", sim_->v_flag_);
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OS::PrintErr("N flag: %d; ", static_cast<int>(sim_->n_flag_));
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OS::PrintErr("Z flag: %d; ", static_cast<int>(sim_->z_flag_));
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OS::PrintErr("C flag: %d; ", static_cast<int>(sim_->c_flag_));
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OS::PrintErr("V flag: %d\n", static_cast<int>(sim_->v_flag_));
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} else if (strcmp(cmd, "unstop") == 0) {
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intptr_t stop_pc = sim_->get_pc() - Instr::kInstrSize;
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Instr* stop_instr = reinterpret_cast<Instr*>(stop_pc);
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@ -1355,7 +1355,7 @@ void Simulator::DecodeMoveWide(Instr* instr) {
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const int64_t shifted_imm = static_cast<int64_t>(instr->Imm16Field())
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<< shift;
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if (instr->SFField()) {
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if (instr->SFField() != 0) {
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if (instr->Bits(29, 2) == 0) {
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// Format(instr, "movn'sf 'rd, 'imm16 'hw");
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set_register(instr, rd, ~shifted_imm, instr->RdMode());
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@ -1399,7 +1399,7 @@ void Simulator::DecodeAddSubImm(Instr* instr) {
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const Register rn = instr->RnField();
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uint32_t imm = (instr->Bit(22) == 1) ? (instr->Imm12Field() << 12)
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: (instr->Imm12Field());
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||||
if (instr->SFField()) {
|
||||
if (instr->SFField() != 0) {
|
||||
// 64-bit add.
|
||||
const uint64_t rn_val = get_register(rn, instr->RnMode());
|
||||
const uint64_t alu_out = addition ? (rn_val + imm) : (rn_val - imm);
|
||||
|
@ -2155,7 +2155,7 @@ void Simulator::DecodeLoadStoreRegPair(Instr* instr) {
|
|||
// SIMD/FP.
|
||||
const VRegister vt = instr->VtField();
|
||||
const VRegister vt2 = instr->Vt2Field();
|
||||
if (instr->Bit(22)) {
|
||||
if (instr->Bit(22) != 0) {
|
||||
// Format(instr, "ldp 'vt, 'vt2, 'memop");
|
||||
switch (size) {
|
||||
case 4:
|
||||
|
@ -2215,7 +2215,7 @@ void Simulator::DecodeLoadStoreRegPair(Instr* instr) {
|
|||
// Integer.
|
||||
const Register rt = instr->RtField();
|
||||
const Register rt2 = instr->Rt2Field();
|
||||
if (instr->Bit(22)) {
|
||||
if (instr->Bit(22) != 0) {
|
||||
// Format(instr, "ldp'sf 'rt, 'rt2, 'memop");
|
||||
const bool is_signed = instr->Bit(30) == 1;
|
||||
int64_t val1 = 0; // Sign extend into an int64_t.
|
||||
|
@ -2274,7 +2274,7 @@ void Simulator::DecodeLoadRegLiteral(Instr* instr) {
|
|||
const int64_t pc = reinterpret_cast<int64_t>(instr);
|
||||
const int64_t address = pc + off;
|
||||
const int64_t val = ReadX(address, instr);
|
||||
if (instr->Bit(30)) {
|
||||
if (instr->Bit(30) != 0) {
|
||||
// Format(instr, "ldrx 'rt, 'pcldr");
|
||||
set_register(instr, rt, val, R31IsZR);
|
||||
} else {
|
||||
|
@ -2487,7 +2487,8 @@ int64_t Simulator::ExtendOperand(uint8_t reg_size,
|
|||
int64_t Simulator::DecodeShiftExtendOperand(Instr* instr) {
|
||||
const Register rm = instr->RmField();
|
||||
const int64_t rm_val = get_register(rm, R31IsZR);
|
||||
const uint8_t size = instr->SFField() ? kXRegSizeInBits : kWRegSizeInBits;
|
||||
const uint8_t size =
|
||||
instr->SFField() != 0 ? kXRegSizeInBits : kWRegSizeInBits;
|
||||
if (instr->IsShift()) {
|
||||
const Shift shift_type = instr->ShiftTypeField();
|
||||
const uint8_t shift_amount = instr->Imm6Field();
|
||||
|
@ -2509,7 +2510,7 @@ void Simulator::DecodeAddSubShiftExt(Instr* instr) {
|
|||
const Register rd = instr->RdField();
|
||||
const Register rn = instr->RnField();
|
||||
const uint64_t rm_val = DecodeShiftExtendOperand(instr);
|
||||
if (instr->SFField()) {
|
||||
if (instr->SFField() != 0) {
|
||||
// 64-bit add.
|
||||
const uint64_t rn_val = get_register(rn, instr->RnMode());
|
||||
const uint64_t alu_out = rn_val + (addition ? rm_val : -rm_val);
|
||||
|
@ -2550,7 +2551,7 @@ void Simulator::DecodeAddSubWithCarry(Instr* instr) {
|
|||
const uint64_t rm_val64 = get_register(rm, R31IsZR);
|
||||
uint32_t rm_val32 = get_wregister(rm, R31IsZR);
|
||||
const uint32_t carry_in = c_flag_ ? 1 : 0;
|
||||
if (instr->SFField()) {
|
||||
if (instr->SFField() != 0) {
|
||||
// 64-bit add.
|
||||
const uint64_t alu_out =
|
||||
rn_val64 + (addition ? rm_val64 : ~rm_val64) + carry_in;
|
||||
|
@ -2965,19 +2966,19 @@ void Simulator::DecodeSIMDCopy(Instr* instr) {
|
|||
int32_t idx4 = -1;
|
||||
int32_t idx5 = -1;
|
||||
int32_t element_bytes;
|
||||
if (imm5 & 0x1) {
|
||||
if ((imm5 & 0x1) != 0) {
|
||||
idx4 = imm4;
|
||||
idx5 = imm5 >> 1;
|
||||
element_bytes = 1;
|
||||
} else if (imm5 & 0x2) {
|
||||
} else if ((imm5 & 0x2) != 0) {
|
||||
idx4 = imm4 >> 1;
|
||||
idx5 = imm5 >> 2;
|
||||
element_bytes = 2;
|
||||
} else if (imm5 & 0x4) {
|
||||
} else if ((imm5 & 0x4) != 0) {
|
||||
idx4 = imm4 >> 2;
|
||||
idx5 = imm5 >> 3;
|
||||
element_bytes = 4;
|
||||
} else if (imm5 & 0x8) {
|
||||
} else if ((imm5 & 0x8) != 0) {
|
||||
idx4 = imm4 >> 3;
|
||||
idx5 = imm5 >> 4;
|
||||
element_bytes = 8;
|
||||
|
|
|
@ -687,7 +687,7 @@ void Simulator::Interpret(CInstr instr) {
|
|||
}
|
||||
#endif
|
||||
case C_JR: {
|
||||
if (instr.encoding() & (C_JALR ^ C_JR)) {
|
||||
if ((instr.encoding() & (C_JALR ^ C_JR)) != 0) {
|
||||
if ((instr.rs1() == ZR) && (instr.rs2() == ZR)) {
|
||||
InterpretEBREAK(instr);
|
||||
} else if (instr.rs2() == ZR) {
|
||||
|
|
|
@ -69,4 +69,4 @@ uword Simulator::FunctionForRedirect(uword redirect) {
|
|||
|
||||
#endif // !defined(USING_SIMULATOR)
|
||||
|
||||
#endif // defined TARGET_ARCH_RISCV
|
||||
#endif // defined TARGET_ARCH_X64
|
||||
|
|
Loading…
Reference in a new issue