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[vm] Enable clang-tidy for arm, arm64, riscv64, product, release, precompiler.

Browse source 
TEST=ci
Change-Id: I319c932a6f4b6e18d7e53b66d69702bf017e4b93
Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/313060
Commit-Queue: Ryan Macnak <rmacnak@google.com>
Reviewed-by: Alexander Aprelev <aam@google.com>
This commit is contained in:
Ryan Macnak 2023-07-11 15:13:58 +00:00 committed by Commit Queue
parent 80a6670d5d
commit 453fce9e77
13 changed files with 127 additions and 80 deletions
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2
runtime/bin/reference_counting.h
View file

@ -7,6 +7,8 @@
#include <atomic>
#include "platform/assert.h"
namespace dart {
namespace bin {

104
runtime/tools/run_clang_tidy.dart
View file

@ -35,6 +35,13 @@ Future<void> generatePerfettoBuildFlags() async {
const String clangTidy = './buildtools/linux-x64/clang/bin/clang-tidy';
List<String> compilerFlagsForFile(String filepath) {
String arch = "X64";
if (filepath.contains("_arm.")) arch = "ARM";
if (filepath.contains("_arm64.")) arch = "ARM64";
if (filepath.contains("_riscv.")) arch = "RISCV64";
// Skipping IA32 because it neither has a simulator nor works with crossword
// and the host architecture is fixed.
final flags = <String>[
'-Iruntime',
'-Ithird_party',
@ -43,9 +50,7 @@ List<String> compilerFlagsForFile(String filepath) {
'-Ithird_party/perfetto/include',
'-Ithird_party/zlib',
'-Iout/DebugX64/gen/third_party/perfetto/build_config',
'-DTARGET_ARCH_X64',
'-DDEBUG',
'-DDART_TARGET_OS_LINUX',
'-DTARGET_ARCH_$arch',
'-DTESTING',
'-std=c++17',
'-x',
@ -54,13 +59,6 @@ List<String> compilerFlagsForFile(String filepath) {
return flags;
}
Future<ProcessResult> runClangTidyOn(String filepath) async {
// The `runtime/.clang-tidy` file has the enabled checks in it.
final args = <String>['-quiet', filepath, '--']
..addAll(compilerFlagsForFile(filepath));
return await Process.run(clangTidy, args);
}
final pool = new Pool(max(1, Platform.numberOfProcessors ~/ 2));
// Exclude running the linter on those files.
@ -84,6 +82,8 @@ final Set<String> excludedFiles = Set<String>.from([
'runtime/bin/namespace_linux.h',
'runtime/bin/namespace_macos.h',
'runtime/bin/namespace_win.h',
'runtime/bin/platform_macos.h',
'runtime/bin/platform_macos_cocoa.h',
'runtime/bin/socket_base_android.h',
'runtime/bin/socket_base_fuchsia.h',
'runtime/bin/socket_base_linux.h',
@ -133,9 +133,10 @@ final Set<String> excludedFiles = Set<String>.from([
'runtime/vm/os_thread_macos.h',
'runtime/vm/os_thread_win.h',
'runtime/vm/regexp_assembler_bytecode_inl.h',
'runtime/vm/simulator_arm64.h',
'runtime/vm/simulator_arm.h',
'runtime/vm/simulator_arm64.h',
'runtime/vm/simulator_riscv.h',
'runtime/vm/simulator_x64.h',
'runtime/vm/stack_frame_arm.h',
'runtime/vm/stack_frame_arm64.h',
'runtime/vm/stack_frame_ia32.h',
@ -148,6 +149,32 @@ final Set<String> excludedFiles = Set<String>.from([
'runtime/vm/compiler/backend/locations_helpers_arm.h',
]);
final defineSets = [
[
'-DDEBUG',
],
[
'-DNDEBUG',
],
[
'-DNDEBUG',
'-DPRODUCT',
],
[
'-DDART_PRECOMPILER',
'-DDEBUG',
],
[
'-DDART_PRECOMPILER',
'-DNDEBUG',
],
[
'-DDART_PRECOMPILER',
'-DNDEBUG',
'-DPRODUCT',
],
];
main(List<String> files) async {
await generatePerfettoBuildFlags();
@ -156,32 +183,39 @@ main(List<String> files) async {
files = files.where((filepath) => !excludedFiles.contains(filepath)).toList();
// Analyze the [files] in parallel.
await Future.wait(files.map((String filepath) async {
final processResult =
await pool.withResource(() => runClangTidyOn(filepath));
for (List<String> defines in defineSets) {
await Future.wait(files.map((String filepath) async {
// The `runtime/.clang-tidy` file has the enabled checks in it.
final args = <String>['-quiet', filepath, '--']
..addAll(compilerFlagsForFile(filepath))
..addAll(defines);
final processResult =
await pool.withResource(() => Process.run(clangTidy, args));
final int exitCode = processResult.exitCode;
final String stdout = processResult.stdout.trim();
final String stderr = processResult.stderr.trim();
final int exitCode = processResult.exitCode;
final String stdout = processResult.stdout.trim();
final String stderr = processResult.stderr.trim();
if (exitCode != 0 || stdout.isNotEmpty) {
if (!isFirstFailure) {
print('');
print('--------------------------------------------------------------');
print('');
if (exitCode != 0 || stdout.isNotEmpty) {
if (!isFirstFailure) {
print('');
print('------------------------------------------------------------');
print('');
}
isFirstFailure = false;
}
isFirstFailure = false;
}
if (exitCode != 0) {
print('exit-code: $exitCode');
print('stdout:');
print('${stdout}');
print('stderr:');
print('${stderr}');
} else if (stdout.isNotEmpty) {
// The actual lints go to stdout.
print(stdout);
}
}));
if (exitCode != 0) {
print('command: $clangTidy ${args.join(" ")}');
print('exit-code: $exitCode');
print('stdout:');
print('${stdout}');
print('stderr:');
print('${stderr}');
} else if (stdout.isNotEmpty) {
// The actual lints go to stdout.
print(stdout);
}
}));
}
}

1
runtime/vm/bitfield.h
View file

@ -7,6 +7,7 @@
#include <type_traits>
#include "platform/assert.h"
#include "platform/atomic.h"
#include "platform/globals.h"
#include "platform/thread_sanitizer.h"

12
runtime/vm/compiler/assembler/disassembler_arm.cc
View file

@ -1061,13 +1061,13 @@ void ARMDecoder::DecodeType6(Instr* instr) {
}
} else if (instr->IsVFPMultipleLoadStore()) {
if (instr->HasL()) { // vldm
if (instr->Bit(8)) { // vldmd
if (instr->Bit(8) != 0) { // vldmd
Format(instr, "vldmd'cond'pu 'rn'w, 'dlist");
} else { // vldms
Format(instr, "vldms'cond'pu 'rn'w, 'slist");
}
} else { // vstm
if (instr->Bit(8)) { // vstmd
if (instr->Bit(8) != 0) { // vstmd
Format(instr, "vstmd'cond'pu 'rn'w, 'dlist");
} else { // vstms
Format(instr, "vstms'cond'pu 'rn'w, 'slist");
@ -1388,11 +1388,11 @@ void ARMDecoder::DecodeSIMDDataProcessing(Instr* instr) {
(instr->Bits(20, 2) == 3) && (instr->Bits(23, 2) == 3) &&
(instr->Bit(7) == 0)) {
int32_t imm4 = instr->Bits(16, 4);
if (imm4 & 1) {
if ((imm4 & 1) != 0) {
Format(instr, "vdupb 'qd, 'dm['imm4_vdup]");
} else if (imm4 & 2) {
} else if ((imm4 & 2) != 0) {
Format(instr, "vduph 'qd, 'dm['imm4_vdup]");
} else if (imm4 & 4) {
} else if ((imm4 & 4) != 0) {
Format(instr, "vdupw 'qd, 'dm['imm4_vdup]");
} else {
Unknown(instr);
@ -1506,7 +1506,7 @@ void Disassembler::DecodeInstruction(char* hex_buffer,
decoder.InstructionDecode(pc);
int32_t instruction_bits = Instr::At(pc)->InstructionBits();
Utils::SNPrint(hex_buffer, hex_size, "%08x", instruction_bits);
if (out_instr_size) {
if (out_instr_size != nullptr) {
*out_instr_size = Instr::kInstrSize;
}

20
runtime/vm/compiler/assembler/disassembler_arm64.cc
View file

@ -380,13 +380,13 @@ int ARM64Decoder::FormatOption(Instr* instr, const char* format) {
ASSERT(STRING_STARTS_WITH(format, "csz"));
const int32_t imm5 = instr->Bits(16, 5);
char const* typ = "??";
if (imm5 & 0x1) {
if ((imm5 & 0x1) != 0) {
typ = "b";
} else if (imm5 & 0x2) {
} else if ((imm5 & 0x2) != 0) {
typ = "h";
} else if (imm5 & 0x4) {
} else if ((imm5 & 0x4) != 0) {
typ = "s";
} else if (imm5 & 0x8) {
} else if ((imm5 & 0x8) != 0) {
typ = "d";
}
buffer_pos_ += Utils::SNPrint(current_position_in_buffer(),
@ -484,13 +484,13 @@ int ARM64Decoder::FormatOption(Instr* instr, const char* format) {
shift = 1;
}
int32_t idx = -1;
if (imm5 & 0x1) {
if ((imm5 & 0x1) != 0) {
idx = imm >> shift;
} else if (imm5 & 0x2) {
} else if ((imm5 & 0x2) != 0) {
idx = imm >> (shift + 1);
} else if (imm5 & 0x4) {
} else if ((imm5 & 0x4) != 0) {
idx = imm >> (shift + 2);
} else if (imm5 & 0x8) {
} else if ((imm5 & 0x8) != 0) {
idx = imm >> (shift + 3);
}
buffer_pos_ += Utils::SNPrint(current_position_in_buffer(),
@ -783,7 +783,7 @@ void ARM64Decoder::DecodeLoadRegLiteral(Instr* instr) {
(instr->Bits(24, 3) != 0)) {
Unknown(instr);
}
if (instr->Bit(30)) {
if (instr->Bit(30) != 0) {
Format(instr, "ldrx 'rt, 'pcldr");
} else {
Format(instr, "ldrw 'rt, 'pcldr");
@ -1663,7 +1663,7 @@ void Disassembler::DecodeInstruction(char* hex_buffer,
decoder.InstructionDecode(pc);
int32_t instruction_bits = Instr::At(pc)->InstructionBits();
Utils::SNPrint(hex_buffer, hex_size, "%08x", instruction_bits);
if (out_instr_size) {
if (out_instr_size != nullptr) {
*out_instr_size = Instr::kInstrSize;
}

4
runtime/vm/compiler/assembler/disassembler_riscv.cc
View file

@ -259,7 +259,7 @@ void RISCVDisassembler::DisassembleInstruction(CInstr instr) {
break;
#endif
case C_JR:
if (instr.encoding() & (C_JALR ^ C_JR)) {
if ((instr.encoding() & (C_JALR ^ C_JR)) != 0) {
if ((instr.rs1() == ZR) && (instr.rs2() == ZR)) {
Print("ebreak", instr, RV_C);
} else if (instr.rs2() == ZR) {
@ -1788,7 +1788,7 @@ void Disassembler::DecodeInstruction(char* hex_buffer,
Utils::SNPrint(hex_buffer, hex_size, "%08x",
LoadUnaligned(reinterpret_cast<uint32_t*>(pc)));
}
if (out_instr_size) {
if (out_instr_size != nullptr) {
*out_instr_size = instr_size;
}

16
runtime/vm/constants_riscv.h
View file

@ -932,7 +932,9 @@ const intptr_t kReleaseShift = 25;
const intptr_t kAcquireShift = 26;
#define DEFINE_REG_ENCODING(type, name, shift) \
inline uint32_t Is##name(type r) { return static_cast<uint32_t>(r) < 32; } \
inline bool Is##name(type r) { \
return static_cast<uint32_t>(r) < 32; \
} \
inline uint32_t Encode##name(type r) { \
ASSERT(Is##name(r)); \
return static_cast<uint32_t>(r) << shift; \
@ -951,7 +953,9 @@ DEFINE_REG_ENCODING(FRegister, FRs3, 27)
#undef DEFINE_REG_ENCODING
#define DEFINE_FUNCT_ENCODING(type, name, shift, mask) \
inline uint32_t Is##name(type f) { return (f & mask) == f; } \
inline bool Is##name(type f) { \
return (f & mask) == f; \
} \
inline uint32_t Encode##name(type f) { \
ASSERT(Is##name(f)); \
return f << shift; \
@ -1125,7 +1129,9 @@ class Instr {
};
#define DEFINE_REG_ENCODING(type, name, shift) \
inline uint32_t Is##name(type r) { return static_cast<uint32_t>(r) < 32; } \
inline bool Is##name(type r) { \
return static_cast<uint32_t>(r) < 32; \
} \
inline uint32_t Encode##name(type r) { \
ASSERT(Is##name(r)); \
return static_cast<uint32_t>(r) << shift; \
@ -1135,7 +1141,9 @@ class Instr {
}
#define DEFINE_REG_PRIME_ENCODING(type, name, shift) \
inline uint32_t Is##name(type r) { return (r >= 8) && (r < 16); } \
inline bool Is##name(type r) { \
return (r >= 8) && (r < 16); \
} \
inline uint32_t Encode##name(type r) { \
ASSERT(Is##name(r)); \
return (static_cast<uint32_t>(r) & 7) << shift; \

2
runtime/vm/dwarf.cc
View file

@ -606,7 +606,7 @@ class LineNumberProgramWriter {
intptr_t file_ = 1;
intptr_t line_ = 1;
intptr_t column_ = 0;
intptr_t end_sequence_ = false;
bool end_sequence_ = false;
// Other info not stored in the state machine registers.
intptr_t label_ = 0;

3
runtime/vm/heap/sampler.h
View file

@ -10,7 +10,8 @@
#include <atomic>
#include "include/dart_api.h"
#include "vm/allocation.h"
#include "vm/globals.h"
namespace dart {

6
runtime/vm/instructions_arm64.cc
View file

@ -310,8 +310,8 @@ bool DecodeLoadObjectFromPoolOrThread(uword pc, const Code& code, Object* obj) {
}
if (instr->RnField() == instr->RtField()) {
Instr* add = Instr::At(pc - Instr::kInstrSize);
if (add->IsAddSubImmOp() && add->SFField() && (instr->Bit(22) == 1) &&
(add->RdField() == add->RtField())) {
if (add->IsAddSubImmOp() && (add->SFField() != 0) &&
(instr->Bit(22) == 1) && (add->RdField() == add->RtField())) {
offset = (add->Imm12Field() << 12) + offset;
if (add->RnField() == PP) {
// PP is untagged on ARM64.
@ -326,7 +326,7 @@ bool DecodeLoadObjectFromPoolOrThread(uword pc, const Code& code, Object* obj) {
// TODO(rmacnak): Loads with offsets beyond 24 bits.
}
if (instr->IsAddSubImmOp() && instr->SFField() &&
if (instr->IsAddSubImmOp() && (instr->SFField() != 0) &&
(instr->RnField() == NULL_REG)) {
uint32_t imm = (instr->Bit(22) == 1) ? (instr->Imm12Field() << 12)
: (instr->Imm12Field());

33
runtime/vm/simulator_arm64.cc
View file

@ -676,10 +676,10 @@ void SimulatorDebugger::Debug() {
}
} else if (strcmp(cmd, "flags") == 0) {
OS::PrintErr("APSR: ");
OS::PrintErr("N flag: %d; ", sim_->n_flag_);
OS::PrintErr("Z flag: %d; ", sim_->z_flag_);
OS::PrintErr("C flag: %d; ", sim_->c_flag_);
OS::PrintErr("V flag: %d\n", sim_->v_flag_);
OS::PrintErr("N flag: %d; ", static_cast<int>(sim_->n_flag_));
OS::PrintErr("Z flag: %d; ", static_cast<int>(sim_->z_flag_));
OS::PrintErr("C flag: %d; ", static_cast<int>(sim_->c_flag_));
OS::PrintErr("V flag: %d\n", static_cast<int>(sim_->v_flag_));
} else if (strcmp(cmd, "unstop") == 0) {
intptr_t stop_pc = sim_->get_pc() - Instr::kInstrSize;
Instr* stop_instr = reinterpret_cast<Instr*>(stop_pc);
@ -1355,7 +1355,7 @@ void Simulator::DecodeMoveWide(Instr* instr) {
const int64_t shifted_imm = static_cast<int64_t>(instr->Imm16Field())
<< shift;
if (instr->SFField()) {
if (instr->SFField() != 0) {
if (instr->Bits(29, 2) == 0) {
// Format(instr, "movn'sf 'rd, 'imm16 'hw");
set_register(instr, rd, ~shifted_imm, instr->RdMode());
@ -1399,7 +1399,7 @@ void Simulator::DecodeAddSubImm(Instr* instr) {
const Register rn = instr->RnField();
uint32_t imm = (instr->Bit(22) == 1) ? (instr->Imm12Field() << 12)
: (instr->Imm12Field());
if (instr->SFField()) {
if (instr->SFField() != 0) {
// 64-bit add.
const uint64_t rn_val = get_register(rn, instr->RnMode());
const uint64_t alu_out = addition ? (rn_val + imm) : (rn_val - imm);
@ -2155,7 +2155,7 @@ void Simulator::DecodeLoadStoreRegPair(Instr* instr) {
// SIMD/FP.
const VRegister vt = instr->VtField();
const VRegister vt2 = instr->Vt2Field();
if (instr->Bit(22)) {
if (instr->Bit(22) != 0) {
// Format(instr, "ldp 'vt, 'vt2, 'memop");
switch (size) {
case 4:
@ -2215,7 +2215,7 @@ void Simulator::DecodeLoadStoreRegPair(Instr* instr) {
// Integer.
const Register rt = instr->RtField();
const Register rt2 = instr->Rt2Field();
if (instr->Bit(22)) {
if (instr->Bit(22) != 0) {
// Format(instr, "ldp'sf 'rt, 'rt2, 'memop");
const bool is_signed = instr->Bit(30) == 1;
int64_t val1 = 0; // Sign extend into an int64_t.
@ -2274,7 +2274,7 @@ void Simulator::DecodeLoadRegLiteral(Instr* instr) {
const int64_t pc = reinterpret_cast<int64_t>(instr);
const int64_t address = pc + off;
const int64_t val = ReadX(address, instr);
if (instr->Bit(30)) {
if (instr->Bit(30) != 0) {
// Format(instr, "ldrx 'rt, 'pcldr");
set_register(instr, rt, val, R31IsZR);
} else {
@ -2487,7 +2487,8 @@ int64_t Simulator::ExtendOperand(uint8_t reg_size,
int64_t Simulator::DecodeShiftExtendOperand(Instr* instr) {
const Register rm = instr->RmField();
const int64_t rm_val = get_register(rm, R31IsZR);
const uint8_t size = instr->SFField() ? kXRegSizeInBits : kWRegSizeInBits;
const uint8_t size =
instr->SFField() != 0 ? kXRegSizeInBits : kWRegSizeInBits;
if (instr->IsShift()) {
const Shift shift_type = instr->ShiftTypeField();
const uint8_t shift_amount = instr->Imm6Field();
@ -2509,7 +2510,7 @@ void Simulator::DecodeAddSubShiftExt(Instr* instr) {
const Register rd = instr->RdField();
const Register rn = instr->RnField();
const uint64_t rm_val = DecodeShiftExtendOperand(instr);
if (instr->SFField()) {
if (instr->SFField() != 0) {
// 64-bit add.
const uint64_t rn_val = get_register(rn, instr->RnMode());
const uint64_t alu_out = rn_val + (addition ? rm_val : -rm_val);
@ -2550,7 +2551,7 @@ void Simulator::DecodeAddSubWithCarry(Instr* instr) {
const uint64_t rm_val64 = get_register(rm, R31IsZR);
uint32_t rm_val32 = get_wregister(rm, R31IsZR);
const uint32_t carry_in = c_flag_ ? 1 : 0;
if (instr->SFField()) {
if (instr->SFField() != 0) {
// 64-bit add.
const uint64_t alu_out =
rn_val64 + (addition ? rm_val64 : ~rm_val64) + carry_in;
@ -2965,19 +2966,19 @@ void Simulator::DecodeSIMDCopy(Instr* instr) {
int32_t idx4 = -1;
int32_t idx5 = -1;
int32_t element_bytes;
if (imm5 & 0x1) {
if ((imm5 & 0x1) != 0) {
idx4 = imm4;
idx5 = imm5 >> 1;
element_bytes = 1;
} else if (imm5 & 0x2) {
} else if ((imm5 & 0x2) != 0) {
idx4 = imm4 >> 1;
idx5 = imm5 >> 2;
element_bytes = 2;
} else if (imm5 & 0x4) {
} else if ((imm5 & 0x4) != 0) {
idx4 = imm4 >> 2;
idx5 = imm5 >> 3;
element_bytes = 4;
} else if (imm5 & 0x8) {
} else if ((imm5 & 0x8) != 0) {
idx4 = imm4 >> 3;
idx5 = imm5 >> 4;
element_bytes = 8;

2
runtime/vm/simulator_riscv.cc
View file

@ -687,7 +687,7 @@ void Simulator::Interpret(CInstr instr) {
}
#endif
case C_JR: {
if (instr.encoding() & (C_JALR ^ C_JR)) {
if ((instr.encoding() & (C_JALR ^ C_JR)) != 0) {
if ((instr.rs1() == ZR) && (instr.rs2() == ZR)) {
InterpretEBREAK(instr);
} else if (instr.rs2() == ZR) {

2
runtime/vm/simulator_x64.cc
View file

@ -69,4 +69,4 @@ uword Simulator::FunctionForRedirect(uword redirect) {
#endif // !defined(USING_SIMULATOR)
#endif // defined TARGET_ARCH_RISCV
#endif // defined TARGET_ARCH_X64