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[vm/sim/simd] Fix vmin/vmax implementation on simulator.
minss/maxss used by simulator 0.0==-0.0, which is inconsistent with arm native instructions. Fixes https://github.com/dart-lang/sdk/issues/48988 Addresses https://github.com/dart-lang/sdk/issues/40426 TEST=ci Change-Id: I9d88d89e342bb543b1e90fdbe3c7aa8303353dab Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/244320 Reviewed-by: Ryan Macnak <rmacnak@google.com> Commit-Queue: Alexander Aprelev <aam@google.com>
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@ -195,7 +195,8 @@ DEFINE_NATIVE_ENTRY(Float32x4_clamp, 0, 3) {
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float _w;
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// ARM semantics are different from X86/X64 at an instruction level. Ensure
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// that we match the semantics of the architecture in the C version.
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#if defined(TARGET_ARCH_IA32) || defined(TARGET_ARCH_X64)
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#if defined(TARGET_ARCH_IA32) || defined(TARGET_ARCH_X64) || \
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defined(USING_SIMULATOR)
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_x = self.x() < hi.x() ? self.x() : hi.x();
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_y = self.y() < hi.y() ? self.y() : hi.y();
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_z = self.z() < hi.z() ? self.z() : hi.z();
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@ -741,7 +742,8 @@ DEFINE_NATIVE_ENTRY(Float64x2_clamp, 0, 3) {
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// ARM semantics are different from X86/X64 at an instruction level. Ensure
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// that we match the semantics of the architecture in the C version.
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#if defined(TARGET_ARCH_IA32) || defined(TARGET_ARCH_X64)
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#if defined(TARGET_ARCH_IA32) || defined(TARGET_ARCH_X64) || \
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defined(USING_SIMULATOR)
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_x = self.x() < hi.x() ? self.x() : hi.x();
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_y = self.y() < hi.y() ? self.y() : hi.y();
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_x = lo.x() < _x ? _x : lo.x();
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@ -6732,6 +6732,25 @@ ASSEMBLER_TEST_RUN(Vcged, test) {
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"ret\n");
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}
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// Verify that vmaxs(-0.0, 0.0) = 0.0
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ASSEMBLER_TEST_GENERATE(Vmaxs_zero, assembler) {
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__ veor(V1, V1, V1);
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__ vnegd(V2, V1);
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__ vmaxs(V0, V2, V1);
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__ ret();
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}
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ASSEMBLER_TEST_RUN(Vmaxs_zero, test) {
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typedef double (*DoubleReturn)() DART_UNUSED;
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double d = EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry());
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EXPECT_EQ(true, !signbit(d) && (d == 0.0));
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EXPECT_DISASSEMBLY(
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"veor v1, v1, v1\n"
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"vnegd v2, v1\n"
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"vmaxs v0, v2, v1\n"
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"ret\n");
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}
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ASSEMBLER_TEST_GENERATE(Vmaxs, assembler) {
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__ LoadDImmediate(V0, 10.5);
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__ LoadDImmediate(V1, 10.0);
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@ -6791,6 +6810,25 @@ ASSEMBLER_TEST_RUN(Vmaxs, test) {
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"ret\n");
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}
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// Verify that vmaxd(-0.0, 0.0) = 0.0
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ASSEMBLER_TEST_GENERATE(Vmaxd_zero, assembler) {
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__ veor(V1, V1, V1);
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__ vnegd(V2, V1);
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__ vmaxd(V0, V2, V1);
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__ ret();
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}
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ASSEMBLER_TEST_RUN(Vmaxd_zero, test) {
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typedef double (*DoubleReturn)() DART_UNUSED;
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double d = EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry());
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EXPECT_EQ(true, !signbit(d) && (d == 0.0));
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EXPECT_DISASSEMBLY(
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"veor v1, v1, v1\n"
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"vnegd v2, v1\n"
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"vmaxd v0, v2, v1\n"
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"ret\n");
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}
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ASSEMBLER_TEST_GENERATE(Vmaxd, assembler) {
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__ LoadDImmediate(V0, 21.0);
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__ LoadDImmediate(V1, 20.5);
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@ -6826,6 +6864,26 @@ ASSEMBLER_TEST_RUN(Vmaxd, test) {
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"ret\n");
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}
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// Verify that vmins(-0.0, 0.0) = -0.0
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ASSEMBLER_TEST_GENERATE(Vmins_zero, assembler) {
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__ veor(V1, V1, V1);
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__ vnegd(V2, V1);
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__ vmins(V0, V1, V2);
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__ ret();
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}
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ASSEMBLER_TEST_RUN(Vmins_zero, test) {
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typedef double (*DoubleReturn)() DART_UNUSED;
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double d = EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry());
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fprintf(stderr, "d: %f\n", d);
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EXPECT_EQ(true, signbit(d) && (d == 0.0));
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EXPECT_DISASSEMBLY(
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"veor v1, v1, v1\n"
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"vnegd v2, v1\n"
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"vmins v0, v1, v2\n"
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"ret\n");
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}
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ASSEMBLER_TEST_GENERATE(Vmins, assembler) {
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__ LoadDImmediate(V0, 10.5);
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__ LoadDImmediate(V1, 11.0);
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@ -6885,6 +6943,26 @@ ASSEMBLER_TEST_RUN(Vmins, test) {
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"ret\n");
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}
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// Verify that vmind(-0.0, 0.0) = -0.0
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ASSEMBLER_TEST_GENERATE(Vmind_zero, assembler) {
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__ veor(V1, V1, V1);
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__ vnegd(V2, V1);
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__ vmind(V0, V1, V2);
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__ ret();
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}
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ASSEMBLER_TEST_RUN(Vmind_zero, test) {
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typedef double (*DoubleReturn)() DART_UNUSED;
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double d = EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry());
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fprintf(stderr, "d: %f\n", d);
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EXPECT_EQ(true, signbit(d) && (d == 0.0));
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EXPECT_DISASSEMBLY(
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"veor v1, v1, v1\n"
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"vnegd v2, v1\n"
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"vmind v0, v1, v2\n"
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"ret\n");
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}
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ASSEMBLER_TEST_GENERATE(Vmind, assembler) {
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__ LoadDImmediate(V0, 21.0);
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__ LoadDImmediate(V1, 21.5);
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@ -3409,6 +3409,25 @@ ASSEMBLER_TEST_RUN(Vcgtqs, test) {
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}
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}
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// Verify that vmins(-0.0, 0.0) = -0.0
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ASSEMBLER_TEST_GENERATE(Vminqs_zero, assembler) {
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if (TargetCPUFeatures::neon_supported()) {
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__ veorq(Q1, Q1, Q1);
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__ vnegqs(Q2, Q1);
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__ vminqs(Q0, Q1, Q2);
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}
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__ Ret();
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}
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ASSEMBLER_TEST_RUN(Vminqs_zero, test) {
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EXPECT(test != NULL);
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if (TargetCPUFeatures::neon_supported()) {
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typedef int (*Tst)() DART_UNUSED;
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float res = EXECUTE_TEST_CODE_FLOAT(Tst, test->entry());
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EXPECT_EQ(true, signbit(res) && (res == 0.0));
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}
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}
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ASSEMBLER_TEST_GENERATE(Vminqs, assembler) {
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if (TargetCPUFeatures::neon_supported()) {
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__ LoadSImmediate(S0, 1.0);
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@ -3441,6 +3460,25 @@ ASSEMBLER_TEST_RUN(Vminqs, test) {
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}
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}
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ASSEMBLER_TEST_GENERATE(Vmaxqs_zero, assembler) {
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if (TargetCPUFeatures::neon_supported()) {
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__ veorq(Q1, Q1, Q1);
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__ vnegqs(Q2, Q1);
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__ vmaxqs(Q0, Q2, Q1);
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}
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__ Ret();
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}
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// Verify that vmaxqs(-0.0, 0.0) = 0.0
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ASSEMBLER_TEST_RUN(Vmaxqs_zero, test) {
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EXPECT(test != NULL);
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if (TargetCPUFeatures::neon_supported()) {
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typedef int (*Tst)() DART_UNUSED;
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float res = EXECUTE_TEST_CODE_FLOAT(Tst, test->entry());
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EXPECT_EQ(true, !signbit(res) && (res == 0.0));
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}
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}
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ASSEMBLER_TEST_GENERATE(Vmaxqs, assembler) {
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if (TargetCPUFeatures::neon_supported()) {
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__ LoadSImmediate(S0, 1.0);
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@ -2893,6 +2893,22 @@ static void simd_value_swap(simd_value_t* s1,
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s2->data_[i2].u = tmp;
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}
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static float vminf(float f1, float f2) {
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if (f1 == f2) {
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// take care of (-0.0) < 0.0, (they are equal according to minss)
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return signbit(f1) ? f1 : f2;
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}
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return f1 > f2 ? f2 : f1;
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}
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static float vmaxf(float f1, float f2) {
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if (f1 == f2) {
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// take care of (-0.0) < 0.0, (they are equal according to minss)
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return signbit(f1) ? f2 : f1;
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}
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return f1 < f2 ? f2 : f1;
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}
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void Simulator::DecodeSIMDDataProcessing(Instr* instr) {
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ASSERT(instr->ConditionField() == kSpecialCondition);
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@ -3118,13 +3134,13 @@ void Simulator::DecodeSIMDDataProcessing(Instr* instr) {
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(instr->Bits(20, 2) == 2) && (instr->Bits(23, 2) == 0)) {
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// Format(instr, "vminqs 'qd, 'qn, 'qm");
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for (int i = 0; i < 4; i++) {
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s8d.data_[i].f = fminf(s8n.data_[i].f, s8m.data_[i].f);
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s8d.data_[i].f = vminf(s8n.data_[i].f, s8m.data_[i].f);
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}
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} else if ((instr->Bits(8, 4) == 15) && (instr->Bit(4) == 0) &&
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(instr->Bits(20, 2) == 0) && (instr->Bits(23, 2) == 0)) {
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// Format(instr, "vmaxqs 'qd, 'qn, 'qm");
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for (int i = 0; i < 4; i++) {
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s8d.data_[i].f = fmaxf(s8n.data_[i].f, s8m.data_[i].f);
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s8d.data_[i].f = vmaxf(s8n.data_[i].f, s8m.data_[i].f);
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}
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} else if ((instr->Bits(8, 4) == 7) && (instr->Bit(4) == 0) &&
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(instr->Bits(20, 2) == 3) && (instr->Bits(23, 2) == 3) &&
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@ -3003,6 +3003,38 @@ void Simulator::DecodeSIMDCopy(Instr* instr) {
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}
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}
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static float vminf(float f1, float f2) {
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if (f1 == f2) {
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// take care of (-0.0) < 0.0, (they are equal according to minss)
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return signbit(f1) ? f1 : f2;
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}
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return f1 > f2 ? f2 : f1;
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}
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static float vmaxf(float f1, float f2) {
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if (f1 == f2) {
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// take care of (-0.0) < 0.0, (they are equal according to minss)
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return signbit(f1) ? f2 : f1;
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}
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return f1 < f2 ? f2 : f1;
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}
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static double vmind(double f1, double f2) {
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if (f1 == f2) {
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// take care of (-0.0) < 0.0, (they are equal according to minss)
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return signbit(f1) ? f1 : f2;
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}
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return f1 > f2 ? f2 : f1;
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}
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static double vmaxd(double f1, double f2) {
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if (f1 == f2) {
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// take care of (-0.0) < 0.0, (they are equal according to minss)
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return signbit(f1) ? f2 : f1;
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}
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return f1 < f2 ? f2 : f1;
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}
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void Simulator::DecodeSIMDThreeSame(Instr* instr) {
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const int Q = instr->Bit(30);
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const int U = instr->Bit(29);
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@ -3069,11 +3101,11 @@ void Simulator::DecodeSIMDThreeSame(Instr* instr) {
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} else if ((U == 0) && (opcode == 0x1e)) {
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if (instr->Bit(23) == 1) {
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// Format(instr, "vmin'vsz 'vd, 'vn, 'vm");
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const float m = fminf(vn_flt, vm_flt);
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const float m = vminf(vn_flt, vm_flt);
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res = bit_cast<int32_t, float>(m);
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} else {
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// Format(instr, "vmax'vsz 'vd, 'vn, 'vm");
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const float m = fmaxf(vn_flt, vm_flt);
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const float m = vmaxf(vn_flt, vm_flt);
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res = bit_cast<int32_t, float>(m);
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}
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} else if ((U == 0) && (opcode == 0x1f)) {
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@ -3143,11 +3175,11 @@ void Simulator::DecodeSIMDThreeSame(Instr* instr) {
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} else if ((U == 0) && (opcode == 0x1e)) {
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if (instr->Bit(23) == 1) {
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// Format(instr, "vmin'vsz 'vd, 'vn, 'vm");
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const double m = fmin(vn_dbl, vm_dbl);
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const double m = vmind(vn_dbl, vm_dbl);
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res = bit_cast<int64_t, double>(m);
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} else {
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// Format(instr, "vmax'vsz 'vd, 'vn, 'vm");
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const double m = fmax(vn_dbl, vm_dbl);
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const double m = vmaxd(vn_dbl, vm_dbl);
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res = bit_cast<int64_t, double>(m);
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}
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} else {
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@ -1,7 +1,8 @@
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// Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
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// for details. All rights reserved. Use of this source code is governed by a
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// BSD-style license that can be found in the LICENSE file.
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// VMOptions=--optimization-counter-threshold=10 --no-background-compilation
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// VMOptions=--intrinsify --optimization-counter-threshold=10 --no-background-compilation
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// VMOptions=--no-intrinsify --optimization-counter-threshold=10 --no-background-compilation
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// @dart = 2.9
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