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[vm] Speed up the RISC-V simulator.

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TEST=ci
Change-Id: I8ddba01117d21fcf915d77bc06765a0d576f55ca
Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/248682
Reviewed-by: Alexander Markov <alexmarkov@google.com>
Commit-Queue: Ryan Macnak <rmacnak@google.com>
This commit is contained in:
Ryan Macnak 2022-06-16 17:56:02 +00:00 committed by Commit Bot
parent 31c49c4fd8
commit 01a7f207c3
2 changed files with 45 additions and 0 deletions
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43
runtime/vm/simulator_riscv.cc
View file

@ -383,6 +383,28 @@ int64_t Simulator::Call(intx_t entry,
}
void Simulator::Execute() {
if (LIKELY(FLAG_trace_sim_after == ULLONG_MAX)) {
ExecuteNoTrace();
} else {
ExecuteTrace();
}
}
void Simulator::ExecuteNoTrace() {
while (pc_ != kEndSimulatingPC) {
uint16_t parcel = *reinterpret_cast<uint16_t*>(pc_);
if (IsCInstruction(parcel)) {
CInstr instr(parcel);
Interpret(instr);
} else {
Instr instr(*reinterpret_cast<uint32_t*>(pc_));
Interpret(instr);
}
instret_++;
}
}
void Simulator::ExecuteTrace() {
while (pc_ != kEndSimulatingPC) {
uint16_t parcel = *reinterpret_cast<uint16_t*>(pc_);
if (IsCInstruction(parcel)) {
@ -482,6 +504,7 @@ void Simulator::PrintStack() {
}
}
DART_FORCE_INLINE
void Simulator::Interpret(Instr instr) {
switch (instr.opcode()) {
case LUI:
@ -552,6 +575,7 @@ void Simulator::Interpret(Instr instr) {
}
}
DART_FORCE_INLINE
void Simulator::Interpret(CInstr instr) {
switch (instr.opcode()) {
case C_LWSP: {
@ -812,21 +836,25 @@ void Simulator::Interpret(CInstr instr) {
pc_ += instr.length();
}
DART_FORCE_INLINE
void Simulator::InterpretLUI(Instr instr) {
set_xreg(instr.rd(), sign_extend(instr.utype_imm()));
pc_ += instr.length();
}
DART_FORCE_INLINE
void Simulator::InterpretAUIPC(Instr instr) {
set_xreg(instr.rd(), pc_ + sign_extend(instr.utype_imm()));
pc_ += instr.length();
}
DART_FORCE_INLINE
void Simulator::InterpretJAL(Instr instr) {
set_xreg(instr.rd(), pc_ + instr.length());
pc_ += sign_extend(instr.jtype_imm());
}
DART_FORCE_INLINE
void Simulator::InterpretJALR(Instr instr) {
uintx_t base = get_xreg(instr.rs1());
uintx_t offset = static_cast<uintx_t>(instr.itype_imm());
@ -834,6 +862,7 @@ void Simulator::InterpretJALR(Instr instr) {
pc_ = base + offset;
}
DART_FORCE_INLINE
void Simulator::InterpretBRANCH(Instr instr) {
switch (instr.funct3()) {
case BEQ:
@ -887,6 +916,7 @@ void Simulator::InterpretBRANCH(Instr instr) {
}
}
DART_FORCE_INLINE
void Simulator::InterpretLOAD(Instr instr) {
uintx_t addr = get_xreg(instr.rs1()) + instr.itype_imm();
switch (instr.funct3()) {
@ -919,6 +949,7 @@ void Simulator::InterpretLOAD(Instr instr) {
pc_ += instr.length();
}
DART_FORCE_INLINE
void Simulator::InterpretLOADFP(Instr instr) {
uintx_t addr = get_xreg(instr.rs1()) + instr.itype_imm();
switch (instr.funct3()) {
@ -934,6 +965,7 @@ void Simulator::InterpretLOADFP(Instr instr) {
pc_ += instr.length();
}
DART_FORCE_INLINE
void Simulator::InterpretSTORE(Instr instr) {
uintx_t addr = get_xreg(instr.rs1()) + instr.stype_imm();
switch (instr.funct3()) {
@ -957,6 +989,7 @@ void Simulator::InterpretSTORE(Instr instr) {
pc_ += instr.length();
}
DART_FORCE_INLINE
void Simulator::InterpretSTOREFP(Instr instr) {
uintx_t addr = get_xreg(instr.rs1()) + instr.stype_imm();
switch (instr.funct3()) {
@ -972,6 +1005,7 @@ void Simulator::InterpretSTOREFP(Instr instr) {
pc_ += instr.length();
}
DART_FORCE_INLINE
void Simulator::InterpretOPIMM(Instr instr) {
switch (instr.funct3()) {
case ADDI:
@ -1018,6 +1052,7 @@ void Simulator::InterpretOPIMM(Instr instr) {
pc_ += instr.length();
}
DART_FORCE_INLINE
void Simulator::InterpretOPIMM32(Instr instr) {
switch (instr.funct3()) {
case ADDI: {
@ -1049,6 +1084,7 @@ void Simulator::InterpretOPIMM32(Instr instr) {
pc_ += instr.length();
}
DART_FORCE_INLINE
void Simulator::InterpretOP(Instr instr) {
switch (instr.funct7()) {
case 0:
@ -1065,6 +1101,7 @@ void Simulator::InterpretOP(Instr instr) {
}
}
DART_FORCE_INLINE
void Simulator::InterpretOP_0(Instr instr) {
switch (instr.funct3()) {
case ADD:
@ -1247,6 +1284,7 @@ static uint32_t remuw(uint32_t a, uint32_t b) {
}
#endif // XLEN >= 64
DART_FORCE_INLINE
void Simulator::InterpretOP_MULDIV(Instr instr) {
switch (instr.funct3()) {
case MUL:
@ -1280,6 +1318,7 @@ void Simulator::InterpretOP_MULDIV(Instr instr) {
pc_ += instr.length();
}
DART_FORCE_INLINE
void Simulator::InterpretOP_SUB(Instr instr) {
switch (instr.funct3()) {
case ADD:
@ -1296,6 +1335,7 @@ void Simulator::InterpretOP_SUB(Instr instr) {
pc_ += instr.length();
}
DART_FORCE_INLINE
void Simulator::InterpretOP32(Instr instr) {
switch (instr.funct7()) {
#if XLEN >= 64
@ -1314,6 +1354,7 @@ void Simulator::InterpretOP32(Instr instr) {
}
}
DART_FORCE_INLINE
void Simulator::InterpretOP32_0(Instr instr) {
switch (instr.funct3()) {
#if XLEN >= 64
@ -1342,6 +1383,7 @@ void Simulator::InterpretOP32_0(Instr instr) {
pc_ += instr.length();
}
DART_FORCE_INLINE
void Simulator::InterpretOP32_SUB(Instr instr) {
switch (instr.funct3()) {
#if XLEN >= 64
@ -1364,6 +1406,7 @@ void Simulator::InterpretOP32_SUB(Instr instr) {
pc_ += instr.length();
}
DART_FORCE_INLINE
void Simulator::InterpretOP32_MULDIV(Instr instr) {
switch (instr.funct3()) {
#if XLEN >= 64

2
runtime/vm/simulator_riscv.h
View file

@ -325,6 +325,8 @@ class Simulator {
// Executes RISC-V instructions until the PC reaches kEndSimulatingPC.
void Execute();
void ExecuteNoTrace();
void ExecuteTrace();
// Returns true if tracing of executed instructions is enabled.
bool IsTracingExecution() const;