2013-01-18 21:44:58 +00:00
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// Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
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// for details. All rights reserved. Use of this source code is governed by a
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// BSD-style license that can be found in the LICENSE file.
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#include "vm/globals.h" // Needed here to get TARGET_ARCH_MIPS.
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#if defined(TARGET_ARCH_MIPS)
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2013-03-08 21:16:46 +00:00
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#include "vm/constants_mips.h"
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2013-06-17 15:58:31 +00:00
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#include "vm/cpu.h"
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2013-01-18 21:44:58 +00:00
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#include "vm/instructions.h"
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#include "vm/object.h"
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namespace dart {
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CallPattern::CallPattern(uword pc, const Code& code)
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: object_pool_(ObjectPool::Handle(code.GetObjectPool())),
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end_(pc),
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ic_data_load_end_(0),
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target_address_pool_index_(-1),
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ic_data_(ICData::Handle()) {
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ASSERT(code.ContainsInstructionAt(pc));
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2014-01-29 23:07:50 +00:00
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// Last instruction: jalr RA, T9(=R25).
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ASSERT(*(reinterpret_cast<uword*>(end_) - 2) == 0x0320f809);
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Register reg;
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// The end of the pattern is the instruction after the delay slot of the jalr.
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ic_data_load_end_ =
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InstructionPattern::DecodeLoadWordFromPool(end_ - (2 * Instr::kInstrSize),
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®,
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&target_address_pool_index_);
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ASSERT(reg == T9);
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}
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// Decodes a load sequence ending at 'end' (the last instruction of the load
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// sequence is the instruction before the one at end). Returns a pointer to
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// the first instruction in the sequence. Returns the register being loaded
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// and the loaded object in the output parameters 'reg' and 'obj'
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// respectively.
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uword InstructionPattern::DecodeLoadObject(uword end,
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const ObjectPool& object_pool,
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Register* reg,
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Object* obj) {
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uword start = 0;
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Instr* instr = Instr::At(end - Instr::kInstrSize);
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if (instr->OpcodeField() == LW) {
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intptr_t index = 0;
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start = DecodeLoadWordFromPool(end, reg, &index);
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*obj = object_pool.ObjectAt(index);
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} else {
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intptr_t value = 0;
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start = DecodeLoadWordImmediate(end, reg, &value);
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*obj = reinterpret_cast<RawObject*>(value);
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}
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return start;
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}
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// Decodes a load sequence ending at 'end' (the last instruction of the load
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// sequence is the instruction before the one at end). Returns a pointer to
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// the first instruction in the sequence. Returns the register being loaded
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// and the loaded immediate value in the output parameters 'reg' and 'value'
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// respectively.
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uword InstructionPattern::DecodeLoadWordImmediate(uword end,
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Register* reg,
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intptr_t* value) {
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// The pattern is a fixed size, but match backwards for uniformity with
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// DecodeLoadWordFromPool.
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uword start = end - Instr::kInstrSize;
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Instr* instr = Instr::At(start);
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intptr_t imm = 0;
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ASSERT(instr->OpcodeField() == ORI);
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imm = instr->UImmField();
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*reg = instr->RtField();
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start -= Instr::kInstrSize;
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instr = Instr::At(start);
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ASSERT(instr->OpcodeField() == LUI);
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ASSERT(instr->RtField() == *reg);
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imm |= (instr->UImmField() << 16);
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*value = imm;
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return start;
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}
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// Decodes a load sequence ending at 'end' (the last instruction of the load
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// sequence is the instruction before the one at end). Returns a pointer to
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// the first instruction in the sequence. Returns the register being loaded
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// and the index in the pool being read from in the output parameters 'reg'
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// and 'index' respectively.
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uword InstructionPattern::DecodeLoadWordFromPool(uword end,
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Register* reg,
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intptr_t* index) {
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uword start = end - Instr::kInstrSize;
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Instr* instr = Instr::At(start);
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intptr_t offset = 0;
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if ((instr->OpcodeField() == LW) && (instr->RsField() == PP)) {
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offset = instr->SImmField();
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*reg = instr->RtField();
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} else {
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ASSERT(instr->OpcodeField() == LW);
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offset = instr->SImmField();
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*reg = instr->RtField();
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start -= Instr::kInstrSize;
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instr = Instr::At(start);
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ASSERT(instr->OpcodeField() == SPECIAL);
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ASSERT(instr->FunctionField() == ADDU);
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ASSERT(instr->RdField() == *reg);
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ASSERT(instr->RsField() == *reg);
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ASSERT(instr->RtField() == PP);
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start -= Instr::kInstrSize;
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instr = Instr::At(start);
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ASSERT(instr->OpcodeField() == LUI);
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ASSERT(instr->RtField() == *reg);
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// Offset is signed, so add the upper 16 bits.
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offset += (instr->UImmField() << 16);
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}
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*index = ObjectPool::IndexFromOffset(offset);
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return start;
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}
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RawICData* CallPattern::IcData() {
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if (ic_data_.IsNull()) {
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Register reg;
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InstructionPattern::DecodeLoadObject(ic_data_load_end_,
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object_pool_,
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®,
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&ic_data_);
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ASSERT(reg == S5);
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}
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return ic_data_.raw();
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}
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uword CallPattern::TargetAddress() const {
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return object_pool_.RawValueAt(target_address_pool_index_);
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}
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void CallPattern::SetTargetAddress(uword target_address) const {
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object_pool_.SetRawValueAt(target_address_pool_index_, target_address);
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// No need to flush the instruction cache, since the code is not modified.
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}
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2013-06-17 15:58:31 +00:00
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void CallPattern::InsertAt(uword pc, uword target_address) {
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Instr* lui = Instr::At(pc + (0 * Instr::kInstrSize));
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Instr* ori = Instr::At(pc + (1 * Instr::kInstrSize));
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Instr* jr = Instr::At(pc + (2 * Instr::kInstrSize));
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Instr* nop = Instr::At(pc + (3 * Instr::kInstrSize));
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uint16_t target_lo = target_address & 0xffff;
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uint16_t target_hi = target_address >> 16;
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2014-01-29 23:07:50 +00:00
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lui->SetImmInstrBits(LUI, ZR, T9, target_hi);
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ori->SetImmInstrBits(ORI, T9, T9, target_lo);
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jr->SetSpecialInstrBits(JALR, T9, ZR, RA);
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nop->SetInstructionBits(Instr::kNopInstruction);
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ASSERT(kFixedLengthInBytes == 4 * Instr::kInstrSize);
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CPU::FlushICache(pc, kFixedLengthInBytes);
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}
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2013-09-09 15:39:26 +00:00
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JumpPattern::JumpPattern(uword pc, const Code& code) : pc_(pc) { }
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bool JumpPattern::IsValid() const {
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Instr* lui = Instr::At(pc_ + (0 * Instr::kInstrSize));
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Instr* ori = Instr::At(pc_ + (1 * Instr::kInstrSize));
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Instr* jr = Instr::At(pc_ + (2 * Instr::kInstrSize));
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Instr* nop = Instr::At(pc_ + (3 * Instr::kInstrSize));
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return (lui->OpcodeField() == LUI) &&
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(ori->OpcodeField() == ORI) &&
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(jr->OpcodeField() == SPECIAL) &&
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(jr->FunctionField() == JR) &&
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(nop->InstructionBits() == Instr::kNopInstruction);
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}
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uword JumpPattern::TargetAddress() const {
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Instr* lui = Instr::At(pc_ + (0 * Instr::kInstrSize));
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Instr* ori = Instr::At(pc_ + (1 * Instr::kInstrSize));
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const uint16_t target_lo = ori->UImmField();
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const uint16_t target_hi = lui->UImmField();
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return (target_hi << 16) | target_lo;
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}
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2013-03-08 21:16:46 +00:00
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void JumpPattern::SetTargetAddress(uword target_address) const {
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Instr* lui = Instr::At(pc_ + (0 * Instr::kInstrSize));
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Instr* ori = Instr::At(pc_ + (1 * Instr::kInstrSize));
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const int32_t lui_bits = lui->InstructionBits();
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const int32_t ori_bits = ori->InstructionBits();
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const uint16_t target_lo = target_address & 0xffff;
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const uint16_t target_hi = target_address >> 16;
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lui->SetInstructionBits((lui_bits & 0xffff0000) | target_hi);
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ori->SetInstructionBits((ori_bits & 0xffff0000) | target_lo);
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}
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2015-02-26 18:48:55 +00:00
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ReturnPattern::ReturnPattern(uword pc)
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: pc_(pc) {
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}
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bool ReturnPattern::IsValid() const {
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Instr* jr = Instr::At(pc_);
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return (jr->OpcodeField() == SPECIAL) &&
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(jr->FunctionField() == JR) &&
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(jr->RsField() == RA);
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}
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2013-01-18 21:44:58 +00:00
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} // namespace dart
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#endif // defined TARGET_ARCH_MIPS
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