2014-04-02 17:39:32 +00:00
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// Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file
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// for details. All rights reserved. Use of this source code is governed by a
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// BSD-style license that can be found in the LICENSE file.
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// Classes that describe assembly patterns as used by inline caches.
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2016-10-26 07:26:03 +00:00
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#ifndef RUNTIME_VM_INSTRUCTIONS_ARM64_H_
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#define RUNTIME_VM_INSTRUCTIONS_ARM64_H_
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2014-04-02 17:39:32 +00:00
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2016-10-26 07:26:03 +00:00
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#ifndef RUNTIME_VM_INSTRUCTIONS_H_
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2014-04-02 17:39:32 +00:00
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#error Do not include instructions_arm64.h directly; use instructions.h instead.
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#endif
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2019-01-25 16:45:13 +00:00
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#include "vm/allocation.h"
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#include "vm/compiler/assembler/assembler.h"
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#include "vm/constants.h"
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#include "vm/native_function.h"
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2014-04-02 17:39:32 +00:00
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namespace dart {
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2019-01-25 16:45:13 +00:00
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class Code;
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class ICData;
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class ObjectPool;
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class RawCode;
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class RawICData;
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class RawObject;
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2014-04-02 17:39:32 +00:00
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class InstructionPattern : public AllStatic {
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public:
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// Decodes a load sequence ending at 'end' (the last instruction of the
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// load sequence is the instruction before the one at end). Returns the
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// address of the first instruction in the sequence. Returns the register
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// being loaded and the loaded object in the output parameters 'reg' and
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// 'obj' respectively.
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static uword DecodeLoadObject(uword end,
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const ObjectPool& object_pool,
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Register* reg,
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Object* obj);
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// Decodes a load sequence ending at 'end' (the last instruction of the
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// load sequence is the instruction before the one at end). Returns the
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// address of the first instruction in the sequence. Returns the register
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// being loaded and the loaded immediate value in the output parameters
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// 'reg' and 'value' respectively.
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static uword DecodeLoadWordImmediate(uword end,
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Register* reg,
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intptr_t* value);
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// Decodes a load sequence ending at 'end' (the last instruction of the
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// load sequence is the instruction before the one at end). Returns the
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// address of the first instruction in the sequence. Returns the register
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// being loaded and the index in the pool being read from in the output
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// parameters 'reg' and 'index' respectively.
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2018-06-11 21:33:05 +00:00
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// IMPORANT: When generating code loading values from pool on ARM64 use
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// LoadWordFromPool macro instruction instead of emitting direct load.
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// The macro instruction takes care of pool offsets that can't be
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// encoded as immediates.
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static uword DecodeLoadWordFromPool(uword end,
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Register* reg,
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intptr_t* index);
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2018-09-11 10:02:04 +00:00
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// Decodes a load sequence ending at 'end' (the last instruction of the
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// load sequence is the instruction before the one at end). Returns the
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// address of the first instruction in the sequence. Returns the registers
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// being loaded and the index in the pool being read from in the output
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// parameters 'reg1', 'reg2' and 'index' respectively.
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// IMPORANT: When generating code loading values from pool on ARM64 use
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// LoadDoubleWordFromPool macro instruction instead of emitting direct load.
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// The macro instruction takes care of pool offsets that can't be
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// encoded as immediates.
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static uword DecodeLoadDoubleWordFromPool(uword end,
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Register* reg1,
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Register* reg2,
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intptr_t* index);
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// Encodes a load sequence ending at 'end'. Encodes a fixed length two
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// instruction load from the pool pointer in PP using the destination
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// register reg as a temporary for the base address.
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static void EncodeLoadWordFromPoolFixed(uword end, int32_t offset);
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};
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class CallPattern : public ValueObject {
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public:
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CallPattern(uword pc, const Code& code);
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RawCode* TargetCode() const;
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void SetTargetCode(const Code& target) const;
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private:
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const ObjectPool& object_pool_;
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intptr_t target_code_pool_index_;
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DISALLOW_COPY_AND_ASSIGN(CallPattern);
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};
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2019-06-12 21:56:53 +00:00
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class ICCallPattern : public ValueObject {
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public:
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ICCallPattern(uword pc, const Code& caller_code);
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RawObject* Data() const;
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void SetData(const Object& data) const;
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RawCode* TargetCode() const;
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void SetTargetCode(const Code& target) const;
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private:
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const ObjectPool& object_pool_;
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intptr_t target_pool_index_;
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intptr_t data_pool_index_;
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DISALLOW_COPY_AND_ASSIGN(ICCallPattern);
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};
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2015-08-21 09:37:50 +00:00
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class NativeCallPattern : public ValueObject {
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public:
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NativeCallPattern(uword pc, const Code& code);
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RawCode* target() const;
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void set_target(const Code& target) const;
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NativeFunction native_function() const;
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void set_native_function(NativeFunction target) const;
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private:
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const ObjectPool& object_pool_;
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uword end_;
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intptr_t native_function_pool_index_;
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intptr_t target_code_pool_index_;
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DISALLOW_COPY_AND_ASSIGN(NativeCallPattern);
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};
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2016-08-12 18:18:35 +00:00
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// Instance call that can switch between a direct monomorphic call, an IC call,
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// and a megamorphic call.
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// load guarded cid load ICData load MegamorphicCache
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// load monomorphic target <-> load ICLookup stub -> load MMLookup stub
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// call target.entry call stub.entry call stub.entry
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class SwitchableCallPatternBase : public ValueObject {
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public:
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explicit SwitchableCallPatternBase(const Code& code);
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RawObject* data() const;
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void SetData(const Object& data) const;
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protected:
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const ObjectPool& object_pool_;
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intptr_t data_pool_index_;
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intptr_t target_pool_index_;
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private:
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DISALLOW_COPY_AND_ASSIGN(SwitchableCallPatternBase);
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};
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// See [SwitchableCallBase] for a switchable calls in general.
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//
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// The target slot is always a [Code] object: Either the code of the
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// monomorphic function or a stub code.
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class SwitchableCallPattern : public SwitchableCallPatternBase {
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public:
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SwitchableCallPattern(uword pc, const Code& code);
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RawCode* target() const;
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void SetTarget(const Code& target) const;
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private:
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DISALLOW_COPY_AND_ASSIGN(SwitchableCallPattern);
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};
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2018-12-14 16:11:53 +00:00
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// See [SwitchableCallBase] for a switchable calls in general.
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//
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// The target slot is always a direct entrypoint address: Either the entry point
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// of the monomorphic function or a stub entry point.
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class BareSwitchableCallPattern : public SwitchableCallPatternBase {
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public:
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BareSwitchableCallPattern(uword pc, const Code& code);
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RawCode* target() const;
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void SetTarget(const Code& target) const;
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private:
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DISALLOW_COPY_AND_ASSIGN(BareSwitchableCallPattern);
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};
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2015-02-26 18:48:55 +00:00
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class ReturnPattern : public ValueObject {
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public:
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explicit ReturnPattern(uword pc);
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// bx_lr = 1.
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static const int kLengthInBytes = 1 * Instr::kInstrSize;
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2016-11-08 21:54:47 +00:00
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int pattern_length_in_bytes() const { return kLengthInBytes; }
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bool IsValid() const;
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private:
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const uword pc_;
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};
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2018-11-01 12:34:42 +00:00
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class PcRelativeCallPattern : public ValueObject {
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public:
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// 26 bit signed integer which will get multiplied by 4.
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static const intptr_t kLowerCallingRange = -(1 << 27);
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static const intptr_t kUpperCallingRange = (1 << 27) - 1;
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explicit PcRelativeCallPattern(uword pc) : pc_(pc) {}
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static const int kLengthInBytes = 1 * Instr::kInstrSize;
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int32_t distance() {
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#if !defined(DART_PRECOMPILED_RUNTIME)
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return compiler::Assembler::DecodeImm26BranchOffset(
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*reinterpret_cast<int32_t*>(pc_));
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#else
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UNREACHABLE();
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return 0;
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#endif
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}
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void set_distance(int32_t distance) {
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#if !defined(DART_PRECOMPILED_RUNTIME)
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int32_t* word = reinterpret_cast<int32_t*>(pc_);
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*word = compiler::Assembler::EncodeImm26BranchOffset(distance, *word);
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#else
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UNREACHABLE();
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#endif
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}
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bool IsValid() const;
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private:
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uword pc_;
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};
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2019-01-17 12:32:38 +00:00
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// Instruction pattern for a tail call to a signed 32-bit PC-relative offset
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//
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// The AOT compiler can emit PC-relative calls. If the destination of such a
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// call is not in range for the "bl <offset>" instruction, the AOT compiler will
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// emit a trampoline which is in range. That trampoline will then tail-call to
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// the final destination (also via PC-relative offset, but it supports a full
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// signed 32-bit offset).
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//
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// The pattern of the trampoline looks like:
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//
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// adr TMP, #lower16 (same as TMP = PC + #lower16)
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// movz TMP2, #higher16 lsl 16
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// add TMP, TMP, TMP2, SXTW
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// br TMP
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//
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class PcRelativeTrampolineJumpPattern : public ValueObject {
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public:
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explicit PcRelativeTrampolineJumpPattern(uword pattern_start)
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: pattern_start_(pattern_start) {
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USE(pattern_start_);
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}
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static const int kLengthInBytes = 4 * Instr::kInstrSize;
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void Initialize();
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int32_t distance();
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void set_distance(int32_t distance);
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bool IsValid() const;
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private:
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// This offset must be applied to account for the fact that
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// a) the actual "branch" is only in the 3rd instruction
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// b) when reading the PC it reports current instruction + 8
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static const intptr_t kDistanceOffset = -5 * Instr::kInstrSize;
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// adr TMP, #lower16 (same as TMP = PC + #lower16)
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static const uint32_t kAdrEncoding = (1 << 28) | (TMP << kRdShift);
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// movz TMP2, #higher16 lsl 16
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static const uint32_t kMovzEncoding = MOVZ | (1 << kHWShift) | TMP2;
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// add TMP, TMP, TMP2, SXTW
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static const uint32_t kAddTmpTmp2 = 0x8b31c210;
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// br TMP
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static const uint32_t kJumpEncoding = BR | (TMP << kRnShift);
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uword pattern_start_;
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};
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2014-04-02 17:39:32 +00:00
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} // namespace dart
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2016-10-26 07:26:03 +00:00
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#endif // RUNTIME_VM_INSTRUCTIONS_ARM64_H_
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