2019-06-03 22:14:16 +00:00
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#!/usr/bin/env bash
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# Copyright (c) 2019, the Dart project authors. Please see the AUTHORS file
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# for details. All rights reserved. Use of this source code is governed by a
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# BSD-style license that can be found in the LICENSE file.
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set -e
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FILE="runtime/vm/compiler/runtime_offsets_extracted.h"
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# Make sure we're running in the SDK directory.
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if ! test -f "$FILE"; then
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echo "Couldn't find $FILE"
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echo "Make sure to run this script from the Dart SDK directory."
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exit 1
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fi
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TEMP="${FILE}.temp"
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2020-01-24 22:03:05 +00:00
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TEMP_HEADER="${FILE}.header.temp"
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TEMP_JIT="${FILE}.jit.temp"
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TEMP_AOT="${FILE}.aot.temp"
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2020-10-06 07:59:33 +00:00
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# Remove old temp files if the previous run was stopped prematurely.
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rm -rf "${TEMP}" "${TEMP_HEADER}" "${TEMP_JIT}" "${TEMP_AOT}"
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# We're regenerating the file, but we want to keep all the comments etc at the
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2021-02-02 19:26:34 +00:00
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# top of the file. So just delete everything after the first "#if ".
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2020-10-06 07:59:33 +00:00
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LINE=$(grep "#if " "$FILE" -n | head -n 1 | sed "s/^\([0-9]*\):.*/\1/")
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2020-01-24 22:03:05 +00:00
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head -n $(expr $LINE - 1) "$FILE" >"$TEMP_HEADER"
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2019-06-03 22:14:16 +00:00
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# Run offsets_extractor for every architecture and append the results.
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run() {
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2021-11-29 09:34:23 +00:00
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tools/build.py --mode=$1 --arch=$2 offsets_extractor offsets_extractor_precompiled_runtime
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2020-01-24 22:03:05 +00:00
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echo "" >>"$TEMP_JIT"
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2020-01-27 15:59:56 +00:00
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out/$3/offsets_extractor >>"$TEMP_JIT"
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2020-01-24 22:03:05 +00:00
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echo "" >>"$TEMP_AOT"
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2020-01-27 15:59:56 +00:00
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out/$3/offsets_extractor_precompiled_runtime >>"$TEMP_AOT"
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2019-06-03 22:14:16 +00:00
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}
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2020-01-27 15:59:56 +00:00
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echo "" >>"$TEMP_JIT"
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echo "" >>"$TEMP_AOT"
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echo "#if !defined(PRODUCT)" >>"$TEMP_JIT"
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echo "#if !defined(PRODUCT)" >>"$TEMP_AOT"
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run release simarm ReleaseSIMARM
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run release x64 ReleaseX64
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run release ia32 ReleaseIA32
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run release simarm64 ReleaseSIMARM64
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2021-02-04 17:44:37 +00:00
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run release x64c ReleaseX64C
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run release simarm64c ReleaseSIMARM64C
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[vm] Support RISC-V.
Implements a backend targeting RV32GC and RV64GC, based on Linux standardizing around GC. The assembler is written to make it easy to disable usage of C, but because the sizes of some instruction sequences are compile-time constants, an additional build configuration would need to be defined to make use of it.
The assembler and disassembler cover every RV32/64GC instruction. The simulator covers all instructions except accessing CSRs and the floating point state accessible through such, include accrued exceptions and dynamic rounding mode.
Quirks:
- RISC-V is a compare-and-branch architecture, but some existing "architecture-independent" parts of the Dart compiler assume a condition code architecture. To avoid rewriting these parts, we use a peephole in the assembler to map to compare-and-branch. See Assembler::BranchIf. Luckily nothing depended on taking multiple branches on the same condition code set.
- There are no hardware overflow checks, so we must use Hacker's Delight style software checks. Often these are very cheap: if the sign of one operand is known, a single branch is needed.
- The ranges of RISC-V branches and jumps are such that we use 3 levels of generation for forward branches, instead of the 2 levels of near and far branches used on ARM[64]. Nearly all code is handled by the first two levels with 20-bits of range, with enormous regex matchers triggering the third level that uses aupic+jalr to get 32-bits of range.
- For PC-relative calls in AOT, we always generate auipc+jalr pairs with 32-bits of range, so we never generate trampolines.
- Only a subset of registers are available in some compressed instructions, so we assign the most popular uses to these registers. In particular, THR, TMP[2], CODE and PP. This has the effect of assigning CODE and PP to volatile registers in the C calling convention, whereas they are assigned preserved registers on the other architectures. As on ARM64, PP is untagged; this is so short indices can be accessed with a compressed instruction.
- There are no push or pop instructions, so combining pushes and pops is preferred so we can update SP once.
- The C calling convention has a strongly aligned stack, but unlike on ARM64 we don't need to use an alternate stack pointer. The author ensured language was added to the RISC-V psABI making the OS responsible for realigning the stack pointer for signal handlers, allowing Dart to leave the stack pointer misaligned from the C calling convention's point of view until a foreign call.
- We don't bother with the link register tracking done on ARM[64]. Instead we make use of an alternate link register to avoid inline spilling in the write barrier.
Unimplemented:
- non-trivial FFI cases
- Compressed pointers - No intention to implement.
- Unboxed SIMD - We might make use of the V extension registers when the V extension is ratified.
- BigInt intrinsics
TEST=existing tests for IL level, new tests for assembler/disassembler/simulator
Bug: https://github.com/dart-lang/sdk/issues/38587
Bug: https://github.com/dart-lang/sdk/issues/48164
Change-Id: I991d1df4be5bf55efec5371b767b332d37dfa3e0
Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/217289
Reviewed-by: Alexander Markov <alexmarkov@google.com>
Reviewed-by: Daco Harkes <dacoharkes@google.com>
Reviewed-by: Slava Egorov <vegorov@google.com>
Commit-Queue: Ryan Macnak <rmacnak@google.com>
2022-01-20 00:57:57 +00:00
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run release simriscv32 ReleaseSIMRISCV32
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run release simriscv64 ReleaseSIMRISCV64
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2020-01-27 15:59:56 +00:00
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echo "" >>"$TEMP_JIT"
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echo "" >>"$TEMP_AOT"
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echo "#else // !defined(PRODUCT)" >>"$TEMP_JIT"
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echo "#else // !defined(PRODUCT)" >>"$TEMP_AOT"
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run product simarm ProductSIMARM
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run product x64 ProductX64
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run product ia32 ProductIA32
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run product simarm64 ProductSIMARM64
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2021-02-04 17:44:37 +00:00
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run product x64c ProductX64C
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run product simarm64c ProductSIMARM64C
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[vm] Support RISC-V.
Implements a backend targeting RV32GC and RV64GC, based on Linux standardizing around GC. The assembler is written to make it easy to disable usage of C, but because the sizes of some instruction sequences are compile-time constants, an additional build configuration would need to be defined to make use of it.
The assembler and disassembler cover every RV32/64GC instruction. The simulator covers all instructions except accessing CSRs and the floating point state accessible through such, include accrued exceptions and dynamic rounding mode.
Quirks:
- RISC-V is a compare-and-branch architecture, but some existing "architecture-independent" parts of the Dart compiler assume a condition code architecture. To avoid rewriting these parts, we use a peephole in the assembler to map to compare-and-branch. See Assembler::BranchIf. Luckily nothing depended on taking multiple branches on the same condition code set.
- There are no hardware overflow checks, so we must use Hacker's Delight style software checks. Often these are very cheap: if the sign of one operand is known, a single branch is needed.
- The ranges of RISC-V branches and jumps are such that we use 3 levels of generation for forward branches, instead of the 2 levels of near and far branches used on ARM[64]. Nearly all code is handled by the first two levels with 20-bits of range, with enormous regex matchers triggering the third level that uses aupic+jalr to get 32-bits of range.
- For PC-relative calls in AOT, we always generate auipc+jalr pairs with 32-bits of range, so we never generate trampolines.
- Only a subset of registers are available in some compressed instructions, so we assign the most popular uses to these registers. In particular, THR, TMP[2], CODE and PP. This has the effect of assigning CODE and PP to volatile registers in the C calling convention, whereas they are assigned preserved registers on the other architectures. As on ARM64, PP is untagged; this is so short indices can be accessed with a compressed instruction.
- There are no push or pop instructions, so combining pushes and pops is preferred so we can update SP once.
- The C calling convention has a strongly aligned stack, but unlike on ARM64 we don't need to use an alternate stack pointer. The author ensured language was added to the RISC-V psABI making the OS responsible for realigning the stack pointer for signal handlers, allowing Dart to leave the stack pointer misaligned from the C calling convention's point of view until a foreign call.
- We don't bother with the link register tracking done on ARM[64]. Instead we make use of an alternate link register to avoid inline spilling in the write barrier.
Unimplemented:
- non-trivial FFI cases
- Compressed pointers - No intention to implement.
- Unboxed SIMD - We might make use of the V extension registers when the V extension is ratified.
- BigInt intrinsics
TEST=existing tests for IL level, new tests for assembler/disassembler/simulator
Bug: https://github.com/dart-lang/sdk/issues/38587
Bug: https://github.com/dart-lang/sdk/issues/48164
Change-Id: I991d1df4be5bf55efec5371b767b332d37dfa3e0
Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/217289
Reviewed-by: Alexander Markov <alexmarkov@google.com>
Reviewed-by: Daco Harkes <dacoharkes@google.com>
Reviewed-by: Slava Egorov <vegorov@google.com>
Commit-Queue: Ryan Macnak <rmacnak@google.com>
2022-01-20 00:57:57 +00:00
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run product simriscv32 ProductSIMRISCV32
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run product simriscv64 ProductSIMRISCV64
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2020-01-27 15:59:56 +00:00
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echo "" >>"$TEMP_JIT"
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echo "" >>"$TEMP_AOT"
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echo "#endif // !defined(PRODUCT)" >>"$TEMP_JIT"
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echo "#endif // !defined(PRODUCT)" >>"$TEMP_AOT"
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2019-06-03 22:14:16 +00:00
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2020-01-24 22:03:05 +00:00
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cat $TEMP_HEADER >>"$TEMP"
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cat $TEMP_JIT >>"$TEMP"
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cat $TEMP_AOT >>"$TEMP"
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2019-06-03 22:14:16 +00:00
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echo "" >>"$TEMP"
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echo "#endif // RUNTIME_VM_COMPILER_RUNTIME_OFFSETS_EXTRACTED_H_" >>"$TEMP"
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mv "$TEMP" "$FILE"
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2020-01-27 15:59:56 +00:00
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# Cleanup.
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2019-06-03 22:14:16 +00:00
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git cl format "$FILE"
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2020-01-24 22:03:05 +00:00
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rm "$TEMP_HEADER"
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rm "$TEMP_JIT"
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rm "$TEMP_AOT"
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2019-06-03 22:14:16 +00:00
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echo -e "\n\nSuccessfully generated $FILE :)"
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