mirror of
https://github.com/python/cpython
synced 2024-11-02 12:22:35 +00:00
481 lines
16 KiB
C
481 lines
16 KiB
C
#ifdef _Py_JIT
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#include "Python.h"
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#include "pycore_abstract.h"
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#include "pycore_call.h"
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#include "pycore_ceval.h"
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#include "pycore_dict.h"
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#include "pycore_intrinsics.h"
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#include "pycore_long.h"
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#include "pycore_opcode_metadata.h"
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#include "pycore_opcode_utils.h"
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#include "pycore_optimizer.h"
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#include "pycore_pyerrors.h"
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#include "pycore_setobject.h"
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#include "pycore_sliceobject.h"
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#include "pycore_jit.h"
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// Memory management stuff: ////////////////////////////////////////////////////
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#ifndef MS_WINDOWS
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#include <sys/mman.h>
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#endif
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static size_t
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get_page_size(void)
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{
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#ifdef MS_WINDOWS
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SYSTEM_INFO si;
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GetSystemInfo(&si);
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return si.dwPageSize;
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#else
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return sysconf(_SC_PAGESIZE);
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#endif
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}
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static void
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jit_error(const char *message)
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{
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#ifdef MS_WINDOWS
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int hint = GetLastError();
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#else
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int hint = errno;
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#endif
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PyErr_Format(PyExc_RuntimeWarning, "JIT %s (%d)", message, hint);
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}
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static unsigned char *
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jit_alloc(size_t size)
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{
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assert(size);
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assert(size % get_page_size() == 0);
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#ifdef MS_WINDOWS
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int flags = MEM_COMMIT | MEM_RESERVE;
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unsigned char *memory = VirtualAlloc(NULL, size, flags, PAGE_READWRITE);
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int failed = memory == NULL;
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#else
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int flags = MAP_ANONYMOUS | MAP_PRIVATE;
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unsigned char *memory = mmap(NULL, size, PROT_READ | PROT_WRITE, flags, -1, 0);
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int failed = memory == MAP_FAILED;
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#endif
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if (failed) {
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jit_error("unable to allocate memory");
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return NULL;
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}
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return memory;
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}
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static int
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jit_free(unsigned char *memory, size_t size)
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{
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assert(size);
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assert(size % get_page_size() == 0);
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#ifdef MS_WINDOWS
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int failed = !VirtualFree(memory, 0, MEM_RELEASE);
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#else
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int failed = munmap(memory, size);
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#endif
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if (failed) {
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jit_error("unable to free memory");
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return -1;
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}
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return 0;
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}
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static int
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mark_executable(unsigned char *memory, size_t size)
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{
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if (size == 0) {
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return 0;
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}
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assert(size % get_page_size() == 0);
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// Do NOT ever leave the memory writable! Also, don't forget to flush the
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// i-cache (I cannot begin to tell you how horrible that is to debug):
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#ifdef MS_WINDOWS
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if (!FlushInstructionCache(GetCurrentProcess(), memory, size)) {
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jit_error("unable to flush instruction cache");
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return -1;
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}
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int old;
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int failed = !VirtualProtect(memory, size, PAGE_EXECUTE_READ, &old);
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#else
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__builtin___clear_cache((char *)memory, (char *)memory + size);
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int failed = mprotect(memory, size, PROT_EXEC | PROT_READ);
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#endif
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if (failed) {
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jit_error("unable to protect executable memory");
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return -1;
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}
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return 0;
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}
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// JIT compiler stuff: /////////////////////////////////////////////////////////
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// Warning! AArch64 requires you to get your hands dirty. These are your gloves:
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// value[value_start : value_start + len]
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static uint32_t
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get_bits(uint64_t value, uint8_t value_start, uint8_t width)
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{
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assert(width <= 32);
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return (value >> value_start) & ((1ULL << width) - 1);
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}
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// *loc[loc_start : loc_start + width] = value[value_start : value_start + width]
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static void
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set_bits(uint32_t *loc, uint8_t loc_start, uint64_t value, uint8_t value_start,
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uint8_t width)
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{
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assert(loc_start + width <= 32);
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// Clear the bits we're about to patch:
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*loc &= ~(((1ULL << width) - 1) << loc_start);
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assert(get_bits(*loc, loc_start, width) == 0);
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// Patch the bits:
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*loc |= get_bits(value, value_start, width) << loc_start;
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assert(get_bits(*loc, loc_start, width) == get_bits(value, value_start, width));
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}
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// See https://developer.arm.com/documentation/ddi0602/2023-09/Base-Instructions
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// for instruction encodings:
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#define IS_AARCH64_ADD_OR_SUB(I) (((I) & 0x11C00000) == 0x11000000)
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#define IS_AARCH64_ADRP(I) (((I) & 0x9F000000) == 0x90000000)
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#define IS_AARCH64_BRANCH(I) (((I) & 0x7C000000) == 0x14000000)
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#define IS_AARCH64_LDR_OR_STR(I) (((I) & 0x3B000000) == 0x39000000)
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#define IS_AARCH64_MOV(I) (((I) & 0x9F800000) == 0x92800000)
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// LLD is a great reference for performing relocations... just keep in
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// mind that Tools/jit/build.py does filtering and preprocessing for us!
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// Here's a good place to start for each platform:
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// - aarch64-apple-darwin:
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// - https://github.com/llvm/llvm-project/blob/main/lld/MachO/Arch/ARM64.cpp
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// - https://github.com/llvm/llvm-project/blob/main/lld/MachO/Arch/ARM64Common.cpp
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// - https://github.com/llvm/llvm-project/blob/main/lld/MachO/Arch/ARM64Common.h
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// - aarch64-pc-windows-msvc:
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// - https://github.com/llvm/llvm-project/blob/main/lld/COFF/Chunks.cpp
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// - aarch64-unknown-linux-gnu:
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// - https://github.com/llvm/llvm-project/blob/main/lld/ELF/Arch/AArch64.cpp
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// - i686-pc-windows-msvc:
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// - https://github.com/llvm/llvm-project/blob/main/lld/COFF/Chunks.cpp
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// - x86_64-apple-darwin:
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// - https://github.com/llvm/llvm-project/blob/main/lld/MachO/Arch/X86_64.cpp
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// - x86_64-pc-windows-msvc:
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// - https://github.com/llvm/llvm-project/blob/main/lld/COFF/Chunks.cpp
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// - x86_64-unknown-linux-gnu:
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// - https://github.com/llvm/llvm-project/blob/main/lld/ELF/Arch/X86_64.cpp
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// Many of these patches are "relaxing", meaning that they can rewrite the
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// code they're patching to be more efficient (like turning a 64-bit memory
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// load into a 32-bit immediate load). These patches have an "x" in their name.
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// Relative patches have an "r" in their name.
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// 32-bit absolute address.
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void
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patch_32(unsigned char *location, uint64_t value)
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{
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uint32_t *loc32 = (uint32_t *)location;
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// Check that we're not out of range of 32 unsigned bits:
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assert(value < (1ULL << 32));
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*loc32 = (uint32_t)value;
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}
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// 32-bit relative address.
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void
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patch_32r(unsigned char *location, uint64_t value)
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{
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uint32_t *loc32 = (uint32_t *)location;
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value -= (uintptr_t)location;
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// Check that we're not out of range of 32 signed bits:
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assert((int64_t)value >= -(1LL << 31));
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assert((int64_t)value < (1LL << 31));
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*loc32 = (uint32_t)value;
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}
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// 64-bit absolute address.
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void
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patch_64(unsigned char *location, uint64_t value)
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{
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uint64_t *loc64 = (uint64_t *)location;
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*loc64 = value;
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}
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// 12-bit low part of an absolute address. Pairs nicely with patch_aarch64_21r
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// (below).
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void
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patch_aarch64_12(unsigned char *location, uint64_t value)
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{
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uint32_t *loc32 = (uint32_t *)location;
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assert(IS_AARCH64_LDR_OR_STR(*loc32) || IS_AARCH64_ADD_OR_SUB(*loc32));
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// There might be an implicit shift encoded in the instruction:
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uint8_t shift = 0;
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if (IS_AARCH64_LDR_OR_STR(*loc32)) {
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shift = (uint8_t)get_bits(*loc32, 30, 2);
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// If both of these are set, the shift is supposed to be 4.
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// That's pretty weird, and it's never actually been observed...
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assert(get_bits(*loc32, 23, 1) == 0 || get_bits(*loc32, 26, 1) == 0);
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}
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value = get_bits(value, 0, 12);
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assert(get_bits(value, 0, shift) == 0);
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set_bits(loc32, 10, value, shift, 12);
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}
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// Relaxable 12-bit low part of an absolute address. Pairs nicely with
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// patch_aarch64_21rx (below).
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void
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patch_aarch64_12x(unsigned char *location, uint64_t value)
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{
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// This can *only* be relaxed if it occurs immediately before a matching
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// patch_aarch64_21rx. If that happens, the JIT build step will replace both
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// calls with a single call to patch_aarch64_33rx. Otherwise, we end up
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// here, and the instruction is patched normally:
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patch_aarch64_12(location, value);
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}
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// 16-bit low part of an absolute address.
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void
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patch_aarch64_16a(unsigned char *location, uint64_t value)
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{
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uint32_t *loc32 = (uint32_t *)location;
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assert(IS_AARCH64_MOV(*loc32));
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// Check the implicit shift (this is "part 0 of 3"):
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assert(get_bits(*loc32, 21, 2) == 0);
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set_bits(loc32, 5, value, 0, 16);
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}
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// 16-bit middle-low part of an absolute address.
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void
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patch_aarch64_16b(unsigned char *location, uint64_t value)
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{
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uint32_t *loc32 = (uint32_t *)location;
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assert(IS_AARCH64_MOV(*loc32));
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// Check the implicit shift (this is "part 1 of 3"):
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assert(get_bits(*loc32, 21, 2) == 1);
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set_bits(loc32, 5, value, 16, 16);
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}
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// 16-bit middle-high part of an absolute address.
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void
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patch_aarch64_16c(unsigned char *location, uint64_t value)
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{
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uint32_t *loc32 = (uint32_t *)location;
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assert(IS_AARCH64_MOV(*loc32));
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// Check the implicit shift (this is "part 2 of 3"):
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assert(get_bits(*loc32, 21, 2) == 2);
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set_bits(loc32, 5, value, 32, 16);
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}
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// 16-bit high part of an absolute address.
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void
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patch_aarch64_16d(unsigned char *location, uint64_t value)
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{
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uint32_t *loc32 = (uint32_t *)location;
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assert(IS_AARCH64_MOV(*loc32));
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// Check the implicit shift (this is "part 3 of 3"):
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assert(get_bits(*loc32, 21, 2) == 3);
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set_bits(loc32, 5, value, 48, 16);
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}
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// 21-bit count of pages between this page and an absolute address's page... I
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// know, I know, it's weird. Pairs nicely with patch_aarch64_12 (above).
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void
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patch_aarch64_21r(unsigned char *location, uint64_t value)
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{
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uint32_t *loc32 = (uint32_t *)location;
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value = (value >> 12) - ((uintptr_t)location >> 12);
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// Check that we're not out of range of 21 signed bits:
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assert((int64_t)value >= -(1 << 20));
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assert((int64_t)value < (1 << 20));
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// value[0:2] goes in loc[29:31]:
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set_bits(loc32, 29, value, 0, 2);
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// value[2:21] goes in loc[5:26]:
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set_bits(loc32, 5, value, 2, 19);
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}
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// Relaxable 21-bit count of pages between this page and an absolute address's
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// page. Pairs nicely with patch_aarch64_12x (above).
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void
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patch_aarch64_21rx(unsigned char *location, uint64_t value)
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{
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// This can *only* be relaxed if it occurs immediately before a matching
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// patch_aarch64_12x. If that happens, the JIT build step will replace both
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// calls with a single call to patch_aarch64_33rx. Otherwise, we end up
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// here, and the instruction is patched normally:
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patch_aarch64_21r(location, value);
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}
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// 28-bit relative branch.
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void
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patch_aarch64_26r(unsigned char *location, uint64_t value)
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{
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uint32_t *loc32 = (uint32_t *)location;
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assert(IS_AARCH64_BRANCH(*loc32));
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value -= (uintptr_t)location;
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// Check that we're not out of range of 28 signed bits:
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assert((int64_t)value >= -(1 << 27));
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assert((int64_t)value < (1 << 27));
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// Since instructions are 4-byte aligned, only use 26 bits:
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assert(get_bits(value, 0, 2) == 0);
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set_bits(loc32, 0, value, 2, 26);
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}
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// A pair of patch_aarch64_21rx and patch_aarch64_12x.
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void
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patch_aarch64_33rx(unsigned char *location, uint64_t value)
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{
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uint32_t *loc32 = (uint32_t *)location;
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// Try to relax the pair of GOT loads into an immediate value:
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assert(IS_AARCH64_ADRP(*loc32));
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unsigned char reg = get_bits(loc32[0], 0, 5);
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assert(IS_AARCH64_LDR_OR_STR(loc32[1]));
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// There should be only one register involved:
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assert(reg == get_bits(loc32[1], 0, 5)); // ldr's output register.
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assert(reg == get_bits(loc32[1], 5, 5)); // ldr's input register.
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uint64_t relaxed = *(uint64_t *)value;
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if (relaxed < (1UL << 16)) {
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// adrp reg, AAA; ldr reg, [reg + BBB] -> movz reg, XXX; nop
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loc32[0] = 0xD2800000 | (get_bits(relaxed, 0, 16) << 5) | reg;
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loc32[1] = 0xD503201F;
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return;
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}
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if (relaxed < (1ULL << 32)) {
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// adrp reg, AAA; ldr reg, [reg + BBB] -> movz reg, XXX; movk reg, YYY
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loc32[0] = 0xD2800000 | (get_bits(relaxed, 0, 16) << 5) | reg;
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loc32[1] = 0xF2A00000 | (get_bits(relaxed, 16, 16) << 5) | reg;
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return;
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}
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relaxed = value - (uintptr_t)location;
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if ((relaxed & 0x3) == 0 &&
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(int64_t)relaxed >= -(1L << 19) &&
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(int64_t)relaxed < (1L << 19))
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{
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// adrp reg, AAA; ldr reg, [reg + BBB] -> ldr reg, XXX; nop
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loc32[0] = 0x58000000 | (get_bits(relaxed, 2, 19) << 5) | reg;
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loc32[1] = 0xD503201F;
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return;
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}
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// Couldn't do it. Just patch the two instructions normally:
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patch_aarch64_21rx(location, value);
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patch_aarch64_12x(location + 4, value);
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}
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// Relaxable 32-bit relative address.
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void
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patch_x86_64_32rx(unsigned char *location, uint64_t value)
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{
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uint8_t *loc8 = (uint8_t *)location;
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// Try to relax the GOT load into an immediate value:
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uint64_t relaxed = *(uint64_t *)(value + 4) - 4;
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if ((int64_t)relaxed - (int64_t)location >= -(1LL << 31) &&
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(int64_t)relaxed - (int64_t)location + 1 < (1LL << 31))
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{
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if (loc8[-2] == 0x8B) {
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// mov reg, dword ptr [rip + AAA] -> lea reg, [rip + XXX]
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loc8[-2] = 0x8D;
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value = relaxed;
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}
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else if (loc8[-2] == 0xFF && loc8[-1] == 0x15) {
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// call qword ptr [rip + AAA] -> nop; call XXX
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loc8[-2] = 0x90;
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loc8[-1] = 0xE8;
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value = relaxed;
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}
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else if (loc8[-2] == 0xFF && loc8[-1] == 0x25) {
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// jmp qword ptr [rip + AAA] -> nop; jmp XXX
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loc8[-2] = 0x90;
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loc8[-1] = 0xE9;
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value = relaxed;
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}
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}
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patch_32r(location, value);
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}
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#include "jit_stencils.h"
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// Compiles executor in-place. Don't forget to call _PyJIT_Free later!
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int
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_PyJIT_Compile(_PyExecutorObject *executor, const _PyUOpInstruction trace[], size_t length)
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{
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const StencilGroup *group;
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// Loop once to find the total compiled size:
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uintptr_t instruction_starts[UOP_MAX_TRACE_LENGTH];
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size_t code_size = 0;
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size_t data_size = 0;
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group = &trampoline;
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code_size += group->code_size;
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data_size += group->data_size;
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for (size_t i = 0; i < length; i++) {
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const _PyUOpInstruction *instruction = &trace[i];
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group = &stencil_groups[instruction->opcode];
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instruction_starts[i] = code_size;
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code_size += group->code_size;
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data_size += group->data_size;
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}
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group = &stencil_groups[_FATAL_ERROR];
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code_size += group->code_size;
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data_size += group->data_size;
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// Round up to the nearest page:
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size_t page_size = get_page_size();
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assert((page_size & (page_size - 1)) == 0);
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size_t padding = page_size - ((code_size + data_size) & (page_size - 1));
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size_t total_size = code_size + data_size + padding;
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unsigned char *memory = jit_alloc(total_size);
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if (memory == NULL) {
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return -1;
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}
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// Update the offsets of each instruction:
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for (size_t i = 0; i < length; i++) {
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instruction_starts[i] += (uintptr_t)memory;
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}
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// Loop again to emit the code:
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unsigned char *code = memory;
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unsigned char *data = memory + code_size;
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// Compile the trampoline, which handles converting between the native
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// calling convention and the calling convention used by jitted code
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// (which may be different for efficiency reasons). On platforms where
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// we don't change calling conventions, the trampoline is empty and
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// nothing is emitted here:
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group = &trampoline;
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group->emit(code, data, executor, NULL, instruction_starts);
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code += group->code_size;
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data += group->data_size;
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assert(trace[0].opcode == _START_EXECUTOR || trace[0].opcode == _COLD_EXIT);
|
|
for (size_t i = 0; i < length; i++) {
|
|
const _PyUOpInstruction *instruction = &trace[i];
|
|
group = &stencil_groups[instruction->opcode];
|
|
group->emit(code, data, executor, instruction, instruction_starts);
|
|
code += group->code_size;
|
|
data += group->data_size;
|
|
}
|
|
// Protect against accidental buffer overrun into data:
|
|
group = &stencil_groups[_FATAL_ERROR];
|
|
group->emit(code, data, executor, NULL, instruction_starts);
|
|
code += group->code_size;
|
|
data += group->data_size;
|
|
assert(code == memory + code_size);
|
|
assert(data == memory + code_size + data_size);
|
|
if (mark_executable(memory, total_size)) {
|
|
jit_free(memory, total_size);
|
|
return -1;
|
|
}
|
|
executor->jit_code = memory;
|
|
executor->jit_side_entry = memory + trampoline.code_size;
|
|
executor->jit_size = total_size;
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
_PyJIT_Free(_PyExecutorObject *executor)
|
|
{
|
|
unsigned char *memory = (unsigned char *)executor->jit_code;
|
|
size_t size = executor->jit_size;
|
|
if (memory) {
|
|
executor->jit_code = NULL;
|
|
executor->jit_side_entry = NULL;
|
|
executor->jit_size = 0;
|
|
if (jit_free(memory, size)) {
|
|
PyErr_WriteUnraisable(NULL);
|
|
}
|
|
}
|
|
}
|
|
|
|
#endif // _Py_JIT
|