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https://github.com/TASVideos/desmume
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7 Commits
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437d3b4352
| Author | SHA1 | Date | |
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437d3b4352 | ||
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90d0abdae0 | ||
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738298a9e8 | ||
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4a53a30b91 | ||
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a44d7ff406 | ||
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4265ab80ca | ||
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d21d10e087 |
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@ -54,6 +54,10 @@
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#define ASSERT_UNALIGNED(x)
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#endif
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#ifdef DSI_NEWWRAM
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void FASTCALL MMU_UpdateNWRAM();
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#endif
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//TODO - do we need these here?
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static _KEY2 key2;
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@ -907,7 +911,7 @@ void MMU_Init(void)
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LOG("MMU init\n");
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memset(&MMU, 0, sizeof(MMU_struct));
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MMU.blank_memory = &MMU.ARM9_LCD[0xA4000];
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//MMU.DTCMRegion = 0x027C0000;
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@ -926,14 +930,29 @@ void MMU_Init(void)
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MMU.fw.isFirmware = true;
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rtcInit();
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slot1_Init();
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slot2_Init();
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if(Mic_Init() == FALSE)
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if (Mic_Init() == FALSE)
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INFO("Microphone init failed.\n");
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else
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INFO("Microphone successfully inited.\n");
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#ifdef DSI_NEWWRAM
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// Disable all NWRAM Banks on Init
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for (int i = 0; i < 20; i++)
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MMU.regNRWAM_BankControl[i] = 0;
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// Disable all Windows
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for (int i = 0; i < 2; i++)
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for (int q = 0; q < 3; q++)
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MMU.regNWRAM_Windows[i][q] = 0;
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// No Write Protection
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MMU.regNWRAM_Protect = 0 ;
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// update internal data from these init settings
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MMU_UpdateNWRAM();
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#endif
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}
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void MMU_DeInit(void) {
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@ -2717,6 +2736,19 @@ bool validateIORegsWrite(u32 addr, u8 size, u32 val)
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// ...GBA
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case REG_DISPB_MASTERBRIGHT:
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// NWRAM
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#ifdef DSI_NEWWRAM:
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case REG_NWRAM_CTRL_SET0BANK0:
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case REG_NWRAM_CTRL_SET1BANK0:
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case REG_NWRAM_CTRL_SET1BANK4:
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case REG_NWRAM_CTRL_SET2BANK0:
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case REG_NWRAM_CTRL_SET2BANK4:
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case REG_NWRAM_WINDOW_SET0:
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case REG_NWRAM_WINDOW_SET1:
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case REG_NWRAM_WINDOW_SET2:
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case REG_NWRAM_PROTECT:
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#endif
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// 0x04100000
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case REG_IPCFIFORECV:
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case REG_GCDATAIN:
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@ -2818,6 +2850,19 @@ bool validateIORegsWrite(u32 addr, u8 size, u32 val)
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// Sound
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// NWRAM
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#ifdef DSI_NEWWRAM:
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case REG_NWRAM_CTRL_SET0BANK0:
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case REG_NWRAM_CTRL_SET1BANK0:
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case REG_NWRAM_CTRL_SET1BANK4:
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case REG_NWRAM_CTRL_SET2BANK0:
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case REG_NWRAM_CTRL_SET2BANK4:
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case REG_NWRAM_WINDOW_SET0:
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case REG_NWRAM_WINDOW_SET1:
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case REG_NWRAM_WINDOW_SET2:
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case REG_NWRAM_PROTECT:
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#endif
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// 0x04100000 - IPC
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case REG_IPCFIFORECV:
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case REG_GCDATAIN:
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@ -3824,6 +3869,61 @@ void FASTCALL _MMU_ARM9_write08(u32 adr, u8 val)
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case 0x040001AF :
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LOG("%08X : %02X\r\n", adr, val);
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#endif
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#ifdef DSI_NEWWRAM
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case REG_NWRAM_CTRL_SET0BANK0:
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case REG_NWRAM_CTRL_SET0BANK1:
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case REG_NWRAM_CTRL_SET0BANK2:
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case REG_NWRAM_CTRL_SET0BANK3:
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case REG_NWRAM_CTRL_SET1BANK0:
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case REG_NWRAM_CTRL_SET1BANK1:
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case REG_NWRAM_CTRL_SET1BANK2:
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case REG_NWRAM_CTRL_SET1BANK3:
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case REG_NWRAM_CTRL_SET1BANK4:
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case REG_NWRAM_CTRL_SET1BANK5:
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case REG_NWRAM_CTRL_SET1BANK6:
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case REG_NWRAM_CTRL_SET1BANK7:
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case REG_NWRAM_CTRL_SET2BANK0:
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case REG_NWRAM_CTRL_SET2BANK1:
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case REG_NWRAM_CTRL_SET2BANK2:
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case REG_NWRAM_CTRL_SET2BANK3:
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case REG_NWRAM_CTRL_SET2BANK4:
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case REG_NWRAM_CTRL_SET2BANK5:
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case REG_NWRAM_CTRL_SET2BANK6:
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case REG_NWRAM_CTRL_SET2BANK7:
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{
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// check if this bank is currently writeable
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uint8_t bit = (adr >= REG_NWRAM_CTRL_SET1BANK0) ? ((adr - REG_NWRAM_CTRL_SET1BANK0) + 8) : (adr - REG_NWRAM_CTRL_SET0BANK0);
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if (MMU.regNWRAM_Protect & (1 << bit))
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return;
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// otherwise update!
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MMU.regNRWAM_BankControl[adr - REG_NWRAM_CTRL_SET0BANK0] = val;
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MMU_UpdateNWRAM();
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return;
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}
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case REG_NWRAM_WINDOW_SET0:
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case REG_NWRAM_WINDOW_SET0 + 1:
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case REG_NWRAM_WINDOW_SET0 + 2:
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case REG_NWRAM_WINDOW_SET0 + 3:
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case REG_NWRAM_WINDOW_SET1:
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case REG_NWRAM_WINDOW_SET1 + 1:
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case REG_NWRAM_WINDOW_SET1 + 2:
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case REG_NWRAM_WINDOW_SET1 + 3:
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case REG_NWRAM_WINDOW_SET2:
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case REG_NWRAM_WINDOW_SET2 + 1:
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case REG_NWRAM_WINDOW_SET2 + 2:
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case REG_NWRAM_WINDOW_SET2 + 3:
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MMU.regNWRAM_Windows[1][(adr - REG_NWRAM_WINDOW_SET0) >> 2] &= ~(0xff << ((adr & 3) * 8));
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MMU.regNWRAM_Windows[1][(adr - REG_NWRAM_WINDOW_SET0) >> 2] |= (val << ((adr & 3) * 8));
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MMU_UpdateNWRAM();
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return;
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case REG_NWRAM_PROTECT:
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case REG_NWRAM_PROTECT + 1:
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case REG_NWRAM_PROTECT + 2:
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case REG_NWRAM_PROTECT + 3:
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// not writeable on arm9
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return;
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#endif
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}
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MMU.MMU_MEM[ARMCPU_ARM9][adr>>20][adr&MMU.MMU_MASK[ARMCPU_ARM9][adr>>20]]=val;
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@ -3835,6 +3935,18 @@ void FASTCALL _MMU_ARM9_write08(u32 adr, u8 val)
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return;
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}
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#ifdef DSI_NEWWRAM
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if ((adr >> 24) == 0x03)
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{
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if (MMU.NWRAMBLOCKPTRS[0][(adr - 0x03000000) / 0x8000])
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{
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MMU.NWRAMBLOCKPTRS[0][(adr - 0x03000000) / 0x8000][adr & 0x7fff] = val;
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return;
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}
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}
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#endif
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bool unmapped, restricted;
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adr = MMU_LCDmap<ARMCPU_ARM9>(adr, unmapped, restricted);
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if(unmapped) return;
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@ -4541,6 +4653,64 @@ void FASTCALL _MMU_ARM9_write16(u32 adr, u16 val)
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case REG_GCROMCTRL+2 :
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MMU_writeToGCControl<ARMCPU_ARM9>( (T1ReadLong(MMU.MMU_MEM[0][0x40], 0x1A4) & 0xFFFF) | ((u32) val << 16));
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return;
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#ifdef DSI_NEWWRAM
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case REG_NWRAM_CTRL_SET0BANK0:
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case REG_NWRAM_CTRL_SET0BANK1:
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case REG_NWRAM_CTRL_SET0BANK2:
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case REG_NWRAM_CTRL_SET0BANK3:
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case REG_NWRAM_CTRL_SET1BANK0:
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case REG_NWRAM_CTRL_SET1BANK1:
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case REG_NWRAM_CTRL_SET1BANK2:
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case REG_NWRAM_CTRL_SET1BANK3:
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case REG_NWRAM_CTRL_SET1BANK4:
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case REG_NWRAM_CTRL_SET1BANK5:
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case REG_NWRAM_CTRL_SET1BANK6:
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case REG_NWRAM_CTRL_SET1BANK7:
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case REG_NWRAM_CTRL_SET2BANK0:
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case REG_NWRAM_CTRL_SET2BANK1:
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case REG_NWRAM_CTRL_SET2BANK2:
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case REG_NWRAM_CTRL_SET2BANK3:
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case REG_NWRAM_CTRL_SET2BANK4:
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case REG_NWRAM_CTRL_SET2BANK5:
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case REG_NWRAM_CTRL_SET2BANK6:
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case REG_NWRAM_CTRL_SET2BANK7:
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{
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// check if this bank is currently writeable
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for (int i = 0; i < 2; i++)
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{
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uint8_t bit = ((adr + i) >= REG_NWRAM_CTRL_SET1BANK0) ? (((adr+i) - REG_NWRAM_CTRL_SET1BANK0) + 8) : ((adr + i) - REG_NWRAM_CTRL_SET0BANK0);
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if (MMU.regNWRAM_Protect & (1 << bit))
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return;
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// otherwise update!
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MMU.regNRWAM_BankControl[adr - REG_NWRAM_CTRL_SET0BANK0] = val >> (i *8);
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}
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MMU_UpdateNWRAM();
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return;
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}
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case REG_NWRAM_WINDOW_SET0:
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case REG_NWRAM_WINDOW_SET0 + 1:
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case REG_NWRAM_WINDOW_SET0 + 2:
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case REG_NWRAM_WINDOW_SET0 + 3:
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case REG_NWRAM_WINDOW_SET1:
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case REG_NWRAM_WINDOW_SET1 + 1:
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case REG_NWRAM_WINDOW_SET1 + 2:
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case REG_NWRAM_WINDOW_SET1 + 3:
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case REG_NWRAM_WINDOW_SET2:
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case REG_NWRAM_WINDOW_SET2 + 1:
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case REG_NWRAM_WINDOW_SET2 + 2:
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case REG_NWRAM_WINDOW_SET2 + 3:
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MMU.regNWRAM_Windows[1][(adr - REG_NWRAM_WINDOW_SET0) >> 2] &= ~(0xffff << ((adr & 2) * 8));
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MMU.regNWRAM_Windows[1][(adr - REG_NWRAM_WINDOW_SET0) >> 2] |= (val << ((adr & 2) * 8));
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MMU_UpdateNWRAM();
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return;
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case REG_NWRAM_PROTECT:
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case REG_NWRAM_PROTECT + 1:
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case REG_NWRAM_PROTECT + 2:
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case REG_NWRAM_PROTECT + 3:
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// not writeable on arm9
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return;
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#endif
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}
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T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][adr>>20], adr&MMU.MMU_MASK[ARMCPU_ARM9][adr>>20], val);
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@ -4552,6 +4722,17 @@ void FASTCALL _MMU_ARM9_write16(u32 adr, u16 val)
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return;
|
||||
}
|
||||
|
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#ifdef DSI_NEWWRAM
|
||||
if ((adr >> 24) == 0x03)
|
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{
|
||||
if (MMU.NWRAMBLOCKPTRS[1][(adr - 0x03000000) / 0x8000])
|
||||
{
|
||||
T1WriteWord(MMU.NWRAMBLOCKPTRS[1][(adr - 0x03000000) / 0x8000], adr & 0x7fff, val);
|
||||
return;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
bool unmapped, restricted;
|
||||
adr = MMU_LCDmap<ARMCPU_ARM9>(adr, unmapped, restricted);
|
||||
if(unmapped) return;
|
||||
|
|
@ -5081,6 +5262,63 @@ void FASTCALL _MMU_ARM9_write32(u32 adr, u32 val)
|
|||
case REG_GCDATAIN:
|
||||
MMU_writeToGC<ARMCPU_ARM9>(val);
|
||||
return;
|
||||
#ifdef DSI_NEWWRAM
|
||||
case REG_NWRAM_CTRL_SET0BANK0:
|
||||
case REG_NWRAM_CTRL_SET0BANK1:
|
||||
case REG_NWRAM_CTRL_SET0BANK2:
|
||||
case REG_NWRAM_CTRL_SET0BANK3:
|
||||
case REG_NWRAM_CTRL_SET1BANK0:
|
||||
case REG_NWRAM_CTRL_SET1BANK1:
|
||||
case REG_NWRAM_CTRL_SET1BANK2:
|
||||
case REG_NWRAM_CTRL_SET1BANK3:
|
||||
case REG_NWRAM_CTRL_SET1BANK4:
|
||||
case REG_NWRAM_CTRL_SET1BANK5:
|
||||
case REG_NWRAM_CTRL_SET1BANK6:
|
||||
case REG_NWRAM_CTRL_SET1BANK7:
|
||||
case REG_NWRAM_CTRL_SET2BANK0:
|
||||
case REG_NWRAM_CTRL_SET2BANK1:
|
||||
case REG_NWRAM_CTRL_SET2BANK2:
|
||||
case REG_NWRAM_CTRL_SET2BANK3:
|
||||
case REG_NWRAM_CTRL_SET2BANK4:
|
||||
case REG_NWRAM_CTRL_SET2BANK5:
|
||||
case REG_NWRAM_CTRL_SET2BANK6:
|
||||
case REG_NWRAM_CTRL_SET2BANK7:
|
||||
{
|
||||
// check if this bank is currently writeable
|
||||
for (int i = 0; i < 4; i++)
|
||||
{
|
||||
uint8_t bit = ((adr + i) >= REG_NWRAM_CTRL_SET1BANK0) ? (((adr + i) - REG_NWRAM_CTRL_SET1BANK0) + 8) : ((adr + i) - REG_NWRAM_CTRL_SET0BANK0);
|
||||
if (MMU.regNWRAM_Protect & (1 << bit))
|
||||
return;
|
||||
// otherwise update!
|
||||
MMU.regNRWAM_BankControl[adr - REG_NWRAM_CTRL_SET0BANK0] = val >> (i * 8);
|
||||
|
||||
}
|
||||
MMU_UpdateNWRAM();
|
||||
return;
|
||||
}
|
||||
case REG_NWRAM_WINDOW_SET0:
|
||||
case REG_NWRAM_WINDOW_SET0 + 1:
|
||||
case REG_NWRAM_WINDOW_SET0 + 2:
|
||||
case REG_NWRAM_WINDOW_SET0 + 3:
|
||||
case REG_NWRAM_WINDOW_SET1:
|
||||
case REG_NWRAM_WINDOW_SET1 + 1:
|
||||
case REG_NWRAM_WINDOW_SET1 + 2:
|
||||
case REG_NWRAM_WINDOW_SET1 + 3:
|
||||
case REG_NWRAM_WINDOW_SET2:
|
||||
case REG_NWRAM_WINDOW_SET2 + 1:
|
||||
case REG_NWRAM_WINDOW_SET2 + 2:
|
||||
case REG_NWRAM_WINDOW_SET2 + 3:
|
||||
MMU.regNWRAM_Windows[1][(adr - REG_NWRAM_WINDOW_SET0) >> 2] = val;
|
||||
MMU_UpdateNWRAM();
|
||||
return;
|
||||
case REG_NWRAM_PROTECT:
|
||||
case REG_NWRAM_PROTECT + 1:
|
||||
case REG_NWRAM_PROTECT + 2:
|
||||
case REG_NWRAM_PROTECT + 3:
|
||||
// not writeable on arm9
|
||||
return;
|
||||
#endif
|
||||
}
|
||||
|
||||
T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][adr>>20], adr & MMU.MMU_MASK[ARMCPU_ARM9][adr>>20], val);
|
||||
|
|
@ -5092,6 +5330,17 @@ void FASTCALL _MMU_ARM9_write32(u32 adr, u32 val)
|
|||
return;
|
||||
}
|
||||
|
||||
#ifdef DSI_NEWWRAM
|
||||
if ((adr >> 24) == 0x03)
|
||||
{
|
||||
if (MMU.NWRAMBLOCKPTRS[1][(adr - 0x03000000) / 0x8000])
|
||||
{
|
||||
T1WriteLong(MMU.NWRAMBLOCKPTRS[1][(adr - 0x03000000) / 0x8000], adr & 0x7fff, val);
|
||||
return;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
bool unmapped, restricted;
|
||||
adr = MMU_LCDmap<ARMCPU_ARM9>(adr, unmapped, restricted);
|
||||
if(unmapped) return;
|
||||
|
|
@ -5221,9 +5470,59 @@ u8 FASTCALL _MMU_ARM9_read08(u32 adr)
|
|||
case REG_KEYINPUT:
|
||||
LagFrameFlag=0;
|
||||
break;
|
||||
#ifdef DSI_NEWWRAM
|
||||
case REG_NWRAM_CTRL_SET0BANK0:
|
||||
case REG_NWRAM_CTRL_SET0BANK1:
|
||||
case REG_NWRAM_CTRL_SET0BANK2:
|
||||
case REG_NWRAM_CTRL_SET0BANK3:
|
||||
case REG_NWRAM_CTRL_SET1BANK0:
|
||||
case REG_NWRAM_CTRL_SET1BANK1:
|
||||
case REG_NWRAM_CTRL_SET1BANK2:
|
||||
case REG_NWRAM_CTRL_SET1BANK3:
|
||||
case REG_NWRAM_CTRL_SET1BANK4:
|
||||
case REG_NWRAM_CTRL_SET1BANK5:
|
||||
case REG_NWRAM_CTRL_SET1BANK6:
|
||||
case REG_NWRAM_CTRL_SET1BANK7:
|
||||
case REG_NWRAM_CTRL_SET2BANK0:
|
||||
case REG_NWRAM_CTRL_SET2BANK1:
|
||||
case REG_NWRAM_CTRL_SET2BANK2:
|
||||
case REG_NWRAM_CTRL_SET2BANK3:
|
||||
case REG_NWRAM_CTRL_SET2BANK4:
|
||||
case REG_NWRAM_CTRL_SET2BANK5:
|
||||
case REG_NWRAM_CTRL_SET2BANK6:
|
||||
case REG_NWRAM_CTRL_SET2BANK7:
|
||||
return MMU.regNRWAM_BankControl[adr - REG_NWRAM_CTRL_SET0BANK0];
|
||||
case REG_NWRAM_WINDOW_SET0:
|
||||
case REG_NWRAM_WINDOW_SET0 + 1:
|
||||
case REG_NWRAM_WINDOW_SET0 + 2:
|
||||
case REG_NWRAM_WINDOW_SET0 + 3:
|
||||
case REG_NWRAM_WINDOW_SET1:
|
||||
case REG_NWRAM_WINDOW_SET1 + 1:
|
||||
case REG_NWRAM_WINDOW_SET1 + 2:
|
||||
case REG_NWRAM_WINDOW_SET1 + 3:
|
||||
case REG_NWRAM_WINDOW_SET2:
|
||||
case REG_NWRAM_WINDOW_SET2 + 1:
|
||||
case REG_NWRAM_WINDOW_SET2 + 2:
|
||||
case REG_NWRAM_WINDOW_SET2 + 3:
|
||||
return (MMU.regNWRAM_Windows[1][(adr - REG_NWRAM_WINDOW_SET0) >> 2] >> ((adr & 3) * 8)) & 0xff;
|
||||
case REG_NWRAM_PROTECT:
|
||||
case REG_NWRAM_PROTECT + 1:
|
||||
case REG_NWRAM_PROTECT + 2:
|
||||
case REG_NWRAM_PROTECT + 3:
|
||||
return (MMU.regNWRAM_Protect >> ((adr & 3) * 8)) & 0xff;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef DSI_NEWWRAM
|
||||
if ((adr >> 24) == 0x03)
|
||||
{
|
||||
if (MMU.NWRAMBLOCKPTRS[1][(adr - 0x03000000) / 0x8000])
|
||||
return MMU.NWRAMBLOCKPTRS[1][(adr - 0x03000000) / 0x8000][adr & 0x7fff];
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
bool unmapped, restricted;
|
||||
adr = MMU_LCDmap<ARMCPU_ARM9>(adr, unmapped, restricted);
|
||||
if(unmapped) return 0;
|
||||
|
|
@ -5328,11 +5627,59 @@ u16 FASTCALL _MMU_ARM9_read16(u32 adr)
|
|||
case eng_3D_FOG_TABLE+0x10: case eng_3D_FOG_TABLE+0x12: case eng_3D_FOG_TABLE+0x14: case eng_3D_FOG_TABLE+0x16:
|
||||
case eng_3D_FOG_TABLE+0x18: case eng_3D_FOG_TABLE+0x1A: case eng_3D_FOG_TABLE+0x1C: case eng_3D_FOG_TABLE+0x1E:
|
||||
return 0;
|
||||
#ifdef DSI_NEWWRAM
|
||||
case REG_NWRAM_CTRL_SET0BANK0:
|
||||
case REG_NWRAM_CTRL_SET0BANK1:
|
||||
case REG_NWRAM_CTRL_SET0BANK2:
|
||||
case REG_NWRAM_CTRL_SET0BANK3:
|
||||
case REG_NWRAM_CTRL_SET1BANK0:
|
||||
case REG_NWRAM_CTRL_SET1BANK1:
|
||||
case REG_NWRAM_CTRL_SET1BANK2:
|
||||
case REG_NWRAM_CTRL_SET1BANK3:
|
||||
case REG_NWRAM_CTRL_SET1BANK4:
|
||||
case REG_NWRAM_CTRL_SET1BANK5:
|
||||
case REG_NWRAM_CTRL_SET1BANK6:
|
||||
case REG_NWRAM_CTRL_SET1BANK7:
|
||||
case REG_NWRAM_CTRL_SET2BANK0:
|
||||
case REG_NWRAM_CTRL_SET2BANK1:
|
||||
case REG_NWRAM_CTRL_SET2BANK2:
|
||||
case REG_NWRAM_CTRL_SET2BANK3:
|
||||
case REG_NWRAM_CTRL_SET2BANK4:
|
||||
case REG_NWRAM_CTRL_SET2BANK5:
|
||||
case REG_NWRAM_CTRL_SET2BANK6:
|
||||
return MMU.regNRWAM_BankControl[adr - REG_NWRAM_CTRL_SET0BANK0] | (MMU.regNRWAM_BankControl[adr + 1 - REG_NWRAM_CTRL_SET0BANK0] << 8);
|
||||
case REG_NWRAM_WINDOW_SET0:
|
||||
case REG_NWRAM_WINDOW_SET0 + 1:
|
||||
case REG_NWRAM_WINDOW_SET0 + 2:
|
||||
case REG_NWRAM_WINDOW_SET0 + 3:
|
||||
case REG_NWRAM_WINDOW_SET1:
|
||||
case REG_NWRAM_WINDOW_SET1 + 1:
|
||||
case REG_NWRAM_WINDOW_SET1 + 2:
|
||||
case REG_NWRAM_WINDOW_SET1 + 3:
|
||||
case REG_NWRAM_WINDOW_SET2:
|
||||
case REG_NWRAM_WINDOW_SET2 + 1:
|
||||
case REG_NWRAM_WINDOW_SET2 + 2:
|
||||
case REG_NWRAM_WINDOW_SET2 + 3:
|
||||
return (MMU.regNWRAM_Windows[1][(adr - REG_NWRAM_WINDOW_SET0) >> 2] >> ((adr & 2) * 8)) & 0xffff;
|
||||
case REG_NWRAM_PROTECT:
|
||||
case REG_NWRAM_PROTECT + 1:
|
||||
case REG_NWRAM_PROTECT + 2:
|
||||
case REG_NWRAM_PROTECT + 3:
|
||||
return (MMU.regNWRAM_Protect >> ((adr & 2) * 8)) & 0xffff;
|
||||
#endif
|
||||
}
|
||||
|
||||
return T1ReadWord_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM9][adr>>20], adr & MMU.MMU_MASK[ARMCPU_ARM9][adr>>20]);
|
||||
}
|
||||
|
||||
#ifdef DSI_NEWWRAM
|
||||
if ((adr >> 24) == 0x03)
|
||||
{
|
||||
if (MMU.NWRAMBLOCKPTRS[1][(adr - 0x03000000) / 0x8000])
|
||||
return T1ReadWord_guaranteedAligned(MMU.NWRAMBLOCKPTRS[1][(adr - 0x03000000) / 0x8000], adr & 0x7fff);
|
||||
}
|
||||
#endif
|
||||
|
||||
bool unmapped, restricted;
|
||||
adr = MMU_LCDmap<ARMCPU_ARM9>(adr,unmapped, restricted);
|
||||
if(unmapped) return 0;
|
||||
|
|
@ -5473,10 +5820,58 @@ u32 FASTCALL _MMU_ARM9_read32(u32 adr)
|
|||
case REG_KEYINPUT:
|
||||
LagFrameFlag=0;
|
||||
break;
|
||||
#ifdef DSI_NEWWRAM
|
||||
case REG_NWRAM_CTRL_SET0BANK0:
|
||||
case REG_NWRAM_CTRL_SET0BANK1:
|
||||
case REG_NWRAM_CTRL_SET0BANK2:
|
||||
case REG_NWRAM_CTRL_SET0BANK3:
|
||||
case REG_NWRAM_CTRL_SET1BANK0:
|
||||
case REG_NWRAM_CTRL_SET1BANK1:
|
||||
case REG_NWRAM_CTRL_SET1BANK2:
|
||||
case REG_NWRAM_CTRL_SET1BANK3:
|
||||
case REG_NWRAM_CTRL_SET1BANK4:
|
||||
case REG_NWRAM_CTRL_SET1BANK5:
|
||||
case REG_NWRAM_CTRL_SET1BANK6:
|
||||
case REG_NWRAM_CTRL_SET1BANK7:
|
||||
case REG_NWRAM_CTRL_SET2BANK0:
|
||||
case REG_NWRAM_CTRL_SET2BANK1:
|
||||
case REG_NWRAM_CTRL_SET2BANK2:
|
||||
case REG_NWRAM_CTRL_SET2BANK3:
|
||||
case REG_NWRAM_CTRL_SET2BANK4:
|
||||
return MMU.regNRWAM_BankControl[adr - REG_NWRAM_CTRL_SET0BANK0] | (MMU.regNRWAM_BankControl[adr + 1 - REG_NWRAM_CTRL_SET0BANK0] << 8)
|
||||
| (MMU.regNRWAM_BankControl[adr + 2 - REG_NWRAM_CTRL_SET0BANK0] << 16) | (MMU.regNRWAM_BankControl[adr + 3 - REG_NWRAM_CTRL_SET0BANK0] << 24);
|
||||
case REG_NWRAM_WINDOW_SET0:
|
||||
case REG_NWRAM_WINDOW_SET0 + 1:
|
||||
case REG_NWRAM_WINDOW_SET0 + 2:
|
||||
case REG_NWRAM_WINDOW_SET0 + 3:
|
||||
case REG_NWRAM_WINDOW_SET1:
|
||||
case REG_NWRAM_WINDOW_SET1 + 1:
|
||||
case REG_NWRAM_WINDOW_SET1 + 2:
|
||||
case REG_NWRAM_WINDOW_SET1 + 3:
|
||||
case REG_NWRAM_WINDOW_SET2:
|
||||
case REG_NWRAM_WINDOW_SET2 + 1:
|
||||
case REG_NWRAM_WINDOW_SET2 + 2:
|
||||
case REG_NWRAM_WINDOW_SET2 + 3:
|
||||
return MMU.regNWRAM_Windows[1][(adr - REG_NWRAM_WINDOW_SET0) >> 2];
|
||||
case REG_NWRAM_PROTECT:
|
||||
case REG_NWRAM_PROTECT + 1:
|
||||
case REG_NWRAM_PROTECT + 2:
|
||||
case REG_NWRAM_PROTECT + 3:
|
||||
return MMU.regNWRAM_Protect;
|
||||
#endif
|
||||
}
|
||||
return T1ReadLong_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM9][adr>>20], adr & MMU.MMU_MASK[ARMCPU_ARM9][adr>>20]);
|
||||
}
|
||||
|
||||
|
||||
#ifdef DSI_NEWWRAM
|
||||
if ((adr >> 24) == 0x03)
|
||||
{
|
||||
if (MMU.NWRAMBLOCKPTRS[1][(adr - 0x03000000) / 0x8000])
|
||||
return T1ReadLong_guaranteedAligned(MMU.NWRAMBLOCKPTRS[1][(adr - 0x03000000) / 0x8000], adr & 0x7fff);
|
||||
}
|
||||
#endif
|
||||
|
||||
bool unmapped, restricted;
|
||||
adr = MMU_LCDmap<ARMCPU_ARM9>(adr,unmapped, restricted);
|
||||
if(unmapped) return 0;
|
||||
|
|
@ -5582,11 +5977,71 @@ void FASTCALL _MMU_ARM7_write08(u32 adr, u8 val)
|
|||
// into RAM at 0x027FF830
|
||||
MMU_writeToSPIData(val);
|
||||
return;
|
||||
#ifdef DSI_NEWWRAM
|
||||
case REG_NWRAM_CTRL_SET0BANK0:
|
||||
case REG_NWRAM_CTRL_SET0BANK1:
|
||||
case REG_NWRAM_CTRL_SET0BANK2:
|
||||
case REG_NWRAM_CTRL_SET0BANK3:
|
||||
case REG_NWRAM_CTRL_SET1BANK0:
|
||||
case REG_NWRAM_CTRL_SET1BANK1:
|
||||
case REG_NWRAM_CTRL_SET1BANK2:
|
||||
case REG_NWRAM_CTRL_SET1BANK3:
|
||||
case REG_NWRAM_CTRL_SET1BANK4:
|
||||
case REG_NWRAM_CTRL_SET1BANK5:
|
||||
case REG_NWRAM_CTRL_SET1BANK6:
|
||||
case REG_NWRAM_CTRL_SET1BANK7:
|
||||
case REG_NWRAM_CTRL_SET2BANK0:
|
||||
case REG_NWRAM_CTRL_SET2BANK1:
|
||||
case REG_NWRAM_CTRL_SET2BANK2:
|
||||
case REG_NWRAM_CTRL_SET2BANK3:
|
||||
case REG_NWRAM_CTRL_SET2BANK4:
|
||||
case REG_NWRAM_CTRL_SET2BANK5:
|
||||
case REG_NWRAM_CTRL_SET2BANK6:
|
||||
case REG_NWRAM_CTRL_SET2BANK7:
|
||||
/* These registers can not be changed by the arm7, as of a fuse bit in SCFG
|
||||
TODO: If that SFCG is implemented this might get writeable */
|
||||
return;
|
||||
case REG_NWRAM_WINDOW_SET0:
|
||||
case REG_NWRAM_WINDOW_SET0 + 1:
|
||||
case REG_NWRAM_WINDOW_SET0 + 2:
|
||||
case REG_NWRAM_WINDOW_SET0 + 3:
|
||||
case REG_NWRAM_WINDOW_SET1:
|
||||
case REG_NWRAM_WINDOW_SET1 + 1:
|
||||
case REG_NWRAM_WINDOW_SET1 + 2:
|
||||
case REG_NWRAM_WINDOW_SET1 + 3:
|
||||
case REG_NWRAM_WINDOW_SET2:
|
||||
case REG_NWRAM_WINDOW_SET2 + 1:
|
||||
case REG_NWRAM_WINDOW_SET2 + 2:
|
||||
case REG_NWRAM_WINDOW_SET2 + 3:
|
||||
MMU.regNWRAM_Windows[0][(adr - REG_NWRAM_WINDOW_SET0) >> 2] &= ~(0xff << ((adr & 3) * 8));
|
||||
MMU.regNWRAM_Windows[0][(adr - REG_NWRAM_WINDOW_SET0) >> 2] |= (val << ((adr & 3) * 8));
|
||||
MMU_UpdateNWRAM();
|
||||
return;
|
||||
case REG_NWRAM_PROTECT:
|
||||
case REG_NWRAM_PROTECT + 1:
|
||||
case REG_NWRAM_PROTECT + 2:
|
||||
case REG_NWRAM_PROTECT + 3:
|
||||
MMU.regNWRAM_Protect &= ~(0xff << ((adr & 3) * 8));
|
||||
MMU.regNWRAM_Protect |= (val << ((adr & 3) * 8));
|
||||
return;
|
||||
#endif
|
||||
}
|
||||
MMU.MMU_MEM[ARMCPU_ARM7][adr>>20][adr&MMU.MMU_MASK[ARMCPU_ARM7][adr>>20]]=val;
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
#ifdef DSI_NEWWRAM
|
||||
if ((adr >> 24) == 0x03)
|
||||
{
|
||||
if (MMU.NWRAMBLOCKPTRS[0][(adr - 0x03000000) / 0x8000])
|
||||
{
|
||||
MMU.NWRAMBLOCKPTRS[0][(adr - 0x03000000) / 0x8000][adr & 0x7fff] = val;
|
||||
return;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
bool unmapped, restricted;
|
||||
adr = MMU_LCDmap<ARMCPU_ARM7>(adr,unmapped, restricted);
|
||||
if(unmapped) return;
|
||||
|
|
@ -5767,12 +6222,72 @@ void FASTCALL _MMU_ARM7_write16(u32 adr, u16 val)
|
|||
case REG_GCROMCTRL+2 :
|
||||
MMU_writeToGCControl<ARMCPU_ARM7>( (T1ReadLong(MMU.MMU_MEM[1][0x40], 0x1A4) & 0xFFFF) | ((u32) val << 16));
|
||||
return;
|
||||
#ifdef DSI_NEWWRAM
|
||||
case REG_NWRAM_CTRL_SET0BANK0:
|
||||
case REG_NWRAM_CTRL_SET0BANK1:
|
||||
case REG_NWRAM_CTRL_SET0BANK2:
|
||||
case REG_NWRAM_CTRL_SET0BANK3:
|
||||
case REG_NWRAM_CTRL_SET1BANK0:
|
||||
case REG_NWRAM_CTRL_SET1BANK1:
|
||||
case REG_NWRAM_CTRL_SET1BANK2:
|
||||
case REG_NWRAM_CTRL_SET1BANK3:
|
||||
case REG_NWRAM_CTRL_SET1BANK4:
|
||||
case REG_NWRAM_CTRL_SET1BANK5:
|
||||
case REG_NWRAM_CTRL_SET1BANK6:
|
||||
case REG_NWRAM_CTRL_SET1BANK7:
|
||||
case REG_NWRAM_CTRL_SET2BANK0:
|
||||
case REG_NWRAM_CTRL_SET2BANK1:
|
||||
case REG_NWRAM_CTRL_SET2BANK2:
|
||||
case REG_NWRAM_CTRL_SET2BANK3:
|
||||
case REG_NWRAM_CTRL_SET2BANK4:
|
||||
case REG_NWRAM_CTRL_SET2BANK5:
|
||||
case REG_NWRAM_CTRL_SET2BANK6:
|
||||
case REG_NWRAM_CTRL_SET2BANK7:
|
||||
/* These registers can not be changed by the arm7, as of a fuse bit in SCFG
|
||||
TODO: If that SFCG is implemented this might get writeable */
|
||||
return;
|
||||
case REG_NWRAM_WINDOW_SET0:
|
||||
case REG_NWRAM_WINDOW_SET0 + 1:
|
||||
case REG_NWRAM_WINDOW_SET0 + 2:
|
||||
case REG_NWRAM_WINDOW_SET0 + 3:
|
||||
case REG_NWRAM_WINDOW_SET1:
|
||||
case REG_NWRAM_WINDOW_SET1 + 1:
|
||||
case REG_NWRAM_WINDOW_SET1 + 2:
|
||||
case REG_NWRAM_WINDOW_SET1 + 3:
|
||||
case REG_NWRAM_WINDOW_SET2:
|
||||
case REG_NWRAM_WINDOW_SET2 + 1:
|
||||
case REG_NWRAM_WINDOW_SET2 + 2:
|
||||
case REG_NWRAM_WINDOW_SET2 + 3:
|
||||
MMU.regNWRAM_Windows[0][(adr - REG_NWRAM_WINDOW_SET0) >> 2] &= ~(0xffff << ((adr & 2) * 8));
|
||||
MMU.regNWRAM_Windows[0][(adr - REG_NWRAM_WINDOW_SET0) >> 2] |= (val << ((adr & 2) * 8));
|
||||
MMU_UpdateNWRAM();
|
||||
return;
|
||||
case REG_NWRAM_PROTECT:
|
||||
case REG_NWRAM_PROTECT + 1:
|
||||
case REG_NWRAM_PROTECT + 2:
|
||||
case REG_NWRAM_PROTECT + 3:
|
||||
MMU.regNWRAM_Protect &= ~(0xffff << ((adr & 2) * 8));
|
||||
MMU.regNWRAM_Protect |= (val << ((adr & 2) * 8));
|
||||
return;
|
||||
#endif
|
||||
}
|
||||
|
||||
T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][adr>>20], adr&MMU.MMU_MASK[ARMCPU_ARM7][adr>>20], val);
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
#ifdef DSI_NEWWRAM
|
||||
if ((adr >> 24) == 0x03)
|
||||
{
|
||||
if (MMU.NWRAMBLOCKPTRS[0][(adr - 0x03000000) / 0x8000])
|
||||
{
|
||||
T1WriteWord(MMU.NWRAMBLOCKPTRS[0][(adr - 0x03000000) / 0x8000], adr & 0x7fff, val);
|
||||
return;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
bool unmapped, restricted;
|
||||
adr = MMU_LCDmap<ARMCPU_ARM7>(adr,unmapped, restricted);
|
||||
if(unmapped) return;
|
||||
|
|
@ -5867,11 +6382,68 @@ void FASTCALL _MMU_ARM7_write32(u32 adr, u32 val)
|
|||
case REG_GCDATAIN:
|
||||
MMU_writeToGC<ARMCPU_ARM7>(val);
|
||||
return;
|
||||
#ifdef DSI_NEWWRAM
|
||||
case REG_NWRAM_CTRL_SET0BANK0:
|
||||
case REG_NWRAM_CTRL_SET0BANK1:
|
||||
case REG_NWRAM_CTRL_SET0BANK2:
|
||||
case REG_NWRAM_CTRL_SET0BANK3:
|
||||
case REG_NWRAM_CTRL_SET1BANK0:
|
||||
case REG_NWRAM_CTRL_SET1BANK1:
|
||||
case REG_NWRAM_CTRL_SET1BANK2:
|
||||
case REG_NWRAM_CTRL_SET1BANK3:
|
||||
case REG_NWRAM_CTRL_SET1BANK4:
|
||||
case REG_NWRAM_CTRL_SET1BANK5:
|
||||
case REG_NWRAM_CTRL_SET1BANK6:
|
||||
case REG_NWRAM_CTRL_SET1BANK7:
|
||||
case REG_NWRAM_CTRL_SET2BANK0:
|
||||
case REG_NWRAM_CTRL_SET2BANK1:
|
||||
case REG_NWRAM_CTRL_SET2BANK2:
|
||||
case REG_NWRAM_CTRL_SET2BANK3:
|
||||
case REG_NWRAM_CTRL_SET2BANK4:
|
||||
case REG_NWRAM_CTRL_SET2BANK5:
|
||||
case REG_NWRAM_CTRL_SET2BANK6:
|
||||
case REG_NWRAM_CTRL_SET2BANK7:
|
||||
/* These registers can not be changed by the arm7, as of a fuse bit in SCFG
|
||||
TODO: If that SFCG is implemented this might get writeable */
|
||||
return;
|
||||
case REG_NWRAM_WINDOW_SET0:
|
||||
case REG_NWRAM_WINDOW_SET0 + 1:
|
||||
case REG_NWRAM_WINDOW_SET0 + 2:
|
||||
case REG_NWRAM_WINDOW_SET0 + 3:
|
||||
case REG_NWRAM_WINDOW_SET1:
|
||||
case REG_NWRAM_WINDOW_SET1 + 1:
|
||||
case REG_NWRAM_WINDOW_SET1 + 2:
|
||||
case REG_NWRAM_WINDOW_SET1 + 3:
|
||||
case REG_NWRAM_WINDOW_SET2:
|
||||
case REG_NWRAM_WINDOW_SET2 + 1:
|
||||
case REG_NWRAM_WINDOW_SET2 + 2:
|
||||
case REG_NWRAM_WINDOW_SET2 + 3:
|
||||
MMU.regNWRAM_Windows[0][(adr - REG_NWRAM_WINDOW_SET0) >> 2] = val;
|
||||
MMU_UpdateNWRAM();
|
||||
return;
|
||||
case REG_NWRAM_PROTECT:
|
||||
case REG_NWRAM_PROTECT + 1:
|
||||
case REG_NWRAM_PROTECT + 2:
|
||||
case REG_NWRAM_PROTECT + 3:
|
||||
MMU.regNWRAM_Protect = val;
|
||||
return;
|
||||
#endif
|
||||
}
|
||||
T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM7][adr>>20], adr & MMU.MMU_MASK[ARMCPU_ARM7][adr>>20], val);
|
||||
return;
|
||||
}
|
||||
|
||||
#ifdef DSI_NEWWRAM
|
||||
if ((adr >> 24) == 0x03)
|
||||
{
|
||||
if (MMU.NWRAMBLOCKPTRS[0][(adr - 0x03000000) / 0x8000])
|
||||
{
|
||||
T1WriteLong(MMU.NWRAMBLOCKPTRS[0][(adr - 0x03000000) / 0x8000], adr & 0x7fff, val);
|
||||
return;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
bool unmapped, restricted;
|
||||
adr = MMU_LCDmap<ARMCPU_ARM7>(adr,unmapped, restricted);
|
||||
if(unmapped) return;
|
||||
|
|
@ -5959,11 +6531,60 @@ u8 FASTCALL _MMU_ARM7_read08(u32 adr)
|
|||
case REG_TM3CNTL+1: return _MMU_ARM7_read16(adr-1)>>8;
|
||||
case REG_TM3CNTL+2: return _MMU_ARM7_read16(adr);
|
||||
case REG_TM3CNTL+3: return _MMU_ARM7_read16(adr-1)>>8;
|
||||
#ifdef DSI_NEWWRAM
|
||||
case REG_NWRAM_CTRL_SET0BANK0:
|
||||
case REG_NWRAM_CTRL_SET0BANK1:
|
||||
case REG_NWRAM_CTRL_SET0BANK2:
|
||||
case REG_NWRAM_CTRL_SET0BANK3:
|
||||
case REG_NWRAM_CTRL_SET1BANK0:
|
||||
case REG_NWRAM_CTRL_SET1BANK1:
|
||||
case REG_NWRAM_CTRL_SET1BANK2:
|
||||
case REG_NWRAM_CTRL_SET1BANK3:
|
||||
case REG_NWRAM_CTRL_SET1BANK4:
|
||||
case REG_NWRAM_CTRL_SET1BANK5:
|
||||
case REG_NWRAM_CTRL_SET1BANK6:
|
||||
case REG_NWRAM_CTRL_SET1BANK7:
|
||||
case REG_NWRAM_CTRL_SET2BANK0:
|
||||
case REG_NWRAM_CTRL_SET2BANK1:
|
||||
case REG_NWRAM_CTRL_SET2BANK2:
|
||||
case REG_NWRAM_CTRL_SET2BANK3:
|
||||
case REG_NWRAM_CTRL_SET2BANK4:
|
||||
case REG_NWRAM_CTRL_SET2BANK5:
|
||||
case REG_NWRAM_CTRL_SET2BANK6:
|
||||
case REG_NWRAM_CTRL_SET2BANK7:
|
||||
return MMU.regNRWAM_BankControl[adr - REG_NWRAM_CTRL_SET0BANK0];
|
||||
case REG_NWRAM_WINDOW_SET0:
|
||||
case REG_NWRAM_WINDOW_SET0 + 1:
|
||||
case REG_NWRAM_WINDOW_SET0 + 2:
|
||||
case REG_NWRAM_WINDOW_SET0 + 3:
|
||||
case REG_NWRAM_WINDOW_SET1:
|
||||
case REG_NWRAM_WINDOW_SET1 + 1:
|
||||
case REG_NWRAM_WINDOW_SET1 + 2:
|
||||
case REG_NWRAM_WINDOW_SET1 + 3:
|
||||
case REG_NWRAM_WINDOW_SET2:
|
||||
case REG_NWRAM_WINDOW_SET2 + 1:
|
||||
case REG_NWRAM_WINDOW_SET2 + 2:
|
||||
case REG_NWRAM_WINDOW_SET2 + 3:
|
||||
return (MMU.regNWRAM_Windows[0][(adr - REG_NWRAM_WINDOW_SET0) >> 2] >> ((adr & 3) * 8)) & 0xff;
|
||||
case REG_NWRAM_PROTECT:
|
||||
case REG_NWRAM_PROTECT + 1:
|
||||
case REG_NWRAM_PROTECT + 2:
|
||||
case REG_NWRAM_PROTECT + 3:
|
||||
return (MMU.regNWRAM_Protect >> ((adr & 3) * 8)) & 0xff;
|
||||
#endif
|
||||
}
|
||||
|
||||
return MMU.MMU_MEM[ARMCPU_ARM7][adr>>20][adr&MMU.MMU_MASK[ARMCPU_ARM7][adr>>20]];
|
||||
}
|
||||
|
||||
#ifdef DSI_NEWWRAM
|
||||
if ((adr >> 24) == 0x03)
|
||||
{
|
||||
if (MMU.NWRAMBLOCKPTRS[0][(adr - 0x03000000) / 0x8000])
|
||||
return MMU.NWRAMBLOCKPTRS[0][(adr - 0x03000000) / 0x8000][adr & 0x7fff];
|
||||
}
|
||||
#endif
|
||||
|
||||
bool unmapped, restricted;
|
||||
adr = MMU_LCDmap<ARMCPU_ARM7>(adr,unmapped, restricted);
|
||||
if(unmapped) return 0;
|
||||
|
|
@ -6044,10 +6665,58 @@ u16 FASTCALL _MMU_ARM7_read16(u32 adr)
|
|||
//since the arm7 polls this (and EXTKEYIN) every frame, we shouldnt count this as an input check
|
||||
//LagFrameFlag=0;
|
||||
break;
|
||||
#ifdef DSI_NEWWRAM
|
||||
case REG_NWRAM_CTRL_SET0BANK0:
|
||||
case REG_NWRAM_CTRL_SET0BANK1:
|
||||
case REG_NWRAM_CTRL_SET0BANK2:
|
||||
case REG_NWRAM_CTRL_SET0BANK3:
|
||||
case REG_NWRAM_CTRL_SET1BANK0:
|
||||
case REG_NWRAM_CTRL_SET1BANK1:
|
||||
case REG_NWRAM_CTRL_SET1BANK2:
|
||||
case REG_NWRAM_CTRL_SET1BANK3:
|
||||
case REG_NWRAM_CTRL_SET1BANK4:
|
||||
case REG_NWRAM_CTRL_SET1BANK5:
|
||||
case REG_NWRAM_CTRL_SET1BANK6:
|
||||
case REG_NWRAM_CTRL_SET1BANK7:
|
||||
case REG_NWRAM_CTRL_SET2BANK0:
|
||||
case REG_NWRAM_CTRL_SET2BANK1:
|
||||
case REG_NWRAM_CTRL_SET2BANK2:
|
||||
case REG_NWRAM_CTRL_SET2BANK3:
|
||||
case REG_NWRAM_CTRL_SET2BANK4:
|
||||
case REG_NWRAM_CTRL_SET2BANK5:
|
||||
case REG_NWRAM_CTRL_SET2BANK6:
|
||||
return MMU.regNRWAM_BankControl[adr - REG_NWRAM_CTRL_SET0BANK0] | (MMU.regNRWAM_BankControl[adr + 1 - REG_NWRAM_CTRL_SET0BANK0] << 8);
|
||||
case REG_NWRAM_WINDOW_SET0:
|
||||
case REG_NWRAM_WINDOW_SET0 + 1:
|
||||
case REG_NWRAM_WINDOW_SET0 + 2:
|
||||
case REG_NWRAM_WINDOW_SET0 + 3:
|
||||
case REG_NWRAM_WINDOW_SET1:
|
||||
case REG_NWRAM_WINDOW_SET1 + 1:
|
||||
case REG_NWRAM_WINDOW_SET1 + 2:
|
||||
case REG_NWRAM_WINDOW_SET1 + 3:
|
||||
case REG_NWRAM_WINDOW_SET2:
|
||||
case REG_NWRAM_WINDOW_SET2 + 1:
|
||||
case REG_NWRAM_WINDOW_SET2 + 2:
|
||||
case REG_NWRAM_WINDOW_SET2 + 3:
|
||||
return (MMU.regNWRAM_Windows[0][(adr - REG_NWRAM_WINDOW_SET0) >> 2] >> ((adr & 2) * 8)) & 0xffff;
|
||||
case REG_NWRAM_PROTECT:
|
||||
case REG_NWRAM_PROTECT + 1:
|
||||
case REG_NWRAM_PROTECT + 2:
|
||||
case REG_NWRAM_PROTECT + 3:
|
||||
return (MMU.regNWRAM_Protect >> ((adr & 2) * 8)) & 0xffff;
|
||||
#endif
|
||||
}
|
||||
return T1ReadWord_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM7][adr>>20], adr & MMU.MMU_MASK[ARMCPU_ARM7][adr>>20]);
|
||||
}
|
||||
|
||||
#ifdef DSI_NEWWRAM
|
||||
if ((adr >> 24) == 0x03)
|
||||
{
|
||||
if (MMU.NWRAMBLOCKPTRS[0][(adr - 0x03000000) / 0x8000])
|
||||
return T1ReadWord_guaranteedAligned(MMU.NWRAMBLOCKPTRS[0][(adr - 0x03000000) / 0x8000], adr & 0x7fff);
|
||||
}
|
||||
#endif
|
||||
|
||||
bool unmapped, restricted;
|
||||
adr = MMU_LCDmap<ARMCPU_ARM7>(adr,unmapped, restricted);
|
||||
if(unmapped) return 0;
|
||||
|
|
@ -6125,11 +6794,58 @@ u32 FASTCALL _MMU_ARM7_read32(u32 adr)
|
|||
//make sure WRAMSTAT is stashed and then fallthrough return the value from memory. i know, gross.
|
||||
T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x241, MMU.WRAMCNT);
|
||||
break;
|
||||
#ifdef DSI_NEWWRAM
|
||||
case REG_NWRAM_CTRL_SET0BANK0:
|
||||
case REG_NWRAM_CTRL_SET0BANK1:
|
||||
case REG_NWRAM_CTRL_SET0BANK2:
|
||||
case REG_NWRAM_CTRL_SET0BANK3:
|
||||
case REG_NWRAM_CTRL_SET1BANK0:
|
||||
case REG_NWRAM_CTRL_SET1BANK1:
|
||||
case REG_NWRAM_CTRL_SET1BANK2:
|
||||
case REG_NWRAM_CTRL_SET1BANK3:
|
||||
case REG_NWRAM_CTRL_SET1BANK4:
|
||||
case REG_NWRAM_CTRL_SET1BANK5:
|
||||
case REG_NWRAM_CTRL_SET1BANK6:
|
||||
case REG_NWRAM_CTRL_SET1BANK7:
|
||||
case REG_NWRAM_CTRL_SET2BANK0:
|
||||
case REG_NWRAM_CTRL_SET2BANK1:
|
||||
case REG_NWRAM_CTRL_SET2BANK2:
|
||||
case REG_NWRAM_CTRL_SET2BANK3:
|
||||
case REG_NWRAM_CTRL_SET2BANK4:
|
||||
return MMU.regNRWAM_BankControl[adr - REG_NWRAM_CTRL_SET0BANK0] | (MMU.regNRWAM_BankControl[adr + 1 - REG_NWRAM_CTRL_SET0BANK0] << 8)
|
||||
| (MMU.regNRWAM_BankControl[adr + 2 - REG_NWRAM_CTRL_SET0BANK0] << 16) | (MMU.regNRWAM_BankControl[adr + 3 - REG_NWRAM_CTRL_SET0BANK0] << 24);
|
||||
case REG_NWRAM_WINDOW_SET0:
|
||||
case REG_NWRAM_WINDOW_SET0 + 1:
|
||||
case REG_NWRAM_WINDOW_SET0 + 2:
|
||||
case REG_NWRAM_WINDOW_SET0 + 3:
|
||||
case REG_NWRAM_WINDOW_SET1:
|
||||
case REG_NWRAM_WINDOW_SET1 + 1:
|
||||
case REG_NWRAM_WINDOW_SET1 + 2:
|
||||
case REG_NWRAM_WINDOW_SET1 + 3:
|
||||
case REG_NWRAM_WINDOW_SET2:
|
||||
case REG_NWRAM_WINDOW_SET2 + 1:
|
||||
case REG_NWRAM_WINDOW_SET2 + 2:
|
||||
case REG_NWRAM_WINDOW_SET2 + 3:
|
||||
return MMU.regNWRAM_Windows[1][(adr - REG_NWRAM_WINDOW_SET0) >> 2];
|
||||
case REG_NWRAM_PROTECT:
|
||||
case REG_NWRAM_PROTECT + 1:
|
||||
case REG_NWRAM_PROTECT + 2:
|
||||
case REG_NWRAM_PROTECT + 3:
|
||||
return MMU.regNWRAM_Protect;
|
||||
#endif
|
||||
}
|
||||
|
||||
return T1ReadLong_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM7][adr>>20], adr & MMU.MMU_MASK[ARMCPU_ARM7][adr>>20]);
|
||||
}
|
||||
|
||||
#ifdef DSI_NEWWRAM
|
||||
if ((adr >> 24) == 0x03)
|
||||
{
|
||||
if (MMU.NWRAMBLOCKPTRS[0][(adr - 0x03000000) / 0x8000])
|
||||
return T1ReadLong_guaranteedAligned(MMU.NWRAMBLOCKPTRS[0][(adr - 0x03000000) / 0x8000], adr & 0x7fff);
|
||||
}
|
||||
#endif
|
||||
|
||||
bool unmapped, restricted;
|
||||
adr = MMU_LCDmap<ARMCPU_ARM7>(adr,unmapped, restricted);
|
||||
if(unmapped) return 0;
|
||||
|
|
@ -6139,6 +6855,96 @@ u32 FASTCALL _MMU_ARM7_read32(u32 adr)
|
|||
return T1ReadLong_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM7][adr >> 20], adr & MMU.MMU_MASK[ARMCPU_ARM7][adr >> 20]);
|
||||
}
|
||||
|
||||
#ifdef DSI_NEWWRAM
|
||||
|
||||
|
||||
#pragma optimize( "g", off)
|
||||
//================================================= MMU Update new WRAM Mapping
|
||||
void FASTCALL MMU_UpdateNWRAM()
|
||||
{
|
||||
// move through all 32k Blocks in the 0x03000000 to 0x03FFFFFF range. The range consists of 512 blocks
|
||||
// and check where the data for the arm7/arm9 shall point to
|
||||
// TODO: This does not work when blending NWRAM into the HW Register range
|
||||
uint32_t blockLimits[12];
|
||||
uint32_t arm9BlockLimits[6];
|
||||
|
||||
// pre calculate the window limits in 32k Blocks for each core and window
|
||||
for (int i = 0; i < 2; i++)
|
||||
{
|
||||
blockLimits[i * 6 + 0] = (MMU.regNWRAM_Windows[i][0] & 0x0FF0) >> 3;
|
||||
blockLimits[i * 6 + 2] = (MMU.regNWRAM_Windows[i][1] & 0x0FF8) >> 3;
|
||||
blockLimits[i * 6 + 4] = (MMU.regNWRAM_Windows[i][2] & 0x0FF8) >> 3;
|
||||
blockLimits[i * 6 + 1] = (MMU.regNWRAM_Windows[i][0] & 0x0FF00000) >> 19;
|
||||
blockLimits[i * 6 + 3] = (MMU.regNWRAM_Windows[i][1] & 0x0FF80000) >> 19;
|
||||
blockLimits[i * 6 + 5] = (MMU.regNWRAM_Windows[i][2] & 0x0FF80000) >> 19;
|
||||
}
|
||||
|
||||
// now check every block in the 0x03... range to which nwram page it belongs
|
||||
for (int block = 0; block < 512; block++)
|
||||
{
|
||||
for (int core = 0; core < 2; core++)
|
||||
{
|
||||
u8* data = 0;
|
||||
for (int set = 0; (set < 3) && (data == 0); set++)
|
||||
{
|
||||
// for each of the 3 sets
|
||||
if ((block >= blockLimits[core * 6 + set * 2]) && (block < blockLimits[core * 6 + set * 2 + 1]))
|
||||
{
|
||||
// This set is blended in at this region
|
||||
uint8_t sectorLength = (MMU.regNWRAM_Windows[core][set] >> 12) & 0x03;
|
||||
// the first set does not know an image size of 32kB (0) and will default to 64kB (1)
|
||||
if ((sectorLength == 0) && (set == 0))
|
||||
sectorLength = 1;
|
||||
uint8_t sectorBlocks = 1 << sectorLength;
|
||||
uint8_t sectorPart = block & (sectorBlocks - 1);
|
||||
// now iterate through all banks in the set and check if it is
|
||||
// enabled & assigned to the core
|
||||
if (set == 0)
|
||||
{
|
||||
// the set A is special as it combines two 32kB blocks into a single 64kB Block
|
||||
// therefor we have only 4 bank controls which are matching for 2 blocks each
|
||||
for (int bank = 0; bank < 4; bank++)
|
||||
{
|
||||
if (!(MMU.regNRWAM_BankControl[bank] & 0x80)) // not enabled
|
||||
continue;
|
||||
if ((MMU.regNRWAM_BankControl[bank] & 0x03) != (1 - core)) // assigned to dsp or different core
|
||||
continue;
|
||||
if (((MMU.regNRWAM_BankControl[bank] >> 2) & 6) != (sectorPart & ~1))
|
||||
continue;
|
||||
// when this is reached, the current block is found in this set for this core
|
||||
// So remember the data it shall point to
|
||||
// for the first set the parts are of 2 blocks
|
||||
data = &MMU.NWRAM[set][bank | (sectorPart & 1)][0];
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
// otherwise it is a regular set with each 32kB block having its own bank control register
|
||||
for (int bank = 0; bank < 8; bank++)
|
||||
{
|
||||
if (!(MMU.regNRWAM_BankControl[bank + set * 8 - 4] & 0x80)) // not enabled
|
||||
continue;
|
||||
if ((MMU.regNRWAM_BankControl[bank + set * 8 - 4] & 0x03) != (1 - core)) // assigned to dsp or different core
|
||||
continue;
|
||||
if (((MMU.regNRWAM_BankControl[bank + set * 8 - 4] >> 2) & 7) != sectorPart)
|
||||
continue;
|
||||
// when this is reached, the current block is found in this set for this core
|
||||
// So remember the data it shall point to
|
||||
// for the first set the parts are of 2 blocks
|
||||
data = &MMU.NWRAM[set][bank][0];
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
MMU.NWRAMBLOCKPTRS[core][block] = data;
|
||||
}
|
||||
}
|
||||
// TODO
|
||||
}
|
||||
#pragma optimize( "g", on)
|
||||
|
||||
#endif
|
||||
|
||||
//=========================================================================================================
|
||||
|
||||
u32 FASTCALL MMU_read32(u32 proc, u32 adr)
|
||||
|
|
|
|||
|
|
@ -406,6 +406,25 @@ struct MMU_struct
|
|||
//32KB of shared WRAM - can be switched between ARM7 & ARM9 in two blocks
|
||||
u8 SWIRAM[0x8000];
|
||||
|
||||
#ifdef DSI_NEWWRAM
|
||||
// new shared WRAM, 3 banks, each of 256k
|
||||
// smallest chunk to blend in is 32k
|
||||
u8 NWRAM[3][8][32 * 1024];
|
||||
|
||||
// Control register for each bank (named MBK?.? in gbatek)
|
||||
u8 regNRWAM_BankControl[20];
|
||||
// Window control registers. One set of 3 for each core
|
||||
u32 regNWRAM_Windows[2][3];
|
||||
// Bank control write protection register
|
||||
u32 regNWRAM_Protect;
|
||||
|
||||
// Pointer for each block of the region from 0x03000000 to 0x03ffffff
|
||||
// for each core. This way the memory lookup must not calculate the effective
|
||||
// WRAM address on each access but prepares these pointers only when the
|
||||
// window or bank registers changed.
|
||||
u8* NWRAMBLOCKPTRS[2][512] ;
|
||||
#endif
|
||||
|
||||
//Unused ram
|
||||
u8 UNUSED_RAM[4];
|
||||
|
||||
|
|
|
|||
|
|
@ -57,6 +57,11 @@
|
|||
<Import Project="desmume.props" />
|
||||
</ImportGroup>
|
||||
<PropertyGroup Label="UserMacros" />
|
||||
<ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='Release|x64'">
|
||||
<ClCompile>
|
||||
<PreprocessorDefinitions>HAVE_LIBAGG=1;HAVE_JIT=1;HAVE_LUA=1;%(PreprocessorDefinitions);DSI_NEWWRAM</PreprocessorDefinitions>
|
||||
</ClCompile>
|
||||
</ItemDefinitionGroup>
|
||||
<ItemGroup>
|
||||
<ClCompile Include="..\..\addons\slot1comp_mc.cpp" />
|
||||
<ClCompile Include="..\..\addons\slot1comp_protocol.cpp" />
|
||||
|
|
|
|||
|
|
@ -229,7 +229,122 @@ IOReg IORegs9[] = {
|
|||
{"DMA 1",9,1},{"DMA 2",10,1},{"DMA 3",11,1},{"Keypad",12,1},
|
||||
{"Game Pak",13,1},{"IPC sync",16,1},{"IPC send FIFO empty",17,1},{"IPC recv FIFO not empty",18,1},
|
||||
{"Gamecard transfer",19,1},{"Gamecard IREQ_MC",20,1},{"GX FIFO",21,1}}},
|
||||
|
||||
#ifdef DSI_NEWWRAM
|
||||
{ CatBegin, "NWRAM registers", 0, 4, 0, {{0}} },
|
||||
{ MMIOReg, "NWRAMCTRL_S0B0", REG_NWRAM_CTRL_SET0BANK0, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}} },
|
||||
{ MMIOReg, "NWRAMCTRL_S0B1", REG_NWRAM_CTRL_SET0BANK1, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}} },
|
||||
{ MMIOReg, "NWRAMCTRL_S0B2", REG_NWRAM_CTRL_SET0BANK2, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}} },
|
||||
{ MMIOReg, "NWRAMCTRL_S0B3", REG_NWRAM_CTRL_SET0BANK3, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}} },
|
||||
{ MMIOReg, "NWRAMCTRL_S1B0", REG_NWRAM_CTRL_SET0BANK0, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}} },
|
||||
{ MMIOReg, "NWRAMCTRL_S1B1", REG_NWRAM_CTRL_SET1BANK1, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}} },
|
||||
{ MMIOReg, "NWRAMCTRL_S1B2", REG_NWRAM_CTRL_SET1BANK2, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}} },
|
||||
{ MMIOReg, "NWRAMCTRL_S1B3", REG_NWRAM_CTRL_SET1BANK3, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}} },
|
||||
{ MMIOReg, "NWRAMCTRL_S1B4", REG_NWRAM_CTRL_SET1BANK4, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}} },
|
||||
{ MMIOReg, "NWRAMCTRL_S1B5", REG_NWRAM_CTRL_SET1BANK5, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}} },
|
||||
{ MMIOReg, "NWRAMCTRL_S1B6", REG_NWRAM_CTRL_SET1BANK6, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}} },
|
||||
{ MMIOReg, "NWRAMCTRL_S1B7", REG_NWRAM_CTRL_SET1BANK7, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}} },
|
||||
{ MMIOReg, "NWRAMCTRL_S2B0", REG_NWRAM_CTRL_SET1BANK0, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}} },
|
||||
{ MMIOReg, "NWRAMCTRL_S2B1", REG_NWRAM_CTRL_SET1BANK1, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}} },
|
||||
{ MMIOReg, "NWRAMCTRL_S2B2", REG_NWRAM_CTRL_SET1BANK2, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}} },
|
||||
{ MMIOReg, "NWRAMCTRL_S2B3", REG_NWRAM_CTRL_SET1BANK3, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}} },
|
||||
{ MMIOReg, "NWRAMCTRL_S2B4", REG_NWRAM_CTRL_SET1BANK4, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}} },
|
||||
{ MMIOReg, "NWRAMCTRL_S2B5", REG_NWRAM_CTRL_SET1BANK5, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}} },
|
||||
{ MMIOReg, "NWRAMCTRL_S2B6", REG_NWRAM_CTRL_SET1BANK6, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}} },
|
||||
{ MMIOReg, "NWRAMCTRL_S2B7", REG_NWRAM_CTRL_SET1BANK7, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}} },
|
||||
{ MMIOReg, "NWRAMCTRL_WINDOW_0", REG_NWRAM_WINDOW_SET0, 4, 3, {
|
||||
{"Start block", 3, 8},
|
||||
{"End Block", 19, 10},
|
||||
{"Image Size", 12, 2}} },
|
||||
{ MMIOReg, "NWRAMCTRL_WINDOW_1", REG_NWRAM_WINDOW_SET1, 4, 3, {
|
||||
{"Start block", 3, 8},
|
||||
{"End Block", 19, 10},
|
||||
{"Image Size", 12, 2}} },
|
||||
{ MMIOReg, "NWRAMCTRL_WINDOW_2", REG_NWRAM_WINDOW_SET2, 4, 3, {
|
||||
{"Start block", 3, 8},
|
||||
{"End Block", 19, 10},
|
||||
{"Image Size", 12, 2}} },
|
||||
{ MMIOReg, "NWRAMCTRL_PROTECT", REG_NWRAM_PROTECT, 4, 20, {
|
||||
{"Set 0 Part 0 Protected", 0, 1},
|
||||
{"Set 0 Part 1 Protected", 1, 1},
|
||||
{"Set 0 Part 2 Protected", 2, 1},
|
||||
{"Set 0 Part 3 Protected", 3, 1},
|
||||
{"Set 1 Part 0 Protected", 8, 1},
|
||||
{"Set 1 Part 1 Protected", 9, 1},
|
||||
{"Set 1 Part 2 Protected", 10, 1},
|
||||
{"Set 1 Part 3 Protected", 11, 1},
|
||||
{"Set 1 Part 4 Protected", 12, 1},
|
||||
{"Set 1 Part 5 Protected", 13, 1},
|
||||
{"Set 1 Part 6 Protected", 14, 1},
|
||||
{"Set 1 Part 7 Protected", 15, 1},
|
||||
{"Set 2 Part 0 Protected", 16, 1},
|
||||
{"Set 2 Part 1 Protected", 17, 1},
|
||||
{"Set 2 Part 2 Protected", 18, 1},
|
||||
{"Set 2 Part 3 Protected", 19, 1},
|
||||
{"Set 2 Part 4 Protected", 20, 1},
|
||||
{"Set 2 Part 5 Protected", 21, 1},
|
||||
{"Set 2 Part 6 Protected", 22, 1},
|
||||
{"Set 2 Part 7 Protected", 23, 1}} },
|
||||
#endif
|
||||
{ListEnd, "", 0, 0, 0, {{0}}}
|
||||
};
|
||||
|
||||
|
|
@ -271,8 +386,124 @@ IOReg IORegs7[] = {
|
|||
{MMIOReg, "DMA3SAD", REG_DMA3SAD, 4, 1, {{"Value",0,27}}},
|
||||
{MMIOReg, "DMA3DAD", REG_DMA3DAD, 4, 1, {{"Value",0,27}}},
|
||||
{MMIOReg, "DMA3CNT", REG_DMA3CNTL, 4, 8, {{"Word Count",0,21}, {"Dest update method",21,2}, {"Src update method",23,2}, {"Repeat Flag",25,1}, {"32bit Width Enable",26,1},{"Start Mode",28,2}, {"IRQ Enable",30,1}, {"Enabled",31,1}}},
|
||||
|
||||
|
||||
#ifdef DSI_NEWWRAM
|
||||
{CatBegin, "NWRAM registers", 0, 4, 0, {{0}}},
|
||||
{MMIOReg, "NWRAMCTRL_S0B0", REG_NWRAM_CTRL_SET0BANK0, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}}},
|
||||
{MMIOReg, "NWRAMCTRL_S0B1", REG_NWRAM_CTRL_SET0BANK1, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}}},
|
||||
{MMIOReg, "NWRAMCTRL_S0B2", REG_NWRAM_CTRL_SET0BANK2, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}}},
|
||||
{MMIOReg, "NWRAMCTRL_S0B3", REG_NWRAM_CTRL_SET0BANK3, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}}},
|
||||
{MMIOReg, "NWRAMCTRL_S1B0", REG_NWRAM_CTRL_SET0BANK0, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}}},
|
||||
{MMIOReg, "NWRAMCTRL_S1B1", REG_NWRAM_CTRL_SET1BANK1, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}}},
|
||||
{MMIOReg, "NWRAMCTRL_S1B2", REG_NWRAM_CTRL_SET1BANK2, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}}},
|
||||
{MMIOReg, "NWRAMCTRL_S1B3", REG_NWRAM_CTRL_SET1BANK3, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}}},
|
||||
{MMIOReg, "NWRAMCTRL_S1B4", REG_NWRAM_CTRL_SET1BANK4, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}}},
|
||||
{MMIOReg, "NWRAMCTRL_S1B5", REG_NWRAM_CTRL_SET1BANK5, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}}},
|
||||
{MMIOReg, "NWRAMCTRL_S1B6", REG_NWRAM_CTRL_SET1BANK6, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}}},
|
||||
{MMIOReg, "NWRAMCTRL_S1B7", REG_NWRAM_CTRL_SET1BANK7, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}}},
|
||||
{MMIOReg, "NWRAMCTRL_S2B0", REG_NWRAM_CTRL_SET1BANK0, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}}},
|
||||
{MMIOReg, "NWRAMCTRL_S2B1", REG_NWRAM_CTRL_SET1BANK1, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}}},
|
||||
{MMIOReg, "NWRAMCTRL_S2B2", REG_NWRAM_CTRL_SET1BANK2, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}}},
|
||||
{MMIOReg, "NWRAMCTRL_S2B3", REG_NWRAM_CTRL_SET1BANK3, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}}},
|
||||
{MMIOReg, "NWRAMCTRL_S2B4", REG_NWRAM_CTRL_SET1BANK4, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}}},
|
||||
{MMIOReg, "NWRAMCTRL_S2B5", REG_NWRAM_CTRL_SET1BANK5, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}}},
|
||||
{MMIOReg, "NWRAMCTRL_S2B6", REG_NWRAM_CTRL_SET1BANK6, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}}},
|
||||
{MMIOReg, "NWRAMCTRL_S2B7", REG_NWRAM_CTRL_SET1BANK7, 1, 3, {
|
||||
{"Enable", 7, 1},
|
||||
{"Block", 2, 2},
|
||||
{"Owner", 0, 2}}},
|
||||
{ MMIOReg, "NWRAMCTRL_WINDOW_0", REG_NWRAM_WINDOW_SET0, 4, 3, {
|
||||
{"Start block", 3, 8},
|
||||
{"End Block", 19, 10},
|
||||
{"Image Size", 12, 2}} },
|
||||
{ MMIOReg, "NWRAMCTRL_WINDOW_1", REG_NWRAM_WINDOW_SET1, 4, 3, {
|
||||
{"Start block", 3, 8},
|
||||
{"End Block", 19, 10},
|
||||
{"Image Size", 12, 2}} },
|
||||
{ MMIOReg, "NWRAMCTRL_WINDOW_2", REG_NWRAM_WINDOW_SET2, 4, 3, {
|
||||
{"Start block", 3, 8},
|
||||
{"End Block", 19, 10},
|
||||
{"Image Size", 12, 2}} },
|
||||
{ MMIOReg, "NWRAMCTRL_PROTECT", REG_NWRAM_PROTECT, 4, 20, {
|
||||
{"Set 0 Part 0 Protected", 0, 1},
|
||||
{"Set 0 Part 1 Protected", 1, 1},
|
||||
{"Set 0 Part 2 Protected", 2, 1},
|
||||
{"Set 0 Part 3 Protected", 3, 1},
|
||||
{"Set 1 Part 0 Protected", 8, 1},
|
||||
{"Set 1 Part 1 Protected", 9, 1},
|
||||
{"Set 1 Part 2 Protected", 10, 1},
|
||||
{"Set 1 Part 3 Protected", 11, 1},
|
||||
{"Set 1 Part 4 Protected", 12, 1},
|
||||
{"Set 1 Part 5 Protected", 13, 1},
|
||||
{"Set 1 Part 6 Protected", 14, 1},
|
||||
{"Set 1 Part 7 Protected", 15, 1},
|
||||
{"Set 2 Part 0 Protected", 16, 1},
|
||||
{"Set 2 Part 1 Protected", 17, 1},
|
||||
{"Set 2 Part 2 Protected", 18, 1},
|
||||
{"Set 2 Part 3 Protected", 19, 1},
|
||||
{"Set 2 Part 4 Protected", 20, 1},
|
||||
{"Set 2 Part 5 Protected", 21, 1},
|
||||
{"Set 2 Part 6 Protected", 22, 1},
|
||||
{"Set 2 Part 7 Protected", 23, 1}} },
|
||||
#endif
|
||||
|
||||
|
||||
{ListEnd, "", 0, 0, 0, {{0}}}
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -87,7 +87,7 @@ void GetINIPath()
|
|||
}
|
||||
|
||||
FCEUD_MakePathDirs(IniName);
|
||||
wcscpy(IniNameW,mbstowcs(IniName).c_str()); //careful to use locale C-style mbstowcs to get IniName (which is with locale encoding) to unicode
|
||||
wcscpy(IniNameW,mbstowcs_locale(IniName).c_str());
|
||||
|
||||
//write BOM to get unicode
|
||||
FILE* test = fopen(IniName,"rb");
|
||||
|
|
|
|||
|
|
@ -20,6 +20,8 @@
|
|||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#define _XOPEN_SOURCE 500 /* For strdup, realpath */
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <boolean.h>
|
||||
#include <string.h>
|
||||
|
|
|
|||
|
|
@ -170,7 +170,7 @@ void createDirectoryRecursively(std::wstring path)
|
|||
|
||||
void FCEUD_MakePathDirs(const char *fname)
|
||||
{
|
||||
createDirectoryRecursively(mbstowcs(fname));
|
||||
createDirectoryRecursively(mbstowcs_locale(fname));
|
||||
}
|
||||
#endif
|
||||
//------------------------------
|
||||
|
|
|
|||
|
|
@ -227,6 +227,34 @@
|
|||
#define REG_DISPB_BLDY 0x04001054
|
||||
#define REG_DISPB_MASTERBRIGHT 0x0400106C
|
||||
|
||||
// NWRAM Ports
|
||||
#ifdef DSI_NEWWRAM
|
||||
#define REG_NWRAM_CTRL_SET0BANK0 0x04004040
|
||||
#define REG_NWRAM_CTRL_SET0BANK1 0x04004041
|
||||
#define REG_NWRAM_CTRL_SET0BANK2 0x04004042
|
||||
#define REG_NWRAM_CTRL_SET0BANK3 0x04004043
|
||||
#define REG_NWRAM_CTRL_SET1BANK0 0x04004044
|
||||
#define REG_NWRAM_CTRL_SET1BANK1 0x04004045
|
||||
#define REG_NWRAM_CTRL_SET1BANK2 0x04004046
|
||||
#define REG_NWRAM_CTRL_SET1BANK3 0x04004047
|
||||
#define REG_NWRAM_CTRL_SET1BANK4 0x04004048
|
||||
#define REG_NWRAM_CTRL_SET1BANK5 0x04004049
|
||||
#define REG_NWRAM_CTRL_SET1BANK6 0x0400404a
|
||||
#define REG_NWRAM_CTRL_SET1BANK7 0x0400404b
|
||||
#define REG_NWRAM_CTRL_SET2BANK0 0x0400404c
|
||||
#define REG_NWRAM_CTRL_SET2BANK1 0x0400404d
|
||||
#define REG_NWRAM_CTRL_SET2BANK2 0x0400404e
|
||||
#define REG_NWRAM_CTRL_SET2BANK3 0x0400404f
|
||||
#define REG_NWRAM_CTRL_SET2BANK4 0x04004050
|
||||
#define REG_NWRAM_CTRL_SET2BANK5 0x04004051
|
||||
#define REG_NWRAM_CTRL_SET2BANK6 0x04004052
|
||||
#define REG_NWRAM_CTRL_SET2BANK7 0x04004053
|
||||
#define REG_NWRAM_WINDOW_SET0 0x04004054
|
||||
#define REG_NWRAM_WINDOW_SET1 0x04004058
|
||||
#define REG_NWRAM_WINDOW_SET2 0x0400405c
|
||||
#define REG_NWRAM_PROTECT 0x04004060
|
||||
#endif
|
||||
|
||||
// Receive ports
|
||||
#define REG_IPCFIFORECV 0x04100000
|
||||
#define REG_GCDATAIN 0x04100010
|
||||
|
|
|
|||
|
|
@ -284,6 +284,19 @@ std::string mass_replace(const std::string &source, const std::string &victim, c
|
|||
return answer;
|
||||
}
|
||||
|
||||
std::wstring mbstowcs_locale(std::string str)
|
||||
{
|
||||
#ifdef HOST_WINDOWS
|
||||
int plenty = str.size()*4+1;
|
||||
wchar_t *wgarbage = new wchar_t[plenty];
|
||||
MultiByteToWideChar(CP_ACP, MB_PRECOMPOSED, str.data(), -1, wgarbage, plenty);
|
||||
std::wstring ret = wgarbage;
|
||||
delete[] wgarbage;
|
||||
return ret;
|
||||
#endif
|
||||
return mbstowcs(str);
|
||||
}
|
||||
|
||||
//convert a std::string to std::wstring
|
||||
std::wstring mbstowcs(std::string str)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -107,5 +107,7 @@ std::string mass_replace(const std::string &source, const std::string &victim, c
|
|||
std::wstring mbstowcs(std::string str);
|
||||
std::string wcstombs(std::wstring str);
|
||||
|
||||
std::wstring mbstowcs_locale(std::string str);
|
||||
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user