JMPP was doing two indirections : one in PData and then one again in
AddrInd, where there should only be one.
MCS-48 docs :
> The contents of the Program Memory location addressed by the
Accumulator
is used as the new page offset of the Program Counter.
i.e.
(PC 0 – 7) <- ((A))
Previous implementation caused disasm / decompiler errors such as
"Low-level Error: Could not find op at target address"
refs:
https://github.com/NationalSecurityAgency/ghidra/discussions/4818
MCS-48 just barely supports 12 bits of program counter space (4kB), but
many real-world applications use software banking to expand this,
e.g. via IO pins driving extra address lines to the external ROM.
This patch allows up to 16-bit addresses. To use this feature, simply
select the special instruction (typically ORL Pp or ANL Pp) and set a
manual Fallthrough address to the correct bank.
See GH #2423
The SEL MB0/MB1 opcodes set a DBF register but this had no effect, therefore JMP and CALL
destinations didn't take into account DBF.
This is essentially @esaulenka 's patch from
3756e1bcee
but separated from the DFB->DBF typo change, and sets the width of the new
context register to be 1 bit (doesn't need to be 2 bits)
This greatly improves analysis. The only downside is that to manually
override DBF on a single instruction, it needs to be cleared first, then
disassembled again after setting the desired DBF.
the correct syntax for [x,y] bitranges has y= # number of bits. These
three instructions affect the lower 8 bits of PC, not 7.
From MCS-48 docs:
'
MOVP A,@A
(PC: 0-7)<-(A)
(A)<-((PC))
Move data in program memory location addressed by A into A. Program
counter is restored.
'
There is similar wording for MOVP3 and JMPP.
Fixes#4810 on GH
