From 89f73857e6d91a6b0b218c3ebfb850931fd24a61 Mon Sep 17 00:00:00 2001
From: emteere <47253321+emteere@users.noreply.github.com>
Date: Wed, 1 Dec 2021 14:50:23 -0500
Subject: [PATCH] GP-1520_emteere Initial implementation of AppleSilicon AMX
instructions
---
.../Processors/AARCH64/certification.manifest | 3 +
.../AARCH64/data/languages/AARCH64.opinion | 4 +-
.../data/languages/AARCH64_AMXext.sinc | 171 ++++++++++++++++++
.../languages/AARCH64_AppleSilicon.slaspec | 6 +
.../data/languages/AARCH64instructions.sinc | 1 +
.../AARCH64/data/languages/AppleSilicon.ldefs | 18 ++
6 files changed, 201 insertions(+), 2 deletions(-)
create mode 100644 Ghidra/Processors/AARCH64/data/languages/AARCH64_AMXext.sinc
create mode 100644 Ghidra/Processors/AARCH64/data/languages/AARCH64_AppleSilicon.slaspec
create mode 100644 Ghidra/Processors/AARCH64/data/languages/AppleSilicon.ldefs
diff --git a/Ghidra/Processors/AARCH64/certification.manifest b/Ghidra/Processors/AARCH64/certification.manifest
index 3b92c67ff2..8e979fd7ef 100644
--- a/Ghidra/Processors/AARCH64/certification.manifest
+++ b/Ghidra/Processors/AARCH64/certification.manifest
@@ -8,6 +8,8 @@ data/languages/AARCH64.opinion||GHIDRA||||END|
data/languages/AARCH64.pspec||GHIDRA||||END|
data/languages/AARCH64.slaspec||GHIDRA||||END|
data/languages/AARCH64BE.slaspec||GHIDRA||||END|
+data/languages/AARCH64_AMXext.sinc||GHIDRA||||END|
+data/languages/AARCH64_AppleSilicon.slaspec||GHIDRA||||END|
data/languages/AARCH64_base_PACoptions.sinc||GHIDRA||||END|
data/languages/AARCH64_win.cspec||GHIDRA||||END|
data/languages/AARCH64base.sinc||GHIDRA||||END|
@@ -15,6 +17,7 @@ data/languages/AARCH64instructions.sinc||GHIDRA||||END|
data/languages/AARCH64ldst.sinc||GHIDRA||||END|
data/languages/AARCH64neon.sinc||GHIDRA||||END|
data/languages/AARCH64sve.sinc||GHIDRA||||END|
+data/languages/AppleSilicon.ldefs||GHIDRA||||END|
data/manuals/AARCH64.idx||GHIDRA||||END|
data/patterns/AARCH64_LE_patterns.xml||GHIDRA||||END|
data/patterns/patternconstraints.xml||GHIDRA||||END|
diff --git a/Ghidra/Processors/AARCH64/data/languages/AARCH64.opinion b/Ghidra/Processors/AARCH64/data/languages/AARCH64.opinion
index 66182662f4..40fd8d6ad3 100644
--- a/Ghidra/Processors/AARCH64/data/languages/AARCH64.opinion
+++ b/Ghidra/Processors/AARCH64/data/languages/AARCH64.opinion
@@ -3,10 +3,10 @@
-
+
-
+
diff --git a/Ghidra/Processors/AARCH64/data/languages/AARCH64_AMXext.sinc b/Ghidra/Processors/AARCH64/data/languages/AARCH64_AMXext.sinc
new file mode 100644
index 0000000000..2082b6fabb
--- /dev/null
+++ b/Ghidra/Processors/AARCH64/data/languages/AARCH64_AMXext.sinc
@@ -0,0 +1,171 @@
+#
+# Apple AARCH64 extended matrix instructions
+# Contents based on evolving information published on Web
+#
+#
+
+define pcodeop __amx_ldx;
+define pcodeop __amx_ldy;
+define pcodeop __amx_stx;
+define pcodeop __amx_sty;
+define pcodeop __amx_ldz;
+define pcodeop __amx_stz;
+define pcodeop __amx_ldzi;
+define pcodeop __amx_stzi;
+define pcodeop __amx_extrx;
+define pcodeop __amx_extry;
+define pcodeop __amx_fma64;
+define pcodeop __amx_fms64;
+define pcodeop __amx_fma32;
+define pcodeop __amx_fms32;
+define pcodeop __amx_mac16;
+define pcodeop __amx_fma16;
+define pcodeop __amx_fms16;
+define pcodeop __amx_enable;
+define pcodeop __amx_disable;
+define pcodeop __amx_vecint;
+define pcodeop __amx_vecfp;
+define pcodeop __amx_matint;
+define pcodeop __amx_matfp;
+define pcodeop __amx_genlut;
+
+
+with : ImmS_ImmR_TestSet=1 {
+
+AMXAddr: is Rd_GPR64 {
+ addr:8 = Rd_GPR64 & 0x00FFFFFFFFFFFFFF;
+ export addr;
+}
+
+AMXRegOff: is Rd_GPR64 {
+ registerOff:8 = (Rd_GPR64 >> 56) & 0x1F;
+ export registerOff;
+}
+
+AMXSize: is Rd_GPR64 {
+ local size = ((Rd_GPR64 >> 62) & 1);
+ size = zext(size == 0) * 0x40 | zext(size ==1 ) * 0x80;
+ export size;
+}
+
+:__amx_ldx Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=0 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
+{
+ __amx_ldx(Rd_GPR64);
+}
+
+:__amx_ldy Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=1 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
+{
+ __amx_ldy(Rd_GPR64);
+}
+
+:__amx_stx Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=2 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
+{
+ __amx_stx(Rd_GPR64);
+}
+
+:__amx_sty Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=3 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
+{
+ __amx_sty(Rd_GPR64);
+}
+
+:__amx_ldz Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=4 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
+{
+ __amx_ldz(Rd_GPR64);
+}
+
+:__amx_stz Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=5 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
+{
+ __amx_stz(Rd_GPR64);
+}
+
+:__amx_ldzi Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=6 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
+{
+ __amx_ldzi(Rd_GPR64);
+}
+
+:__amx_stzi Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=7 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
+{
+ __amx_stzi(Rd_GPR64);
+}
+
+:__amx_extrx Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=8 & Rd_GPR64
+{
+ __amx_extrx(Rd_GPR64);
+}
+
+:__amx_extry Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=9 & Rd_GPR64
+{
+ __amx_extry(Rd_GPR64);
+}
+
+:__amx_fma64 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=10 & Rd_GPR64
+{
+ __amx_fma64(Rd_GPR64);
+}
+
+:__amx_fms64 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=11 & Rd_GPR64
+{
+ __amx_fms64(Rd_GPR64);
+}
+
+:__amx_fma32 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=12 & Rd_GPR64
+{
+ __amx_fma32(Rd_GPR64);
+}
+
+:__amx_fms32 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=13 & Rd_GPR64
+{
+ __amx_fms32(Rd_GPR64);
+}
+
+:__amx_mac16 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=14 & Rd_GPR64
+{
+ __amx_mac16(Rd_GPR64);
+}
+
+:__amx_fma16 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=15 & Rd_GPR64
+{
+ __amx_fma16(Rd_GPR64);
+}
+
+:__amx_fms16 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=16 & Rd_GPR64
+{
+ __amx_fms16(Rd_GPR64);
+}
+
+:__amxdisable is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=17 & b_0004=1
+{
+ __amx_disable();
+}
+
+:__amxenable is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=17 & b_0004=0
+{
+ __amx_enable();
+}
+
+:__amx_vecint Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=18 & Rd_GPR64
+{
+ __amx_vecint(Rd_GPR64);
+}
+
+:__amx_vecfp Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=19 & Rd_GPR64
+{
+ __amx_vecfp(Rd_GPR64);
+}
+
+:__amx_matint Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=20 & Rd_GPR64
+{
+ __amx_matint(Rd_GPR64);
+}
+
+:__amx_matfp Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=21 & Rd_GPR64
+{
+ __amx_matfp(Rd_GPR64);
+}
+
+:__amx_genlut Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=22 & Rd_GPR64
+{
+ __amx_genlut(Rd_GPR64);
+}
+
+}
\ No newline at end of file
diff --git a/Ghidra/Processors/AARCH64/data/languages/AARCH64_AppleSilicon.slaspec b/Ghidra/Processors/AARCH64/data/languages/AARCH64_AppleSilicon.slaspec
new file mode 100644
index 0000000000..f1290bbd08
--- /dev/null
+++ b/Ghidra/Processors/AARCH64/data/languages/AARCH64_AppleSilicon.slaspec
@@ -0,0 +1,6 @@
+
+@define DATA_ENDIAN "little"
+
+@include "AARCH64instructions.sinc"
+@include "AARCH64_AMXext.sinc"
+
diff --git a/Ghidra/Processors/AARCH64/data/languages/AARCH64instructions.sinc b/Ghidra/Processors/AARCH64/data/languages/AARCH64instructions.sinc
index a3e29b7915..fa11662cdb 100644
--- a/Ghidra/Processors/AARCH64/data/languages/AARCH64instructions.sinc
+++ b/Ghidra/Processors/AARCH64/data/languages/AARCH64instructions.sinc
@@ -1264,6 +1264,7 @@ define token instrAARCH64 (32) endian = little
b_1619 = (16,19)
b_1620 = (16,20)
b_1621 = (16,21)
+ b_1623 = (16,23)
b_1627 = (16,27)
b_1629 = (16,29)
b_1631 = (16,31)
diff --git a/Ghidra/Processors/AARCH64/data/languages/AppleSilicon.ldefs b/Ghidra/Processors/AARCH64/data/languages/AppleSilicon.ldefs
new file mode 100644
index 0000000000..f8c0e540b8
--- /dev/null
+++ b/Ghidra/Processors/AARCH64/data/languages/AppleSilicon.ldefs
@@ -0,0 +1,18 @@
+
+
+
+ AppleSilicon ARM v8.5-A LE instructions, LE data, AMX extensions
+
+
+
+
+
+