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Merge remote-tracking branch 'origin/GP-1520_emteere_AppleSiliconAMX--SQUASHED' into Ghidra_10.1

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ghidra1 2021-12-01 20:18:09 -05:00
parent 438be0f5cb 89f73857e6
commit f8f95c9aef
6 changed files with 201 additions and 2 deletions
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3
Ghidra/Processors/AARCH64/certification.manifest
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@ -8,6 +8,8 @@ data/languages/AARCH64.opinion||GHIDRA||||END|
data/languages/AARCH64.pspec||GHIDRA||||END|
data/languages/AARCH64.slaspec||GHIDRA||||END|
data/languages/AARCH64BE.slaspec||GHIDRA||||END|
data/languages/AARCH64_AMXext.sinc||GHIDRA||||END|
data/languages/AARCH64_AppleSilicon.slaspec||GHIDRA||||END|
data/languages/AARCH64_base_PACoptions.sinc||GHIDRA||||END|
data/languages/AARCH64_win.cspec||GHIDRA||||END|
data/languages/AARCH64base.sinc||GHIDRA||||END|
@ -15,6 +17,7 @@ data/languages/AARCH64instructions.sinc||GHIDRA||||END|
data/languages/AARCH64ldst.sinc||GHIDRA||||END|
data/languages/AARCH64neon.sinc||GHIDRA||||END|
data/languages/AARCH64sve.sinc||GHIDRA||||END|
data/languages/AppleSilicon.ldefs||GHIDRA||||END|
data/manuals/AARCH64.idx||GHIDRA||||END|
data/patterns/AARCH64_LE_patterns.xml||GHIDRA||||END|
data/patterns/patternconstraints.xml||GHIDRA||||END|

4
Ghidra/Processors/AARCH64/data/languages/AARCH64.opinion
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@ -3,10 +3,10 @@
<constraint primary="183" processor="AARCH64" size="64" variant="v8A" />
</constraint>
<constraint loader="Mac OS X Mach-O" compilerSpecID="default">
<constraint primary="16777228" processor="AARCH64" endian="little" size="64" />
<constraint primary="16777228" processor="AARCH64" endian="little" size="64" variant="AppleSilicon" />
</constraint>
<constraint loader="DYLD Cache" compilerSpecID="default">
<constraint primary="AARCH64" processor="AARCH64" endian="little" size="64" />
<constraint primary="AARCH64" processor="AARCH64" endian="little" size="64" variant="AppleSilicon" />
</constraint>
<constraint loader="Portable Executable (PE)" compilerSpecID="windows">
<constraint primary="43620" processor="AARCH64" endian="little" size="64" variant="v8A" />

171
Ghidra/Processors/AARCH64/data/languages/AARCH64_AMXext.sinc Normal file
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@ -0,0 +1,171 @@
#
# Apple AARCH64 extended matrix instructions
# Contents based on evolving information published on Web
#
#
define pcodeop __amx_ldx;
define pcodeop __amx_ldy;
define pcodeop __amx_stx;
define pcodeop __amx_sty;
define pcodeop __amx_ldz;
define pcodeop __amx_stz;
define pcodeop __amx_ldzi;
define pcodeop __amx_stzi;
define pcodeop __amx_extrx;
define pcodeop __amx_extry;
define pcodeop __amx_fma64;
define pcodeop __amx_fms64;
define pcodeop __amx_fma32;
define pcodeop __amx_fms32;
define pcodeop __amx_mac16;
define pcodeop __amx_fma16;
define pcodeop __amx_fms16;
define pcodeop __amx_enable;
define pcodeop __amx_disable;
define pcodeop __amx_vecint;
define pcodeop __amx_vecfp;
define pcodeop __amx_matint;
define pcodeop __amx_matfp;
define pcodeop __amx_genlut;
with : ImmS_ImmR_TestSet=1 {
AMXAddr: is Rd_GPR64 {
addr:8 = Rd_GPR64 & 0x00FFFFFFFFFFFFFF;
export addr;
}
AMXRegOff: is Rd_GPR64 {
registerOff:8 = (Rd_GPR64 >> 56) & 0x1F;
export registerOff;
}
AMXSize: is Rd_GPR64 {
local size = ((Rd_GPR64 >> 62) & 1);
size = zext(size == 0) * 0x40 | zext(size ==1 ) * 0x80;
export size;
}
:__amx_ldx Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=0 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
{
__amx_ldx(Rd_GPR64);
}
:__amx_ldy Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=1 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
{
__amx_ldy(Rd_GPR64);
}
:__amx_stx Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=2 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
{
__amx_stx(Rd_GPR64);
}
:__amx_sty Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=3 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
{
__amx_sty(Rd_GPR64);
}
:__amx_ldz Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=4 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
{
__amx_ldz(Rd_GPR64);
}
:__amx_stz Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=5 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
{
__amx_stz(Rd_GPR64);
}
:__amx_ldzi Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=6 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
{
__amx_ldzi(Rd_GPR64);
}
:__amx_stzi Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=7 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
{
__amx_stzi(Rd_GPR64);
}
:__amx_extrx Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=8 & Rd_GPR64
{
__amx_extrx(Rd_GPR64);
}
:__amx_extry Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=9 & Rd_GPR64
{
__amx_extry(Rd_GPR64);
}
:__amx_fma64 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=10 & Rd_GPR64
{
__amx_fma64(Rd_GPR64);
}
:__amx_fms64 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=11 & Rd_GPR64
{
__amx_fms64(Rd_GPR64);
}
:__amx_fma32 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=12 & Rd_GPR64
{
__amx_fma32(Rd_GPR64);
}
:__amx_fms32 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=13 & Rd_GPR64
{
__amx_fms32(Rd_GPR64);
}
:__amx_mac16 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=14 & Rd_GPR64
{
__amx_mac16(Rd_GPR64);
}
:__amx_fma16 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=15 & Rd_GPR64
{
__amx_fma16(Rd_GPR64);
}
:__amx_fms16 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=16 & Rd_GPR64
{
__amx_fms16(Rd_GPR64);
}
:__amxdisable is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=17 & b_0004=1
{
__amx_disable();
}
:__amxenable is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=17 & b_0004=0
{
__amx_enable();
}
:__amx_vecint Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=18 & Rd_GPR64
{
__amx_vecint(Rd_GPR64);
}
:__amx_vecfp Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=19 & Rd_GPR64
{
__amx_vecfp(Rd_GPR64);
}
:__amx_matint Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=20 & Rd_GPR64
{
__amx_matint(Rd_GPR64);
}
:__amx_matfp Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=21 & Rd_GPR64
{
__amx_matfp(Rd_GPR64);
}
:__amx_genlut Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=22 & Rd_GPR64
{
__amx_genlut(Rd_GPR64);
}
}

6
Ghidra/Processors/AARCH64/data/languages/AARCH64_AppleSilicon.slaspec Normal file
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@ -0,0 +1,6 @@
@define DATA_ENDIAN "little"
@include "AARCH64instructions.sinc"
@include "AARCH64_AMXext.sinc"

1
Ghidra/Processors/AARCH64/data/languages/AARCH64instructions.sinc
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@ -1264,6 +1264,7 @@ define token instrAARCH64 (32) endian = little
b_1619 = (16,19)
b_1620 = (16,20)
b_1621 = (16,21)
b_1623 = (16,23)
b_1627 = (16,27)
b_1629 = (16,29)
b_1631 = (16,31)

18
Ghidra/Processors/AARCH64/data/languages/AppleSilicon.ldefs Normal file
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@ -0,0 +1,18 @@
<?xml version="1.1" encoding="UTF-8"?>
<language_definitions>
<language processor="AARCH64"
endian="little"
size="64"
variant="AppleSilicon"
version="1.5"
slafile="AARCH64_AppleSilicon.sla"
processorspec="AARCH64.pspec"
manualindexfile="../manuals/AARCH64.idx"
id="AARCH64:LE:64:AppleSilicon">
<description>AppleSilicon ARM v8.5-A LE instructions, LE data, AMX extensions</description>
<compiler name="default" spec="AARCH64.cspec" id="default"/>
<external_name tool="gnu" name="aarch64"/>
<external_name tool="gnu" name="aarch64:ilp32"/>
<external_name tool="DWARF.register.mapping.file" name="AARCH64.dwarf"/>
</language>
</language_definitions>