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https://github.com/NationalSecurityAgency/ghidra
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GP-1837: fixed issue with ARM register lists having inconsistent format
This commit is contained in:
ghidorahrex
parent
e2ae03d1b9
commit
f58abb5eec
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@ -615,292 +615,293 @@ Rn_exclaim_WB: is Rn0810 & thc0810=7 & thc0707=1 { }
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Rn_exclaim_WB: is Rn0810 & thc0810 { Rn0810 = mult_addr; }
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# ldlist is the list of registers to be loaded or popped
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LdRtype0: " "^r0 is thc0000=1 & r0 & thc0107=0 { r0 = *mult_addr; mult_addr = mult_addr + 4; }
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LdRtype0: " "^r0^"," is thc0000=1 & r0 { r0 = *mult_addr; mult_addr = mult_addr + 4; }
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LdRtype0: r0 is thc0000=1 & r0 & thc0107=0 { r0 = *mult_addr; mult_addr = mult_addr + 4; }
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LdRtype0: r0, is thc0000=1 & r0 { r0 = *mult_addr; mult_addr = mult_addr + 4; }
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LdRtype0: is thc0000=0 { }
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LdRtype1: LdRtype0 r1 is LdRtype0 & thc0101=1 & r1 & thc0207=0 { r1 = *mult_addr; mult_addr = mult_addr + 4; }
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LdRtype1: LdRtype0 r1^"," is LdRtype0 & thc0101=1 & r1 { r1 = *mult_addr; mult_addr = mult_addr + 4; }
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LdRtype1: LdRtype0 is LdRtype0 & thc0101=0 { }
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LdRtype2: LdRtype1 r2 is LdRtype1 & thc0202=1 & r2 & thc0307=0 { r2 = *mult_addr; mult_addr = mult_addr + 4; }
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LdRtype2: LdRtype1 r2^"," is LdRtype1 & thc0202=1 & r2 { r2 = *mult_addr; mult_addr = mult_addr + 4; }
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LdRtype2: LdRtype1 is LdRtype1 & thc0202=0 { }
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LdRtype3: LdRtype2 r3 is LdRtype2 & thc0303=1 & r3 & thc0407=0 { r3 = *mult_addr; mult_addr = mult_addr + 4; }
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LdRtype3: LdRtype2 r3^"," is LdRtype2 & thc0303=1 & r3 { r3 = *mult_addr; mult_addr = mult_addr + 4; }
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LdRtype3: LdRtype2 is LdRtype2 & thc0303=0 { }
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LdRtype4: LdRtype3 r4 is LdRtype3 & thc0404=1 & r4 & thc0507=0 { r4 = *mult_addr; mult_addr = mult_addr + 4; }
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LdRtype4: LdRtype3 r4^"," is LdRtype3 & thc0404=1 & r4 { r4 = *mult_addr; mult_addr = mult_addr + 4; }
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LdRtype4: LdRtype3 is LdRtype3 & thc0404=0 { }
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LdRtype5: LdRtype4 r5 is LdRtype4 & thc0505=1 & r5 & thc0607=0 { r5 = *mult_addr; mult_addr = mult_addr + 4; }
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LdRtype5: LdRtype4 r5^"," is LdRtype4 & thc0505=1 & r5 { r5 = *mult_addr; mult_addr = mult_addr + 4; }
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LdRtype5: LdRtype4 is LdRtype4 & thc0505=0 { }
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LdRtype6: LdRtype5 r6 is LdRtype5 & thc0606=1 & r6 & thc0707=0 { r6 = *mult_addr; mult_addr = mult_addr + 4; }
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LdRtype6: LdRtype5 r6^"," is LdRtype5 & thc0606=1 & r6 { r6 = *mult_addr; mult_addr = mult_addr + 4; }
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LdRtype6: LdRtype5 is LdRtype5 & thc0606=0 { }
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ldlist: LdRtype6 r7 is LdRtype6 & thc0707=1 & r7 { r7 = *mult_addr; mult_addr = mult_addr + 4; }
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ldlist: LdRtype6 is LdRtype6 & thc0707=0 { }
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LdRtype1: LdRtype0^r1 is LdRtype0 & thc0101=1 & r1 & thc0207=0 { r1 = *mult_addr; mult_addr = mult_addr + 4; }
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LdRtype1: LdRtype0^r1, is LdRtype0 & thc0101=1 & r1 { r1 = *mult_addr; mult_addr = mult_addr + 4; }
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LdRtype1: LdRtype0 is LdRtype0 & thc0101=0 { }
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LdRtype2: LdRtype1^r2 is LdRtype1 & thc0202=1 & r2 & thc0307=0 { r2 = *mult_addr; mult_addr = mult_addr + 4; }
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LdRtype2: LdRtype1^r2, is LdRtype1 & thc0202=1 & r2 { r2 = *mult_addr; mult_addr = mult_addr + 4; }
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LdRtype2: LdRtype1 is LdRtype1 & thc0202=0 { }
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LdRtype3: LdRtype2^r3 is LdRtype2 & thc0303=1 & r3 & thc0407=0 { r3 = *mult_addr; mult_addr = mult_addr + 4; }
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LdRtype3: LdRtype2^r3, is LdRtype2 & thc0303=1 & r3 { r3 = *mult_addr; mult_addr = mult_addr + 4; }
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LdRtype3: LdRtype2 is LdRtype2 & thc0303=0 { }
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LdRtype4: LdRtype3^r4 is LdRtype3 & thc0404=1 & r4 & thc0507=0 { r4 = *mult_addr; mult_addr = mult_addr + 4; }
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LdRtype4: LdRtype3^r4, is LdRtype3 & thc0404=1 & r4 { r4 = *mult_addr; mult_addr = mult_addr + 4; }
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LdRtype4: LdRtype3 is LdRtype3 & thc0404=0 { }
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LdRtype5: LdRtype4^r5 is LdRtype4 & thc0505=1 & r5 & thc0607=0 { r5 = *mult_addr; mult_addr = mult_addr + 4; }
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LdRtype5: LdRtype4^r5, is LdRtype4 & thc0505=1 & r5 { r5 = *mult_addr; mult_addr = mult_addr + 4; }
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LdRtype5: LdRtype4 is LdRtype4 & thc0505=0 { }
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LdRtype6: LdRtype5^r6 is LdRtype5 & thc0606=1 & r6 & thc0707=0 { r6 = *mult_addr; mult_addr = mult_addr + 4; }
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LdRtype6: LdRtype5^r6, is LdRtype5 & thc0606=1 & r6 { r6 = *mult_addr; mult_addr = mult_addr + 4; }
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LdRtype6: LdRtype5 is LdRtype5 & thc0606=0 { }
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ldlist: LdRtype6^r7 is LdRtype6 & thc0707=1 & r7 { r7 = *mult_addr; mult_addr = mult_addr + 4; }
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ldlist: LdRtype6 is LdRtype6 & thc0707=0 { }
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#strlist is the list of registers to be stored
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StrType0: " "^r0 is thc0000=1 & r0 & thc0107=0 { *mult_addr = r0; mult_addr = mult_addr + 4; }
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StrType0: " "^r0^"," is thc0000=1 & r0 { *mult_addr = r0; mult_addr = mult_addr + 4; }
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StrType0: is thc0000=0 { }
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StrType1: StrType0 r1 is StrType0 & thc0101=1 & r1 & thc0207=0 { *mult_addr = r1; mult_addr = mult_addr + 4; }
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StrType1: StrType0 r1^"," is StrType0 & thc0101=1 & r1 { *mult_addr = r1; mult_addr = mult_addr + 4; }
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StrType1: StrType0 is StrType0 & thc0101=0 { }
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StrType2: StrType1 r2 is StrType1 & thc0202=1 & r2 & thc0307=0 { *mult_addr = r2; mult_addr = mult_addr + 4; }
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StrType2: StrType1 r2^"," is StrType1 & thc0202=1 & r2 { *mult_addr = r2; mult_addr = mult_addr + 4; }
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StrType2: StrType1 is StrType1 & thc0202=0 { }
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StrType3: StrType2 r3 is StrType2 & thc0303=1 & r3 & thc0407=0 { *mult_addr = r3; mult_addr = mult_addr + 4; }
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StrType3: StrType2 r3^"," is StrType2 & thc0303=1 & r3 { *mult_addr = r3; mult_addr = mult_addr + 4; }
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StrType3: StrType2 is StrType2 & thc0303=0 { }
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StrType4: StrType3 r4 is StrType3 & thc0404=1 & r4 & thc0507=0 { *mult_addr = r4; mult_addr = mult_addr + 4; }
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StrType4: StrType3 r4^"," is StrType3 & thc0404=1 & r4 { *mult_addr = r4; mult_addr = mult_addr + 4; }
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StrType4: StrType3 is StrType3 & thc0404=0 { }
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StrType5: StrType4 r5 is StrType4 & thc0505=1 & r5 & thc0607=0 { *mult_addr = r5; mult_addr = mult_addr + 4; }
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StrType5: StrType4 r5^"," is StrType4 & thc0505=1 & r5 { *mult_addr = r5; mult_addr = mult_addr + 4; }
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StrType5: StrType4 is StrType4 & thc0505=0 { }
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StrType6: StrType5 r6 is StrType5 & thc0606=1 & r6 & thc0707=0 { *mult_addr = r6; mult_addr = mult_addr + 4; }
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StrType6: StrType5 r6^"," is StrType5 & thc0606=1 & r6 { *mult_addr = r6; mult_addr = mult_addr + 4; }
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StrType6: StrType5 is StrType5 & thc0606=0 { }
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StrType7: StrType6 r7 is StrType6 & thc0707=1 & r7 { *mult_addr = r7; mult_addr = mult_addr + 4; }
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StrType7: StrType6 is StrType6 & thc0707=0 { }
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strlist: StrType7 is StrType7 { }
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StrType0: r0 is thc0000=1 & r0 & thc0107=0 { *mult_addr = r0; mult_addr = mult_addr + 4; }
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StrType0: r0, is thc0000=1 & r0 { *mult_addr = r0; mult_addr = mult_addr + 4; }
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StrType0: is thc0000=0 { }
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StrType1: StrType0^r1 is StrType0 & thc0101=1 & r1 & thc0207=0 { *mult_addr = r1; mult_addr = mult_addr + 4; }
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StrType1: StrType0^r1, is StrType0 & thc0101=1 & r1 { *mult_addr = r1; mult_addr = mult_addr + 4; }
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StrType1: StrType0 is StrType0 & thc0101=0 { }
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StrType2: StrType1^r2 is StrType1 & thc0202=1 & r2 & thc0307=0 { *mult_addr = r2; mult_addr = mult_addr + 4; }
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StrType2: StrType1^r2, is StrType1 & thc0202=1 & r2 { *mult_addr = r2; mult_addr = mult_addr + 4; }
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StrType2: StrType1 is StrType1 & thc0202=0 { }
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StrType3: StrType2^r3 is StrType2 & thc0303=1 & r3 & thc0407=0 { *mult_addr = r3; mult_addr = mult_addr + 4; }
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StrType3: StrType2^r3, is StrType2 & thc0303=1 & r3 { *mult_addr = r3; mult_addr = mult_addr + 4; }
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StrType3: StrType2 is StrType2 & thc0303=0 { }
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StrType4: StrType3^r4 is StrType3 & thc0404=1 & r4 & thc0507=0 { *mult_addr = r4; mult_addr = mult_addr + 4; }
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StrType4: StrType3^r4, is StrType3 & thc0404=1 & r4 { *mult_addr = r4; mult_addr = mult_addr + 4; }
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StrType4: StrType3 is StrType3 & thc0404=0 { }
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StrType5: StrType4^r5 is StrType4 & thc0505=1 & r5 & thc0607=0 { *mult_addr = r5; mult_addr = mult_addr + 4; }
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StrType5: StrType4^r5, is StrType4 & thc0505=1 & r5 { *mult_addr = r5; mult_addr = mult_addr + 4; }
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StrType5: StrType4 is StrType4 & thc0505=0 { }
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StrType6: StrType5^r6 is StrType5 & thc0606=1 & r6 & thc0707=0 { *mult_addr = r6; mult_addr = mult_addr + 4; }
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StrType6: StrType5^r6, is StrType5 & thc0606=1 & r6 { *mult_addr = r6; mult_addr = mult_addr + 4; }
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StrType6: StrType5 is StrType5 & thc0606=0 { }
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StrType7: StrType6^r7 is StrType6 & thc0707=1 & r7 { *mult_addr = r7; mult_addr = mult_addr + 4; }
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StrType7: StrType6 is StrType6 & thc0707=0 { }
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strlist: StrType7 is StrType7 { }
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# pshlist is the list registers to be pushed to memory
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# SCR 10921, fix the order in which the regs appear in the disassembled insn, to be in line with objdump
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# Also add commas between regs
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#
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PshType7: "" is thc0707=0 { }
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PshType7: r7 is thc0707=1 & r7 { mult_addr = mult_addr - 4; *mult_addr = r7; }
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PshType7: "" is thc0707=0 { }
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PshType7: r7 is thc0707=1 & r7 { mult_addr = mult_addr - 4; *mult_addr = r7; }
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PshType6: PshType7 is PshType7 & thc0606=0 { }
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PshType6: r6 is PshType7 & thc0606=1 & r6 & thc0707=0 { mult_addr = mult_addr - 4; *mult_addr = r6; }
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PshType6: r6^"," PshType7 is PshType7 & thc0606=1 & r6 { mult_addr = mult_addr - 4; *mult_addr = r6; }
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PshType6: r6 is thc0606=1 & r6 & thc0707=0 { mult_addr = mult_addr - 4; *mult_addr = r6; }
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PshType6: r6,PshType7 is PshType7 & thc0606=1 & r6 { mult_addr = mult_addr - 4; *mult_addr = r6; }
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PshType5: PshType6 is PshType6 & thc0505=0 { }
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PshType5: r5 is PshType6 & thc0505=1 & r5 & thc0607=0 { mult_addr = mult_addr - 4; *mult_addr = r5; }
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PshType5: r5^"," PshType6 is PshType6 & thc0505=1 & r5 { mult_addr = mult_addr - 4; *mult_addr = r5; }
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PshType5: r5 is thc0505=1 & r5 & thc0607=0 { mult_addr = mult_addr - 4; *mult_addr = r5; }
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PshType5: r5,PshType6 is PshType6 & thc0505=1 & r5 { mult_addr = mult_addr - 4; *mult_addr = r5; }
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PshType4: PshType5 is PshType5 & thc0404=0 { }
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PshType4: r4 is PshType5 & thc0404=1 & r4 & thc0507=0 { mult_addr = mult_addr - 4; *mult_addr = r4; }
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PshType4: r4^"," PshType5 is PshType5 & thc0404=1 & r4 { mult_addr = mult_addr - 4; *mult_addr = r4; }
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PshType4: r4 is thc0404=1 & r4 & thc0507=0 { mult_addr = mult_addr - 4; *mult_addr = r4; }
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PshType4: r4,PshType5 is PshType5 & thc0404=1 & r4 { mult_addr = mult_addr - 4; *mult_addr = r4; }
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PshType3: PshType4 is PshType4 & thc0303=0 { }
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PshType3: r3 is PshType4 & thc0303=1 & r3 & thc0407=0 { mult_addr = mult_addr - 4; *mult_addr = r3; }
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PshType3: r3^"," PshType4 is PshType4 & thc0303=1 & r3 { mult_addr = mult_addr - 4; *mult_addr = r3; }
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PshType3: r3 is thc0303=1 & r3 & thc0407=0 { mult_addr = mult_addr - 4; *mult_addr = r3; }
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PshType3: r3,PshType4 is PshType4 & thc0303=1 & r3 { mult_addr = mult_addr - 4; *mult_addr = r3; }
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PshType2: PshType3 is PshType3 & thc0202=0 { }
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PshType2: r2 is PshType3 & thc0202=1 & r2 & thc0307=0 { mult_addr = mult_addr - 4; *mult_addr = r2; }
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PshType2: r2^"," PshType3 is PshType3 & thc0202=1 & r2 { mult_addr = mult_addr - 4; *mult_addr = r2; }
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PshType2: r2 is thc0202=1 & r2 & thc0307=0 { mult_addr = mult_addr - 4; *mult_addr = r2; }
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PshType2: r2,PshType3 is PshType3 & thc0202=1 & r2 { mult_addr = mult_addr - 4; *mult_addr = r2; }
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PshType1: PshType2 is PshType2 & thc0101=0 { }
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PshType1: r1 is PshType2 & thc0101=1 & r1 & thc0207=0 { mult_addr = mult_addr - 4; *mult_addr = r1; }
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PshType1: r1^"," PshType2 is PshType2 & thc0101=1 & r1 { mult_addr = mult_addr - 4; *mult_addr = r1; }
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PshType1: r1 is thc0101=1 & r1 & thc0207=0 { mult_addr = mult_addr - 4; *mult_addr = r1; }
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PshType1: r1,PshType2 is PshType2 & thc0101=1 & r1 { mult_addr = mult_addr - 4; *mult_addr = r1; }
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pshlist: PshType1 is PshType1 & thc0000=0 { }
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pshlist: r0 is PshType1 & thc0000=1 & r0 & thc0107=0 { mult_addr = mult_addr - 4; *mult_addr = r0; }
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pshlist: r0^"," PshType1 is PshType1 & thc0000=1 & r0 { mult_addr = mult_addr - 4; *mult_addr = r0; }
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pshlist: r0 is thc0000=1 & r0 & thc0107=0 { mult_addr = mult_addr - 4; *mult_addr = r0; }
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pshlist: r0,PshType1 is PshType1 & thc0000=1 & r0 { mult_addr = mult_addr - 4; *mult_addr = r0; }
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# ldlist_inc is the list of registers to be loaded for pop instructions
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thrlist15: r0 is thc0000=1 & r0 & thc0115=0 { r0 = * mult_addr; mult_addr = mult_addr + 4; }
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thrlist15: r0^"," is thc0000=1 & r0 { r0 = * mult_addr; mult_addr = mult_addr + 4; }
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thrlist15: is thc0000=0 { }
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thrlist14: thrlist15 r1 is thc0101=1 & thrlist15 & r1 & thc0215=0 { r1 = * mult_addr; mult_addr = mult_addr + 4; }
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thrlist14: thrlist15 r1^"," is thc0101=1 & thrlist15 & r1 { r1 = * mult_addr; mult_addr = mult_addr + 4; }
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thrlist14: thrlist15 is thc0101=0 & thrlist15 { }
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thrlist13: thrlist14 r2 is thc0202=1 & thrlist14 & r2 & thc0315=0 { r2 = * mult_addr; mult_addr = mult_addr + 4; }
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thrlist13: thrlist14 r2^"," is thc0202=1 & thrlist14 & r2 { r2 = * mult_addr; mult_addr = mult_addr + 4; }
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thrlist13: thrlist14 is thc0202=0 & thrlist14 { }
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thrlist12: thrlist13 r3 is thc0303=1 & thrlist13 & r3 & thc0415=0 { r3 = * mult_addr; mult_addr = mult_addr + 4; }
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thrlist12: thrlist13 r3^"," is thc0303=1 & thrlist13 & r3 { r3 = * mult_addr; mult_addr = mult_addr + 4; }
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thrlist12: thrlist13 is thc0303=0 & thrlist13 { }
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thrlist11: thrlist12 r4 is thc0404=1 & thrlist12 & r4 & thc0515=0 { r4 = * mult_addr; mult_addr = mult_addr + 4; }
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thrlist11: thrlist12 r4^"," is thc0404=1 & thrlist12 & r4 { r4 = * mult_addr; mult_addr = mult_addr + 4; }
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thrlist11: thrlist12 is thc0404=0 & thrlist12 { }
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thrlist10: thrlist11 r5 is thc0505=1 & thrlist11 & r5 & thc0615=0 { r5 = * mult_addr; mult_addr = mult_addr + 4; }
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thrlist10: thrlist11 r5^"," is thc0505=1 & thrlist11 & r5 { r5 = * mult_addr; mult_addr = mult_addr + 4; }
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thrlist10: thrlist11 is thc0505=0 & thrlist11 { }
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thrlist9: thrlist10 r6 is thc0606=1 & thrlist10 & r6 & thc0715=0 { r6 = * mult_addr; mult_addr = mult_addr + 4; }
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thrlist9: thrlist10 r6^"," is thc0606=1 & thrlist10 & r6 { r6 = * mult_addr; mult_addr = mult_addr + 4; }
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thrlist9: thrlist10 is thc0606=0 & thrlist10 { }
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thrlist8: thrlist9 r7 is thc0707=1 & thrlist9 & r7 & thc0815=0 { r7 = * mult_addr; mult_addr = mult_addr + 4; }
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thrlist8: thrlist9 r7^"," is thc0707=1 & thrlist9 & r7 { r7 = * mult_addr; mult_addr = mult_addr + 4; }
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thrlist8: thrlist9 is thc0707=0 & thrlist9 { }
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thrlist7: thrlist8 r8 is thc0808=1 & thrlist8 & r8 & thc0915=0 { r8 = * mult_addr; mult_addr = mult_addr + 4; }
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thrlist7: thrlist8 r8^"," is thc0808=1 & thrlist8 & r8 { r8 = * mult_addr; mult_addr = mult_addr + 4; }
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thrlist7: thrlist8 is thc0808=0 & thrlist8 { }
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thrlist6: thrlist7 r9 is thc0909=1 & thrlist7 & r9 & thc1015=0 { r9 = * mult_addr; mult_addr = mult_addr + 4; }
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thrlist6: thrlist7 r9^"," is thc0909=1 & thrlist7 & r9 { r9 = * mult_addr; mult_addr = mult_addr + 4; }
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thrlist6: thrlist7 is thc0909=0 & thrlist7 { }
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thrlist5: thrlist6 r10 is thc1010=1 & thrlist6 & r10 & thc1115=0 { r10 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist5: thrlist6 r10^"," is thc1010=1 & thrlist6 & r10 { r10 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist5: thrlist6 is thc1010=0 & thrlist6 { }
|
||||
thrlist4: thrlist5 r11 is thc1111=1 & thrlist5 & r11 & thc1215=0 { r11 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist4: thrlist5 r11^"," is thc1111=1 & thrlist5 & r11 { r11 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist4: thrlist5 is thc1111=0 & thrlist5 { }
|
||||
thrlist3: thrlist4 r12 is thc1212=1 & thrlist4 & r12 & thc1315=0 { r12 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist3: thrlist4 r12^"," is thc1212=1 & thrlist4 & r12 { r12 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist3: thrlist4 is thc1212=0 & thrlist4 { }
|
||||
thrlist2: thrlist3 sp is thc1313=1 & thrlist3 & sp & thc1415=0 { sp = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist2: thrlist3 sp^"," is thc1313=1 & thrlist3 & sp { sp = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist2: thrlist3 is thc1313=0 & thrlist3 { }
|
||||
thrlist1: thrlist2 lr is thc1414=1 & thrlist2 & lr & thc1515=0 { lr = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist1: thrlist2 lr^"," is thc1414=1 & thrlist2 & lr { lr = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist1: thrlist2 is thc1414=0 & thrlist2 { }
|
||||
thldrlist_inc: {thrlist1 pc } is thc1515=1 & thrlist1 & pc { pc = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thldrlist_inc: {thrlist1 } is thc1515=0 & thrlist1 { }
|
||||
thrlist15: r0 is thc0000=1 & r0 & thc0115=0 { r0 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist15: r0, is thc0000=1 & r0 { r0 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist15: is thc0000=0 { }
|
||||
thrlist14: thrlist15^r1 is thc0101=1 & thrlist15 & r1 & thc0215=0 { r1 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist14: thrlist15^r1, is thc0101=1 & thrlist15 & r1 { r1 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist14: thrlist15 is thc0101=0 & thrlist15 { }
|
||||
thrlist13: thrlist14^r2 is thc0202=1 & thrlist14 & r2 & thc0315=0 { r2 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist13: thrlist14^r2, is thc0202=1 & thrlist14 & r2 { r2 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist13: thrlist14 is thc0202=0 & thrlist14 { }
|
||||
thrlist12: thrlist13^r3 is thc0303=1 & thrlist13 & r3 & thc0415=0 { r3 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist12: thrlist13^r3, is thc0303=1 & thrlist13 & r3 { r3 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist12: thrlist13 is thc0303=0 & thrlist13 { }
|
||||
thrlist11: thrlist12^r4 is thc0404=1 & thrlist12 & r4 & thc0515=0 { r4 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist11: thrlist12^r4, is thc0404=1 & thrlist12 & r4 { r4 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist11: thrlist12 is thc0404=0 & thrlist12 { }
|
||||
thrlist10: thrlist11^r5 is thc0505=1 & thrlist11 & r5 & thc0615=0 { r5 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist10: thrlist11^r5, is thc0505=1 & thrlist11 & r5 { r5 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist10: thrlist11 is thc0505=0 & thrlist11 { }
|
||||
thrlist9: thrlist10^r6 is thc0606=1 & thrlist10 & r6 & thc0715=0 { r6 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist9: thrlist10^r6, is thc0606=1 & thrlist10 & r6 { r6 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist9: thrlist10 is thc0606=0 & thrlist10 { }
|
||||
thrlist8: thrlist9^r7 is thc0707=1 & thrlist9 & r7 & thc0815=0 { r7 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist8: thrlist9^r7, is thc0707=1 & thrlist9 & r7 { r7 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist8: thrlist9 is thc0707=0 & thrlist9 { }
|
||||
thrlist7: thrlist8^r8 is thc0808=1 & thrlist8 & r8 & thc0915=0 { r8 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist7: thrlist8^r8, is thc0808=1 & thrlist8 & r8 { r8 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist7: thrlist8 is thc0808=0 & thrlist8 { }
|
||||
thrlist6: thrlist7^r9 is thc0909=1 & thrlist7 & r9 & thc1015=0 { r9 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist6: thrlist7^r9, is thc0909=1 & thrlist7 & r9 { r9 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist6: thrlist7 is thc0909=0 & thrlist7 { }
|
||||
thrlist5: thrlist6^r10 is thc1010=1 & thrlist6 & r10 & thc1115=0 { r10 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist5: thrlist6^r10, is thc1010=1 & thrlist6 & r10 { r10 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist5: thrlist6 is thc1010=0 & thrlist6 { }
|
||||
thrlist4: thrlist5^r11 is thc1111=1 & thrlist5 & r11 & thc1215=0 { r11 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist4: thrlist5^r11, is thc1111=1 & thrlist5 & r11 { r11 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist4: thrlist5 is thc1111=0 & thrlist5 { }
|
||||
thrlist3: thrlist4^r12 is thc1212=1 & thrlist4 & r12 & thc1315=0 { r12 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist3: thrlist4^r12, is thc1212=1 & thrlist4 & r12 { r12 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist3: thrlist4 is thc1212=0 & thrlist4 { }
|
||||
thrlist2: thrlist3^sp is thc1313=1 & thrlist3 & sp & thc1415=0 { sp = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist2: thrlist3^sp, is thc1313=1 & thrlist3 & sp { sp = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist2: thrlist3 is thc1313=0 & thrlist3 { }
|
||||
thrlist1: thrlist2^lr is thc1414=1 & thrlist2 & lr & thc1515=0 { lr = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist1: thrlist2^lr, is thc1414=1 & thrlist2 & lr { lr = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thrlist1: thrlist2 is thc1414=0 & thrlist2 { }
|
||||
thldrlist_inc: {thrlist1^pc} is thc1515=1 & thrlist1 & pc { pc = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
thldrlist_inc: {thrlist1} is thc1515=0 & thrlist1 { }
|
||||
|
||||
@if defined(VERSION_6T2) || defined(VERSION_7)
|
||||
|
||||
# thstrlist_inc is the list of registers to be stored using IA or IB in Addressing Mode 4
|
||||
thsinc15: r0 is thc0000=1 & r0 { * mult_addr = r0; mult_addr = mult_addr + 4; }
|
||||
thsinc15: is thc0000=0 { }
|
||||
thsinc14: thsinc15 r1 is thc0101=1 & thsinc15 & r1 & thc0215=0 { * mult_addr = r1; mult_addr = mult_addr + 4; }
|
||||
thsinc14: thsinc15 r1^"," is thc0101=1 & thsinc15 & r1 { * mult_addr = r1; mult_addr = mult_addr + 4; }
|
||||
thsinc14: thsinc15 is thc0101=0 & thsinc15 { }
|
||||
thsinc13: thsinc14 r2 is thc0202=1 & thsinc14 & r2 & thc0315=0 { * mult_addr = r2; mult_addr = mult_addr + 4; }
|
||||
thsinc13: thsinc14 r2^"," is thc0202=1 & thsinc14 & r2 { * mult_addr = r2; mult_addr = mult_addr + 4; }
|
||||
thsinc13: thsinc14 is thc0202=0 & thsinc14 { }
|
||||
thsinc12: thsinc13 r3 is thc0303=1 & thsinc13 & r3 & thc0415=0 { * mult_addr = r3; mult_addr = mult_addr + 4; }
|
||||
thsinc12: thsinc13 r3^"," is thc0303=1 & thsinc13 & r3 { * mult_addr = r3; mult_addr = mult_addr + 4; }
|
||||
thsinc12: thsinc13 is thc0303=0 & thsinc13 { }
|
||||
thsinc11: thsinc12 r4 is thc0404=1 & thsinc12 & r4 & thc0515=0 { * mult_addr = r4; mult_addr = mult_addr + 4; }
|
||||
thsinc11: thsinc12 r4^"," is thc0404=1 & thsinc12 & r4 { * mult_addr = r4; mult_addr = mult_addr + 4; }
|
||||
thsinc11: thsinc12 is thc0404=0 & thsinc12 { }
|
||||
thsinc10: thsinc11 r5 is thc0505=1 & thsinc11 & r5 & thc0615=0 { * mult_addr = r5; mult_addr = mult_addr + 4; }
|
||||
thsinc10: thsinc11 r5^"," is thc0505=1 & thsinc11 & r5 { * mult_addr = r5; mult_addr = mult_addr + 4; }
|
||||
thsinc10: thsinc11 is thc0505=0 & thsinc11 { }
|
||||
thsinc9: thsinc10 r6 is thc0606=1 & thsinc10 & r6 & thc0715=0 { * mult_addr = r6; mult_addr = mult_addr + 4; }
|
||||
thsinc9: thsinc10 r6^"," is thc0606=1 & thsinc10 & r6 { * mult_addr = r6; mult_addr = mult_addr + 4; }
|
||||
thsinc9: thsinc10 is thc0606=0 & thsinc10 { }
|
||||
thsinc8: thsinc9 r7 is thc0707=1 & thsinc9 & r7 & thc0815=0 { * mult_addr = r7; mult_addr = mult_addr + 4; }
|
||||
thsinc8: thsinc9 r7^"," is thc0707=1 & thsinc9 & r7 { * mult_addr = r7; mult_addr = mult_addr + 4; }
|
||||
thsinc8: thsinc9 is thc0707=0 & thsinc9 { }
|
||||
thsinc7: thsinc8 r8 is thc0808=1 & thsinc8 & r8 & thc0915=0 { * mult_addr = r8; mult_addr = mult_addr + 4; }
|
||||
thsinc7: thsinc8 r8^"," is thc0808=1 & thsinc8 & r8 { * mult_addr = r8; mult_addr = mult_addr + 4; }
|
||||
thsinc7: thsinc8 is thc0808=0 & thsinc8 { }
|
||||
thsinc6: thsinc7 r9 is thc0909=1 & thsinc7 & r9 & thc1015=0 { * mult_addr = r9; mult_addr = mult_addr + 4; }
|
||||
thsinc6: thsinc7 r9^"," is thc0909=1 & thsinc7 & r9 { * mult_addr = r9; mult_addr = mult_addr + 4; }
|
||||
thsinc6: thsinc7 is thc0909=0 & thsinc7 { }
|
||||
thsinc5: thsinc6 r10 is thc1010=1 & thsinc6 & r10 & thc1115=0 { * mult_addr = r10; mult_addr = mult_addr + 4; }
|
||||
thsinc5: thsinc6 r10^"," is thc1010=1 & thsinc6 & r10 { * mult_addr = r10; mult_addr = mult_addr + 4; }
|
||||
thsinc5: thsinc6 is thc1010=0 & thsinc6 { }
|
||||
thsinc4: thsinc5 r11 is thc1111=1 & thsinc5 & r11 & thc1215=0 { * mult_addr = r11; mult_addr = mult_addr + 4; }
|
||||
thsinc4: thsinc5 r11^"," is thc1111=1 & thsinc5 & r11 { * mult_addr = r11; mult_addr = mult_addr + 4; }
|
||||
thsinc4: thsinc5 is thc1111=0 & thsinc5 { }
|
||||
thsinc3: thsinc4 r12 is thc1212=1 & thsinc4 & r12 & thc1315=0 { * mult_addr = r12; mult_addr = mult_addr + 4; }
|
||||
thsinc3: thsinc4 r12^"," is thc1212=1 & thsinc4 & r12 { * mult_addr = r12; mult_addr = mult_addr + 4; }
|
||||
thsinc3: thsinc4 is thc1212=0 & thsinc4 { }
|
||||
thsinc2: thsinc3 sp is thc1313=1 & thsinc3 & sp & thc1415=0 { * mult_addr = sp; mult_addr = mult_addr + 4; }
|
||||
thsinc2: thsinc3 sp^"," is thc1313=1 & thsinc3 & sp { * mult_addr = sp; mult_addr = mult_addr + 4; }
|
||||
thsinc2: thsinc3 is thc1313=0 & thsinc3 { }
|
||||
thsinc1: thsinc2 lr is thc1414=1 & thsinc2 & lr & thc1515=0 { * mult_addr = lr; mult_addr = mult_addr + 4; }
|
||||
thsinc1: thsinc2 lr^"," is thc1414=1 & thsinc2 & lr { * mult_addr = lr; mult_addr = mult_addr + 4; }
|
||||
thsinc1: thsinc2 is thc1414=0 & thsinc2 { }
|
||||
thstrlist_inc: {thsinc1 pc } is thc1515=1 & thsinc1 & pc { *:4 mult_addr = inst_start+4; mult_addr = mult_addr + 4; }
|
||||
thstrlist_inc: {thsinc1 } is thc1515=0 & thsinc1 { }
|
||||
thsinc15: r0 is thc0000=1 & r0 & thc0115=0 { * mult_addr = r0; mult_addr = mult_addr + 4; }
|
||||
thsinc15: r0, is thc0000=1 & r0 { * mult_addr = r0; mult_addr = mult_addr + 4; }
|
||||
thsinc15: is thc0000=0 { }
|
||||
thsinc14: thsinc15^r1 is thc0101=1 & thsinc15 & r1 & thc0215=0 { * mult_addr = r1; mult_addr = mult_addr + 4; }
|
||||
thsinc14: thsinc15^r1, is thc0101=1 & thsinc15 & r1 { * mult_addr = r1; mult_addr = mult_addr + 4; }
|
||||
thsinc14: thsinc15 is thc0101=0 & thsinc15 { }
|
||||
thsinc13: thsinc14^r2 is thc0202=1 & thsinc14 & r2 & thc0315=0 { * mult_addr = r2; mult_addr = mult_addr + 4; }
|
||||
thsinc13: thsinc14^r2, is thc0202=1 & thsinc14 & r2 { * mult_addr = r2; mult_addr = mult_addr + 4; }
|
||||
thsinc13: thsinc14 is thc0202=0 & thsinc14 { }
|
||||
thsinc12: thsinc13^r3 is thc0303=1 & thsinc13 & r3 & thc0415=0 { * mult_addr = r3; mult_addr = mult_addr + 4; }
|
||||
thsinc12: thsinc13^r3, is thc0303=1 & thsinc13 & r3 { * mult_addr = r3; mult_addr = mult_addr + 4; }
|
||||
thsinc12: thsinc13 is thc0303=0 & thsinc13 { }
|
||||
thsinc11: thsinc12^r4 is thc0404=1 & thsinc12 & r4 & thc0515=0 { * mult_addr = r4; mult_addr = mult_addr + 4; }
|
||||
thsinc11: thsinc12^r4, is thc0404=1 & thsinc12 & r4 { * mult_addr = r4; mult_addr = mult_addr + 4; }
|
||||
thsinc11: thsinc12 is thc0404=0 & thsinc12 { }
|
||||
thsinc10: thsinc11^r5 is thc0505=1 & thsinc11 & r5 & thc0615=0 { * mult_addr = r5; mult_addr = mult_addr + 4; }
|
||||
thsinc10: thsinc11^r5, is thc0505=1 & thsinc11 & r5 { * mult_addr = r5; mult_addr = mult_addr + 4; }
|
||||
thsinc10: thsinc11 is thc0505=0 & thsinc11 { }
|
||||
thsinc9: thsinc10^r6 is thc0606=1 & thsinc10 & r6 & thc0715=0 { * mult_addr = r6; mult_addr = mult_addr + 4; }
|
||||
thsinc9: thsinc10^r6, is thc0606=1 & thsinc10 & r6 { * mult_addr = r6; mult_addr = mult_addr + 4; }
|
||||
thsinc9: thsinc10 is thc0606=0 & thsinc10 { }
|
||||
thsinc8: thsinc9^r7 is thc0707=1 & thsinc9 & r7 & thc0815=0 { * mult_addr = r7; mult_addr = mult_addr + 4; }
|
||||
thsinc8: thsinc9^r7, is thc0707=1 & thsinc9 & r7 { * mult_addr = r7; mult_addr = mult_addr + 4; }
|
||||
thsinc8: thsinc9 is thc0707=0 & thsinc9 { }
|
||||
thsinc7: thsinc8^r8 is thc0808=1 & thsinc8 & r8 & thc0915=0 { * mult_addr = r8; mult_addr = mult_addr + 4; }
|
||||
thsinc7: thsinc8^r8, is thc0808=1 & thsinc8 & r8 { * mult_addr = r8; mult_addr = mult_addr + 4; }
|
||||
thsinc7: thsinc8 is thc0808=0 & thsinc8 { }
|
||||
thsinc6: thsinc7^r9 is thc0909=1 & thsinc7 & r9 & thc1015=0 { * mult_addr = r9; mult_addr = mult_addr + 4; }
|
||||
thsinc6: thsinc7^r9, is thc0909=1 & thsinc7 & r9 { * mult_addr = r9; mult_addr = mult_addr + 4; }
|
||||
thsinc6: thsinc7 is thc0909=0 & thsinc7 { }
|
||||
thsinc5: thsinc6^r10 is thc1010=1 & thsinc6 & r10 & thc1115=0 { * mult_addr = r10; mult_addr = mult_addr + 4; }
|
||||
thsinc5: thsinc6^r10, is thc1010=1 & thsinc6 & r10 { * mult_addr = r10; mult_addr = mult_addr + 4; }
|
||||
thsinc5: thsinc6 is thc1010=0 & thsinc6 { }
|
||||
thsinc4: thsinc5^r11 is thc1111=1 & thsinc5 & r11 & thc1215=0 { * mult_addr = r11; mult_addr = mult_addr + 4; }
|
||||
thsinc4: thsinc5^r11, is thc1111=1 & thsinc5 & r11 { * mult_addr = r11; mult_addr = mult_addr + 4; }
|
||||
thsinc4: thsinc5 is thc1111=0 & thsinc5 { }
|
||||
thsinc3: thsinc4^r12 is thc1212=1 & thsinc4 & r12 & thc1315=0 { * mult_addr = r12; mult_addr = mult_addr + 4; }
|
||||
thsinc3: thsinc4^r12, is thc1212=1 & thsinc4 & r12 { * mult_addr = r12; mult_addr = mult_addr + 4; }
|
||||
thsinc3: thsinc4 is thc1212=0 & thsinc4 { }
|
||||
thsinc2: thsinc3^sp is thc1313=1 & thsinc3 & sp & thc1415=0 { * mult_addr = sp; mult_addr = mult_addr + 4; }
|
||||
thsinc2: thsinc3^sp, is thc1313=1 & thsinc3 & sp { * mult_addr = sp; mult_addr = mult_addr + 4; }
|
||||
thsinc2: thsinc3 is thc1313=0 & thsinc3 { }
|
||||
thsinc1: thsinc2^lr is thc1414=1 & thsinc2 & lr & thc1515=0 { * mult_addr = lr; mult_addr = mult_addr + 4; }
|
||||
thsinc1: thsinc2^lr, is thc1414=1 & thsinc2 & lr { * mult_addr = lr; mult_addr = mult_addr + 4; }
|
||||
thsinc1: thsinc2 is thc1414=0 & thsinc2 { }
|
||||
thstrlist_inc: {thsinc1^pc} is thc1515=1 & thsinc1 & pc { *:4 mult_addr = inst_start+4; mult_addr = mult_addr + 4; }
|
||||
thstrlist_inc: {thsinc1} is thc1515=0 & thsinc1 { }
|
||||
|
||||
# thldrlist_dec is the list of registers to be loaded using DA or DB in Addressing Mode 4
|
||||
thrldec15: pc is thc1515=1 & pc { pc = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec15: is thc1515=0 { }
|
||||
thrldec14: lr thrldec15 is thc1414=1 & thrldec15 & lr & thc1515=0 { lr = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec14: lr^"," thrldec15 is thc1414=1 & thrldec15 & lr { lr = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec14: thrldec15 is thc1414=0 & thrldec15 { }
|
||||
thrldec13: sp thrldec14 is thc1313=1 & thrldec14 & sp & thc1415=0 { sp = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec13: sp^"," thrldec14 is thc1313=1 & thrldec14 & sp { sp = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec13: thrldec14 is thc1313=0 & thrldec14 { }
|
||||
thrldec12: r12 thrldec13 is thc1212=1 & thrldec13 & r12 & thc1315=0 { r12 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec12: r12^"," thrldec13 is thc1212=1 & thrldec13 & r12 { r12 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec12: thrldec13 is thc1212=0 & thrldec13 { }
|
||||
thrldec11: r11 thrldec12 is thc1111=1 & thrldec12 & r11 & thc1215=0 { r11 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec11: r11^"," thrldec12 is thc1111=1 & thrldec12 & r11 { r11 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec11: thrldec12 is thc1111=0 & thrldec12 { }
|
||||
thrldec10: r10 thrldec11 is thc1010=1 & thrldec11 & r10 & thc1115=0 { r10 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec10: r10^"," thrldec11 is thc1010=1 & thrldec11 & r10 { r10 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec10: thrldec11 is thc1010=0 & thrldec11 { }
|
||||
thrldec9: r9 thrldec10 is thc0909=1 & thrldec10 & r9 & thc1015=0 { r9 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec9: r9^"," thrldec10 is thc0909=1 & thrldec10 & r9 { r9 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec9: thrldec10 is thc0909=0 & thrldec10 { }
|
||||
thrldec8: r8 thrldec9 is thc0808=1 & thrldec9 & r8 & thc0915=0 { r8 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec8: r8^"," thrldec9 is thc0808=1 & thrldec9 & r8 { r8 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec8: thrldec9 is thc0808=0 & thrldec9 { }
|
||||
thrldec7: r7 thrldec8 is thc0707=1 & thrldec8 & r7 & thc0815=0 { r7 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec7: r7^"," thrldec8 is thc0707=1 & thrldec8 & r7 { r7 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec7: thrldec8 is thc0707=0 & thrldec8 { }
|
||||
thrldec6: r6 thrldec7 is thc0606=1 & thrldec7 & r6 & thc0715=0 { r6 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec6: r6^"," thrldec7 is thc0606=1 & thrldec7 & r6 { r6 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec6: thrldec7 is thc0606=0 & thrldec7 { }
|
||||
thrldec5: r5 thrldec6 is thc0505=1 & thrldec6 & r5 & thc0615=0 { r5 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec5: r5^"," thrldec6 is thc0505=1 & thrldec6 & r5 { r5 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec5: thrldec6 is thc0505=0 & thrldec6 { }
|
||||
thrldec4: r4 thrldec5 is thc0404=1 & thrldec5 & r4 & thc0515=0 { r4 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec4: r4^"," thrldec5 is thc0404=1 & thrldec5 & r4 { r4 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec4: thrldec5 is thc0404=0 & thrldec5 { }
|
||||
thrldec3: r3 thrldec4 is thc0303=1 & thrldec4 & r3 & thc0415=0 { r3 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec3: r3^"," thrldec4 is thc0303=1 & thrldec4 & r3 { r3 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec3: thrldec4 is thc0303=0 & thrldec4 { }
|
||||
thrldec2: r2 thrldec3 is thc0202=1 & thrldec3 & r2 & thc0315=0 { r2 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec2: r2^"," thrldec3 is thc0202=1 & thrldec3 & r2 { r2 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec2: thrldec3 is thc0202=0 & thrldec3 { }
|
||||
thrldec1: r1 thrldec2 is thc0101=1 & thrldec2 & r1 & thc0215=0 { r1 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec1: r1^"," thrldec2 is thc0101=1 & thrldec2 & r1 { r1 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec1: thrldec2 is thc0101=0 & thrldec2 { }
|
||||
thldrlist_dec: { r0 thrldec1 } is thc0000=1 & thrldec1 & r0 & thc0115=0 { r0 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thldrlist_dec: { r0^"," thrldec1 } is thc0000=1 & thrldec1 & r0 { r0 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thldrlist_dec: { thrldec1 } is thc0000=0 & thrldec1 { }
|
||||
thrldec15: pc is thc1515=1 & pc { pc = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec15: is thc1515=0 { }
|
||||
thrldec14: lr^thrldec15 is thc1414=1 & thrldec15 & lr & thc1515=0 { lr = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec14: lr,thrldec15 is thc1414=1 & thrldec15 & lr { lr = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec14: thrldec15 is thc1414=0 & thrldec15 { }
|
||||
thrldec13: sp^thrldec14 is thc1313=1 & thrldec14 & sp & thc1415=0 { sp = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec13: sp,thrldec14 is thc1313=1 & thrldec14 & sp { sp = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec13: thrldec14 is thc1313=0 & thrldec14 { }
|
||||
thrldec12: r12^thrldec13 is thc1212=1 & thrldec13 & r12 & thc1315=0 { r12 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec12: r12,thrldec13 is thc1212=1 & thrldec13 & r12 { r12 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec12: thrldec13 is thc1212=0 & thrldec13 { }
|
||||
thrldec11: r11^thrldec12 is thc1111=1 & thrldec12 & r11 & thc1215=0 { r11 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec11: r11,thrldec12 is thc1111=1 & thrldec12 & r11 { r11 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec11: thrldec12 is thc1111=0 & thrldec12 { }
|
||||
thrldec10: r10^thrldec11 is thc1010=1 & thrldec11 & r10 & thc1115=0 { r10 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec10: r10,thrldec11 is thc1010=1 & thrldec11 & r10 { r10 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec10: thrldec11 is thc1010=0 & thrldec11 { }
|
||||
thrldec9: r9^thrldec10 is thc0909=1 & thrldec10 & r9 & thc1015=0 { r9 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec9: r9,thrldec10 is thc0909=1 & thrldec10 & r9 { r9 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec9: thrldec10 is thc0909=0 & thrldec10 { }
|
||||
thrldec8: r8^thrldec9 is thc0808=1 & thrldec9 & r8 & thc0915=0 { r8 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec8: r8,thrldec9 is thc0808=1 & thrldec9 & r8 { r8 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec8: thrldec9 is thc0808=0 & thrldec9 { }
|
||||
thrldec7: r7^thrldec8 is thc0707=1 & thrldec8 & r7 & thc0815=0 { r7 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec7: r7,thrldec8 is thc0707=1 & thrldec8 & r7 { r7 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec7: thrldec8 is thc0707=0 & thrldec8 { }
|
||||
thrldec6: r6^thrldec7 is thc0606=1 & thrldec7 & r6 & thc0715=0 { r6 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec6: r6,thrldec7 is thc0606=1 & thrldec7 & r6 { r6 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec6: thrldec7 is thc0606=0 & thrldec7 { }
|
||||
thrldec5: r5^thrldec6 is thc0505=1 & thrldec6 & r5 & thc0615=0 { r5 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec5: r5,thrldec6 is thc0505=1 & thrldec6 & r5 { r5 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec5: thrldec6 is thc0505=0 & thrldec6 { }
|
||||
thrldec4: r4^thrldec5 is thc0404=1 & thrldec5 & r4 & thc0515=0 { r4 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec4: r4,thrldec5 is thc0404=1 & thrldec5 & r4 { r4 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec4: thrldec5 is thc0404=0 & thrldec5 { }
|
||||
thrldec3: r3^thrldec4 is thc0303=1 & thrldec4 & r3 & thc0415=0 { r3 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec3: r3,thrldec4 is thc0303=1 & thrldec4 & r3 { r3 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec3: thrldec4 is thc0303=0 & thrldec4 { }
|
||||
thrldec2: r2^thrldec3 is thc0202=1 & thrldec3 & r2 & thc0315=0 { r2 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec2: r2,thrldec3 is thc0202=1 & thrldec3 & r2 { r2 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec2: thrldec3 is thc0202=0 & thrldec3 { }
|
||||
thrldec1: r1^thrldec2 is thc0101=1 & thrldec2 & r1 & thc0215=0 { r1 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec1: r1,thrldec2 is thc0101=1 & thrldec2 & r1 { r1 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thrldec1: thrldec2 is thc0101=0 & thrldec2 { }
|
||||
thldrlist_dec: {r0^thrldec1} is thc0000=1 & thrldec1 & r0 & thc0115=0 { r0 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thldrlist_dec: {r0,thrldec1} is thc0000=1 & thrldec1 & r0 { r0 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
thldrlist_dec: {thrldec1} is thc0000=0 & thrldec1 { }
|
||||
|
||||
@endif # defined(VERSION_6T2) || defined(VERSION_7)
|
||||
|
||||
# thstrlist_dec is the list of registers to be pushed
|
||||
thsdec15: pc is thc1515=1 & pc { *:4 mult_addr = inst_start+4; mult_addr = mult_addr - 4; }
|
||||
thsdec15: is thc1515=0 { }
|
||||
thsdec14: lr thsdec15 is thc1414=1 & thsdec15 & lr & thc1515=0 { * mult_addr=lr; mult_addr = mult_addr - 4; }
|
||||
thsdec14: lr^"," thsdec15 is thc1414=1 & thsdec15 & lr { * mult_addr=lr; mult_addr = mult_addr - 4; }
|
||||
thsdec14: thsdec15 is thc1414=0 & thsdec15 { }
|
||||
thsdec13: sp thsdec14 is thc1313=1 & thsdec14 & sp & thc1415=0 { * mult_addr=sp; mult_addr = mult_addr - 4; }
|
||||
thsdec13: sp^"," thsdec14 is thc1313=1 & thsdec14 & sp { * mult_addr=sp; mult_addr = mult_addr - 4; }
|
||||
thsdec13: thsdec14 is thc1313=0 & thsdec14 { }
|
||||
thsdec12: r12 thsdec13 is thc1212=1 & thsdec13 & r12 & thc1315=0 { * mult_addr=r12; mult_addr = mult_addr - 4; }
|
||||
thsdec12: r12^"," thsdec13 is thc1212=1 & thsdec13 & r12 { * mult_addr=r12; mult_addr = mult_addr - 4; }
|
||||
thsdec12: thsdec13 is thc1212=0 & thsdec13 { }
|
||||
thsdec11: r11 thsdec12 is thc1111=1 & thsdec12 & r11 & thc1215=0 { * mult_addr=r11; mult_addr = mult_addr - 4; }
|
||||
thsdec11: r11^"," thsdec12 is thc1111=1 & thsdec12 & r11 { * mult_addr=r11; mult_addr = mult_addr - 4; }
|
||||
thsdec11: thsdec12 is thc1111=0 & thsdec12 { }
|
||||
thsdec10: r10 thsdec11 is thc1010=1 & thsdec11 & r10 & thc1115=0 { * mult_addr=r10; mult_addr = mult_addr - 4; }
|
||||
thsdec10: r10^"," thsdec11 is thc1010=1 & thsdec11 & r10 { * mult_addr=r10; mult_addr = mult_addr - 4; }
|
||||
thsdec10: thsdec11 is thc1010=0 & thsdec11 { }
|
||||
thsdec9: r9 thsdec10 is thc0909=1 & thsdec10 & r9 & thc1015=0 { * mult_addr=r9; mult_addr = mult_addr - 4; }
|
||||
thsdec9: r9^"," thsdec10 is thc0909=1 & thsdec10 & r9 { * mult_addr=r9; mult_addr = mult_addr - 4; }
|
||||
thsdec9: thsdec10 is thc0909=0 & thsdec10 { }
|
||||
thsdec8: r8 thsdec9 is thc0808=1 & thsdec9 & r8 & thc0915=0 { * mult_addr=r8; mult_addr = mult_addr - 4; }
|
||||
thsdec8: r8^"," thsdec9 is thc0808=1 & thsdec9 & r8 { * mult_addr=r8; mult_addr = mult_addr - 4; }
|
||||
thsdec8: thsdec9 is thc0808=0 & thsdec9 { }
|
||||
thsdec7: r7 thsdec8 is thc0707=1 & thsdec8 & r7 & thc0815=0 { * mult_addr=r7; mult_addr = mult_addr - 4; }
|
||||
thsdec7: r7^"," thsdec8 is thc0707=1 & thsdec8 & r7 { * mult_addr=r7; mult_addr = mult_addr - 4; }
|
||||
thsdec7: thsdec8 is thc0707=0 & thsdec8 { }
|
||||
thsdec6: r6 thsdec7 is thc0606=1 & thsdec7 & r6 & thc0715=0 { * mult_addr=r6; mult_addr = mult_addr - 4; }
|
||||
thsdec6: r6^"," thsdec7 is thc0606=1 & thsdec7 & r6 { * mult_addr=r6; mult_addr = mult_addr - 4; }
|
||||
thsdec6: thsdec7 is thc0606=0 & thsdec7 { }
|
||||
thsdec5: r5 thsdec6 is thc0505=1 & thsdec6 & r5 & thc0615=0 { * mult_addr=r5; mult_addr = mult_addr - 4; }
|
||||
thsdec5: r5^"," thsdec6 is thc0505=1 & thsdec6 & r5 { * mult_addr=r5; mult_addr = mult_addr - 4; }
|
||||
thsdec5: thsdec6 is thc0505=0 & thsdec6 { }
|
||||
thsdec4: r4 thsdec5 is thc0404=1 & thsdec5 & r4 & thc0515=0 { * mult_addr=r4; mult_addr = mult_addr - 4; }
|
||||
thsdec4: r4^"," thsdec5 is thc0404=1 & thsdec5 & r4 { * mult_addr=r4; mult_addr = mult_addr - 4; }
|
||||
thsdec4: thsdec5 is thc0404=0 & thsdec5 { }
|
||||
thsdec3: r3 thsdec4 is thc0303=1 & thsdec4 & r3 & thc0415=0 { * mult_addr=r3; mult_addr = mult_addr - 4; }
|
||||
thsdec3: r3^"," thsdec4 is thc0303=1 & thsdec4 & r3 { * mult_addr=r3; mult_addr = mult_addr - 4; }
|
||||
thsdec3: thsdec4 is thc0303=0 & thsdec4 { }
|
||||
thsdec2: r2 thsdec3 is thc0202=1 & thsdec3 & r2 & thc0415=0 { * mult_addr=r2; mult_addr = mult_addr - 4; }
|
||||
thsdec2: r2^"," thsdec3 is thc0202=1 & thsdec3 & r2 { * mult_addr=r2; mult_addr = mult_addr - 4; }
|
||||
thsdec2: thsdec3 is thc0202=0 & thsdec3 { }
|
||||
thsdec1: r1 thsdec2 is thc0101=1 & thsdec2 & r1 & thc0215=0 { * mult_addr=r1; mult_addr = mult_addr - 4; }
|
||||
thsdec1: r1^"," thsdec2 is thc0101=1 & thsdec2 & r1 { * mult_addr=r1; mult_addr = mult_addr - 4; }
|
||||
thsdec1: thsdec2 is thc0101=0 & thsdec2 { }
|
||||
thstrlist_dec: { r0 thsdec1 } is thc0000=1 & thsdec1 & r0 & thc0115=0 { * mult_addr=r0; mult_addr = mult_addr - 4; }
|
||||
thstrlist_dec: { r0^"," thsdec1 } is thc0000=1 & thsdec1 & r0 { * mult_addr=r0; mult_addr = mult_addr - 4; }
|
||||
thstrlist_dec: { thsdec1 } is thc0000=0 & thsdec1 { }
|
||||
thsdec15: pc is thc1515=1 & pc { *:4 mult_addr = inst_start+4; mult_addr = mult_addr - 4; }
|
||||
thsdec15: is thc1515=0 { }
|
||||
thsdec14: lr is thc1414=1 & thsdec15 & lr & thc1515=0 { * mult_addr=lr; mult_addr = mult_addr - 4; }
|
||||
thsdec14: lr,thsdec15 is thc1414=1 & thsdec15 & lr { * mult_addr=lr; mult_addr = mult_addr - 4; }
|
||||
thsdec14: thsdec15 is thc1414=0 & thsdec15 { }
|
||||
thsdec13: sp is thc1313=1 & sp & thc1415=0 { * mult_addr=sp; mult_addr = mult_addr - 4; }
|
||||
thsdec13: sp,thsdec14 is thc1313=1 & thsdec14 & sp { * mult_addr=sp; mult_addr = mult_addr - 4; }
|
||||
thsdec13: thsdec14 is thc1313=0 & thsdec14 { }
|
||||
thsdec12: r12 is thc1212=1 & r12 & thc1315=0 { * mult_addr=r12; mult_addr = mult_addr - 4; }
|
||||
thsdec12: r12,thsdec13 is thc1212=1 & thsdec13 & r12 { * mult_addr=r12; mult_addr = mult_addr - 4; }
|
||||
thsdec12: thsdec13 is thc1212=0 & thsdec13 { }
|
||||
thsdec11: r11 is thc1111=1 & r11 & thc1215=0 { * mult_addr=r11; mult_addr = mult_addr - 4; }
|
||||
thsdec11: r11,thsdec12 is thc1111=1 & thsdec12 & r11 { * mult_addr=r11; mult_addr = mult_addr - 4; }
|
||||
thsdec11: thsdec12 is thc1111=0 & thsdec12 { }
|
||||
thsdec10: r10 is thc1010=1 & r10 & thc1115=0 { * mult_addr=r10; mult_addr = mult_addr - 4; }
|
||||
thsdec10: r10,thsdec11 is thc1010=1 & thsdec11 & r10 { * mult_addr=r10; mult_addr = mult_addr - 4; }
|
||||
thsdec10: thsdec11 is thc1010=0 & thsdec11 { }
|
||||
thsdec9: r9 is thc0909=1 & r9 & thc1015=0 { * mult_addr=r9; mult_addr = mult_addr - 4; }
|
||||
thsdec9: r9,thsdec10 is thc0909=1 & thsdec10 & r9 { * mult_addr=r9; mult_addr = mult_addr - 4; }
|
||||
thsdec9: thsdec10 is thc0909=0 & thsdec10 { }
|
||||
thsdec8: r8 is thc0808=1 & r8 & thc0915=0 { * mult_addr=r8; mult_addr = mult_addr - 4; }
|
||||
thsdec8: r8,thsdec9 is thc0808=1 & thsdec9 & r8 { * mult_addr=r8; mult_addr = mult_addr - 4; }
|
||||
thsdec8: thsdec9 is thc0808=0 & thsdec9 { }
|
||||
thsdec7: r7 is thc0707=1 & r7 & thc0815=0 { * mult_addr=r7; mult_addr = mult_addr - 4; }
|
||||
thsdec7: r7,thsdec8 is thc0707=1 & thsdec8 & r7 { * mult_addr=r7; mult_addr = mult_addr - 4; }
|
||||
thsdec7: thsdec8 is thc0707=0 & thsdec8 { }
|
||||
thsdec6: r6 is thc0606=1 & r6 & thc0715=0 { * mult_addr=r6; mult_addr = mult_addr - 4; }
|
||||
thsdec6: r6,thsdec7 is thc0606=1 & thsdec7 & r6 { * mult_addr=r6; mult_addr = mult_addr - 4; }
|
||||
thsdec6: thsdec7 is thc0606=0 & thsdec7 { }
|
||||
thsdec5: r5 is thc0505=1 & r5 & thc0615=0 { * mult_addr=r5; mult_addr = mult_addr - 4; }
|
||||
thsdec5: r5,thsdec6 is thc0505=1 & thsdec6 & r5 { * mult_addr=r5; mult_addr = mult_addr - 4; }
|
||||
thsdec5: thsdec6 is thc0505=0 & thsdec6 { }
|
||||
thsdec4: r4 is thc0404=1 & r4 & thc0515=0 { * mult_addr=r4; mult_addr = mult_addr - 4; }
|
||||
thsdec4: r4,thsdec5 is thc0404=1 & thsdec5 & r4 { * mult_addr=r4; mult_addr = mult_addr - 4; }
|
||||
thsdec4: thsdec5 is thc0404=0 & thsdec5 { }
|
||||
thsdec3: r3 is thc0303=1 & r3 & thc0415=0 { * mult_addr=r3; mult_addr = mult_addr - 4; }
|
||||
thsdec3: r3,thsdec4 is thc0303=1 & thsdec4 & r3 { * mult_addr=r3; mult_addr = mult_addr - 4; }
|
||||
thsdec3: thsdec4 is thc0303=0 & thsdec4 { }
|
||||
thsdec2: r2 is thc0202=1 & r2 & thc0415=0 { * mult_addr=r2; mult_addr = mult_addr - 4; }
|
||||
thsdec2: r2,thsdec3 is thc0202=1 & thsdec3 & r2 { * mult_addr=r2; mult_addr = mult_addr - 4; }
|
||||
thsdec2: thsdec3 is thc0202=0 & thsdec3 { }
|
||||
thsdec1: r1 is thc0101=1 & r1 & thc0215=0 { * mult_addr=r1; mult_addr = mult_addr - 4; }
|
||||
thsdec1: r1,thsdec2 is thc0101=1 & thsdec2 & r1 { * mult_addr=r1; mult_addr = mult_addr - 4; }
|
||||
thsdec1: thsdec2 is thc0101=0 & thsdec2 { }
|
||||
thstrlist_dec: {r0} is thc0000=1 & r0 & thc0115=0 { * mult_addr=r0; mult_addr = mult_addr - 4; }
|
||||
thstrlist_dec: {r0,thsdec1} is thc0000=1 & thsdec1 & r0 { * mult_addr=r0; mult_addr = mult_addr - 4; }
|
||||
thstrlist_dec: {thsdec1^} is thc0000=0 & thsdec1 { }
|
||||
|
||||
ldbrace: {ldlist } is ldlist { }
|
||||
stbrace: {strlist } is strlist { }
|
||||
psbrace: { pshlist } is pshlist { }
|
||||
ldbrace: {ldlist} is ldlist { }
|
||||
stbrace: {strlist} is strlist { }
|
||||
psbrace: {pshlist} is pshlist { }
|
||||
|
||||
# Some extra subconstructors for the push and pop instructions
|
||||
pclbrace:{ldlist^"," pc } is ldlist & pc { build ldlist; pc = *mult_addr; mult_addr = mult_addr + 4; }
|
||||
pclbrace:{ pc } is thc0007=0 & pc { pc = *mult_addr; mult_addr = mult_addr + 4; }
|
||||
pcpbrace:{ pshlist^"," lr } is pshlist & lr { mult_addr = mult_addr - 4; *mult_addr = lr; build pshlist; }
|
||||
pcpbrace:{ lr } is thc0007=0 & lr { mult_addr = mult_addr - 4; *mult_addr = lr; }
|
||||
pclbrace:{ldlist,pc} is ldlist & pc { build ldlist; pc = *mult_addr; mult_addr = mult_addr + 4; }
|
||||
pclbrace:{pc} is thc0007=0 & pc { pc = *mult_addr; mult_addr = mult_addr + 4; }
|
||||
pcpbrace:{pshlist,lr} is pshlist & lr { mult_addr = mult_addr - 4; *mult_addr = lr; build pshlist; }
|
||||
pcpbrace:{lr} is thc0007=0 & lr { mult_addr = mult_addr - 4; *mult_addr = lr; }
|
||||
|
||||
@if defined(VERSION_6T2) || defined(VERSION_7)
|
||||
RnIndirect12: [Rn0003,"#"^offset12] is Rn0003; offset12 { local tmp = Rn0003 + offset12; export tmp; }
|
||||
|
|
|
|||
|
|
@ -1049,207 +1049,206 @@ addrmode3: [rn],-rm is P24=0 & U23=0 & c2122=0 & rn & c0811=0 & c0707=1 & c0404
|
|||
|
||||
|
||||
# ldlist_inc is the list of registers to be loaded using IA or IB in Addressing Mode 4
|
||||
linc15: r0 is c0000=1 & r0 { r0 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc15: is c0000=0 { }
|
||||
linc14: linc15 r1 is c0101=1 & linc15 & r1 { r1 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc15: r0 is c0000=1 & r0 { r0 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc15: is c0000=0 { }
|
||||
linc14: linc15,r1 is c0101=1 & linc15 & r1 { r1 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc14: r1 is c0101=1 & c0000=0 & r1 { r1 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc14: linc15 is c0101=0 & linc15 { }
|
||||
linc13: linc14 r2 is c0202=1 & linc14 & r2 { r2 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc14: linc15 is c0101=0 & linc15 { }
|
||||
linc13: linc14,r2 is c0202=1 & linc14 & r2 { r2 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc13: r2 is c0202=1 & c0001=0 & r2 { r2 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc13: linc14 is c0202=0 & linc14 { }
|
||||
linc12: linc13 r3 is c0303=1 & linc13 & r3 { r3 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc13: linc14 is c0202=0 & linc14 { }
|
||||
linc12: linc13,r3 is c0303=1 & linc13 & r3 { r3 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc12: r3 is c0303=1 & c0002=0 & r3 { r3 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc12: linc13 is c0303=0 & linc13 { }
|
||||
linc11: linc12 r4 is c0404=1 & linc12 & r4 { r4 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc12: linc13 is c0303=0 & linc13 { }
|
||||
linc11: linc12,r4 is c0404=1 & linc12 & r4 { r4 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc11: r4 is c0404=1 & c0003=0 & r4 { r4 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc11: linc12 is c0404=0 & linc12 { }
|
||||
linc10: linc11 r5 is c0505=1 & linc11 & r5 { r5 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc11: linc12 is c0404=0 & linc12 { }
|
||||
linc10: linc11,r5 is c0505=1 & linc11 & r5 { r5 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc10: r5 is c0505=1 & c0004=0 & r5 { r5 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc10: linc11 is c0505=0 & linc11 { }
|
||||
linc9: linc10 r6 is c0606=1 & linc10 & r6 { r6 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc10: linc11 is c0505=0 & linc11 { }
|
||||
linc9: linc10,r6 is c0606=1 & linc10 & r6 { r6 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc9: r6 is c0606=1 & c0005=0 & r6 { r6 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc9: linc10 is c0606=0 & linc10 { }
|
||||
linc8: linc9 r7 is c0707=1 & linc9 & r7 { r7 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc9: linc10 is c0606=0 & linc10 { }
|
||||
linc8: linc9,r7 is c0707=1 & linc9 & r7 { r7 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc8: r7 is c0707=1 & c0006=0 & r7 { r7 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc8: linc9 is c0707=0 & linc9 { }
|
||||
linc7: linc8 r8 is c0808=1 & linc8 & r8 { r8 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc8: linc9 is c0707=0 & linc9 { }
|
||||
linc7: linc8,r8 is c0808=1 & linc8 & r8 { r8 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc7: r8 is c0808=1 & c0007=0 & r8 { r8 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc7: linc8 is c0808=0 & linc8 { }
|
||||
linc6: linc7 r9 is c0909=1 & linc7 & r9 { r9 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc7: linc8 is c0808=0 & linc8 { }
|
||||
linc6: linc7,r9 is c0909=1 & linc7 & r9 { r9 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc6: r9 is c0909=1 & c0008=0 & r9 { r9 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc6: linc7 is c0909=0 & linc7 { }
|
||||
linc5: linc6 r10 is c1010=1 & linc6 & r10 { r10 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc6: linc7 is c0909=0 & linc7 { }
|
||||
linc5: linc6,r10 is c1010=1 & linc6 & r10 { r10 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc5: r10 is c1010=1 & c0009=0 & r10 { r10 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc5: linc6 is c1010=0 & linc6 { }
|
||||
linc4: linc5 r11 is c1111=1 & linc5 & r11 { r11 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc5: linc6 is c1010=0 & linc6 { }
|
||||
linc4: linc5,r11 is c1111=1 & linc5 & r11 { r11 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc4: r11 is c1111=1 & c0010=0 & r11 { r11 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc4: linc5 is c1111=0 & linc5 { }
|
||||
linc3: linc4 r12 is c1212=1 & linc4 & r12 { r12 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc4: linc5 is c1111=0 & linc5 { }
|
||||
linc3: linc4,r12 is c1212=1 & linc4 & r12 { r12 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc3: r12 is c1212=1 & c0011=0 & r12 { r12 = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc3: linc4 is c1212=0 & linc4 { }
|
||||
linc2: linc3 sp is c1313=1 & linc3 & sp { sp = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc2: sp is c1313=1 & c0012=0 & sp { sp = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc2: linc3 is c1313=0 & linc3 { }
|
||||
linc1: linc2 lr is c1414=1 & linc2 & lr { lr = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc1: lr is c1414=1 & c0013=0 & lr { lr = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc1: linc2 is c1414=0 & linc2 { }
|
||||
linc0: linc1 pc is c1515=1 & linc1 & pc { pc = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc0: pc is c1515=1 & c0014=0 & pc { pc = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc0: linc1 is c1515=0 & linc1 { }
|
||||
ldlist_inc: {linc0} is linc0 { }
|
||||
linc3: linc4 is c1212=0 & linc4 { }
|
||||
linc2: linc3,sp is c1313=1 & linc3 & sp { sp = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc2: sp is c1313=1 & c0012=0 & sp { sp = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc2: linc3 is c1313=0 & linc3 { }
|
||||
linc1: linc2,lr is c1414=1 & linc2 & lr { lr = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc1: lr is c1414=1 & c0013=0 & lr { lr = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc1: linc2 is c1414=0 & linc2 { }
|
||||
linc0: linc1,pc is c1515=1 & linc1 & pc { pc = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc0: pc is c1515=1 & c0014=0 & pc { pc = * mult_addr; mult_addr = mult_addr + 4; }
|
||||
linc0: linc1 is c1515=0 & linc1 { }
|
||||
ldlist_inc: {linc0} is linc0 { }
|
||||
|
||||
# stlist_inc is the list of registers to be stored using IA or IB in Addressing Mode 4
|
||||
sinc15: r0 is c0000=1 & r0 { * mult_addr = r0; mult_addr = mult_addr + 4; }
|
||||
sinc15: is c0000=0 { }
|
||||
sinc14: sinc15 r1 is c0101=1 & sinc15 & r1 { * mult_addr = r1; mult_addr = mult_addr + 4; }
|
||||
sinc14: r1 is c0101=1 & c0000=0 & r1 { * mult_addr = r1; mult_addr = mult_addr + 4; }
|
||||
sinc14: sinc15 is c0101=0 & sinc15 { }
|
||||
sinc13: sinc14 r2 is c0202=1 & sinc14 & r2 { * mult_addr = r2; mult_addr = mult_addr + 4; }
|
||||
sinc13: r2 is c0202=1 & c0001=0 & r2 { * mult_addr = r2; mult_addr = mult_addr + 4; }
|
||||
sinc13: sinc14 is c0202=0 & sinc14 { }
|
||||
sinc12: sinc13 r3 is c0303=1 & sinc13 & r3 { * mult_addr = r3; mult_addr = mult_addr + 4; }
|
||||
sinc12: r3 is c0303=1 & c0002=0 & r3 { * mult_addr = r3; mult_addr = mult_addr + 4; }
|
||||
sinc12: sinc13 is c0303=0 & sinc13 { }
|
||||
sinc11: sinc12 r4 is c0404=1 & sinc12 & r4 { * mult_addr = r4; mult_addr = mult_addr + 4; }
|
||||
sinc11: r4 is c0404=1 & c0003=0 & r4 { * mult_addr = r4; mult_addr = mult_addr + 4; }
|
||||
sinc11: sinc12 is c0404=0 & sinc12 { }
|
||||
sinc10: sinc11 r5 is c0505=1 & sinc11 & r5 { * mult_addr = r5; mult_addr = mult_addr + 4; }
|
||||
sinc10: r5 is c0505=1 & c0004=0 & r5 { * mult_addr = r5; mult_addr = mult_addr + 4; }
|
||||
sinc10: sinc11 is c0505=0 & sinc11 { }
|
||||
sinc9: sinc10 r6 is c0606=1 & sinc10 & r6 { * mult_addr = r6; mult_addr = mult_addr + 4; }
|
||||
sinc9: r6 is c0606=1 & c0005=0 & r6 { * mult_addr = r6; mult_addr = mult_addr + 4; }
|
||||
sinc9: sinc10 is c0606=0 & sinc10 { }
|
||||
sinc8: sinc9 r7 is c0707=1 & sinc9 & r7 { * mult_addr = r7; mult_addr = mult_addr + 4; }
|
||||
sinc8: r7 is c0707=1 & c0006=0 & r7 { * mult_addr = r7; mult_addr = mult_addr + 4; }
|
||||
sinc8: sinc9 is c0707=0 & sinc9 { }
|
||||
sinc7: sinc8 r8 is c0808=1 & sinc8 & r8 { * mult_addr = r8; mult_addr = mult_addr + 4; }
|
||||
sinc7: r8 is c0808=1 & c0007=0 & r8 { * mult_addr = r8; mult_addr = mult_addr + 4; }
|
||||
sinc7: sinc8 is c0808=0 & sinc8 { }
|
||||
sinc6: sinc7 r9 is c0909=1 & sinc7 & r9 { * mult_addr = r9; mult_addr = mult_addr + 4; }
|
||||
sinc6: r9 is c0909=1 & c0008=0 & r9 { * mult_addr = r9; mult_addr = mult_addr + 4; }
|
||||
sinc6: sinc7 is c0909=0 & sinc7 { }
|
||||
sinc5: sinc6 r10 is c1010=1 & sinc6 & r10 { * mult_addr = r10; mult_addr = mult_addr + 4; }
|
||||
sinc5: r10 is c1010=1 & c0009=0 & r10 { * mult_addr = r10; mult_addr = mult_addr + 4; }
|
||||
sinc5: sinc6 is c1010=0 & sinc6 { }
|
||||
sinc4: sinc5 r11 is c1111=1 & sinc5 & r11 { * mult_addr = r11; mult_addr = mult_addr + 4; }
|
||||
sinc4: r11 is c1111=1 & c0010=0 & r11 { * mult_addr = r11; mult_addr = mult_addr + 4; }
|
||||
sinc4: sinc5 is c1111=0 & sinc5 { }
|
||||
sinc3: sinc4 r12 is c1212=1 & sinc4 & r12 { * mult_addr = r12; mult_addr = mult_addr + 4; }
|
||||
sinc3: r12 is c1212=1 & c0011=0 & r12 { * mult_addr = r12; mult_addr = mult_addr + 4; }
|
||||
sinc3: sinc4 is c1212=0 & sinc4 { }
|
||||
sinc2: sinc3 sp is c1313=1 & sinc3 & sp { * mult_addr = sp; mult_addr = mult_addr + 4; }
|
||||
sinc2: sp is c1313=1 & c0012=0 & sp { * mult_addr = sp; mult_addr = mult_addr + 4; }
|
||||
sinc2: sinc3 is c1313=0 & sinc3 { }
|
||||
sinc1: sinc2 lr is c1414=1 & sinc2 & lr { * mult_addr = lr; mult_addr = mult_addr + 4; }
|
||||
sinc1: lr is c1414=1 & c0013=0 & lr { * mult_addr = lr; mult_addr = mult_addr + 4; }
|
||||
sinc1: sinc2 is c1414=0 & sinc2 { }
|
||||
sinc0: sinc1 pc is c1515=1 & sinc1 & pc { *:4 mult_addr = (inst_start + 8); mult_addr = mult_addr + 4; }
|
||||
sinc0: pc is c1515=1 & c0014=0 & pc { *:4 mult_addr = (inst_start + 8); mult_addr = mult_addr + 4; }
|
||||
sinc0: sinc1 is c1515=0 & sinc1 { }
|
||||
stlist_inc: { sinc0 } is sinc0 { }
|
||||
sinc15: r0 is c0000=1 & r0 { * mult_addr = r0; mult_addr = mult_addr + 4; }
|
||||
sinc15: is c0000=0 { }
|
||||
sinc14: sinc15,r1 is c0101=1 & sinc15 & r1 { * mult_addr = r1; mult_addr = mult_addr + 4; }
|
||||
sinc14: r1 is c0101=1 & c0000=0 & r1 { * mult_addr = r1; mult_addr = mult_addr + 4; }
|
||||
sinc14: sinc15 is c0101=0 & sinc15 { }
|
||||
sinc13: sinc14,r2 is c0202=1 & sinc14 & r2 { * mult_addr = r2; mult_addr = mult_addr + 4; }
|
||||
sinc13: r2 is c0202=1 & c0001=0 & r2 { * mult_addr = r2; mult_addr = mult_addr + 4; }
|
||||
sinc13: sinc14 is c0202=0 & sinc14 { }
|
||||
sinc12: sinc13,r3 is c0303=1 & sinc13 & r3 { * mult_addr = r3; mult_addr = mult_addr + 4; }
|
||||
sinc12: r3 is c0303=1 & c0002=0 & r3 { * mult_addr = r3; mult_addr = mult_addr + 4; }
|
||||
sinc12: sinc13 is c0303=0 & sinc13 { }
|
||||
sinc11: sinc12,r4 is c0404=1 & sinc12 & r4 { * mult_addr = r4; mult_addr = mult_addr + 4; }
|
||||
sinc11: r4 is c0404=1 & c0003=0 & r4 { * mult_addr = r4; mult_addr = mult_addr + 4; }
|
||||
sinc11: sinc12 is c0404=0 & sinc12 { }
|
||||
sinc10: sinc11,r5 is c0505=1 & sinc11 & r5 { * mult_addr = r5; mult_addr = mult_addr + 4; }
|
||||
sinc10: r5 is c0505=1 & c0004=0 & r5 { * mult_addr = r5; mult_addr = mult_addr + 4; }
|
||||
sinc10: sinc11 is c0505=0 & sinc11 { }
|
||||
sinc9: sinc10,r6 is c0606=1 & sinc10 & r6 { * mult_addr = r6; mult_addr = mult_addr + 4; }
|
||||
sinc9: r6 is c0606=1 & c0005=0 & r6 { * mult_addr = r6; mult_addr = mult_addr + 4; }
|
||||
sinc9: sinc10 is c0606=0 & sinc10 { }
|
||||
sinc8: sinc9,r7 is c0707=1 & sinc9 & r7 { * mult_addr = r7; mult_addr = mult_addr + 4; }
|
||||
sinc8: r7 is c0707=1 & c0006=0 & r7 { * mult_addr = r7; mult_addr = mult_addr + 4; }
|
||||
sinc8: sinc9 is c0707=0 & sinc9 { }
|
||||
sinc7: sinc8,r8 is c0808=1 & sinc8 & r8 { * mult_addr = r8; mult_addr = mult_addr + 4; }
|
||||
sinc7: r8 is c0808=1 & c0007=0 & r8 { * mult_addr = r8; mult_addr = mult_addr + 4; }
|
||||
sinc7: sinc8 is c0808=0 & sinc8 { }
|
||||
sinc6: sinc7,r9 is c0909=1 & sinc7 & r9 { * mult_addr = r9; mult_addr = mult_addr + 4; }
|
||||
sinc6: r9 is c0909=1 & c0008=0 & r9 { * mult_addr = r9; mult_addr = mult_addr + 4; }
|
||||
sinc6: sinc7 is c0909=0 & sinc7 { }
|
||||
sinc5: sinc6,r10 is c1010=1 & sinc6 & r10 { * mult_addr = r10; mult_addr = mult_addr + 4; }
|
||||
sinc5: r10 is c1010=1 & c0009=0 & r10 { * mult_addr = r10; mult_addr = mult_addr + 4; }
|
||||
sinc5: sinc6 is c1010=0 & sinc6 { }
|
||||
sinc4: sinc5,r11 is c1111=1 & sinc5 & r11 { * mult_addr = r11; mult_addr = mult_addr + 4; }
|
||||
sinc4: r11 is c1111=1 & c0010=0 & r11 { * mult_addr = r11; mult_addr = mult_addr + 4; }
|
||||
sinc4: sinc5 is c1111=0 & sinc5 { }
|
||||
sinc3: sinc4,r12 is c1212=1 & sinc4 & r12 { * mult_addr = r12; mult_addr = mult_addr + 4; }
|
||||
sinc3: r12 is c1212=1 & c0011=0 & r12 { * mult_addr = r12; mult_addr = mult_addr + 4; }
|
||||
sinc3: sinc4 is c1212=0 & sinc4 { }
|
||||
sinc2: sinc3,sp is c1313=1 & sinc3 & sp { * mult_addr = sp; mult_addr = mult_addr + 4; }
|
||||
sinc2: sp is c1313=1 & c0012=0 & sp { * mult_addr = sp; mult_addr = mult_addr + 4; }
|
||||
sinc2: sinc3 is c1313=0 & sinc3 { }
|
||||
sinc1: sinc2,lr is c1414=1 & sinc2 & lr { * mult_addr = lr; mult_addr = mult_addr + 4; }
|
||||
sinc1: lr is c1414=1 & c0013=0 & lr { * mult_addr = lr; mult_addr = mult_addr + 4; }
|
||||
sinc1: sinc2 is c1414=0 & sinc2 { }
|
||||
sinc0: sinc1,pc is c1515=1 & sinc1 & pc { *:4 mult_addr = (inst_start + 8); mult_addr = mult_addr + 4; }
|
||||
sinc0: pc is c1515=1 & c0014=0 & pc { *:4 mult_addr = (inst_start + 8); mult_addr = mult_addr + 4; }
|
||||
sinc0: sinc1 is c1515=0 & sinc1 { }
|
||||
stlist_inc: {sinc0} is sinc0 { }
|
||||
|
||||
|
||||
# ldlist_dec is the list of registers to be loaded using DA or DB in Addressing Mode 4
|
||||
ldec15: pc is c1515=1 & pc { pc = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec15: is c1515=0 { }
|
||||
ldec14: lr ldec15 is c1414=1 & ldec15 & lr { lr = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec14: lr is c1414=1 & c1515=0 & lr { lr = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec14: ldec15 is c1414=0 & ldec15 { }
|
||||
ldec13: sp ldec14 is c1313=1 & ldec14 & sp { sp = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec13: sp is c1313=1 & c1415=0 & sp { sp = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec13: ldec14 is c1313=0 & ldec14 { }
|
||||
ldec12: r12 ldec13 is c1212=1 & ldec13 & r12 { r12 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec12: r12 is c1212=1 & c1315=0 & r12 { r12 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec12: ldec13 is c1212=0 & ldec13 { }
|
||||
ldec11: r11 ldec12 is c1111=1 & ldec12 & r11 { r11 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec11: r11 is c1111=1 & c1215=0 & r11 { r11 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec11: ldec12 is c1111=0 & ldec12 { }
|
||||
ldec10: r10 ldec11 is c1010=1 & ldec11 & r10 { r10 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec10: r10 is c1010=1 & c1115=0 & r10 { r10 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec10: ldec11 is c1010=0 & ldec11 { }
|
||||
ldec9: r9 ldec10 is c0909=1 & ldec10 & r9 { r9 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec9: r9 is c0909=1 & c1015=0 & r9 { r9 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec9: ldec10 is c0909=0 & ldec10 { }
|
||||
ldec8: r8 ldec9 is c0808=1 & ldec9 & r8 { r8 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec8: r8 is c0808=1 & c0915=0 & r8 { r8 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec8: ldec9 is c0808=0 & ldec9 { }
|
||||
ldec7: r7 ldec8 is c0707=1 & ldec8 & r7 { r7 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec7: r7 is c0707=1 & c0815=0 & r7 { r7 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec7: ldec8 is c0707=0 & ldec8 { }
|
||||
ldec6: r6 ldec7 is c0606=1 & ldec7 & r6 { r6 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec6: r6 is c0606=1 & c0715=0 & r6 { r6 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec6: ldec7 is c0606=0 & ldec7 { }
|
||||
ldec5: r5 ldec6 is c0505=1 & ldec6 & r5 { r5 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec5: r5 is c0505=1 & c0615=0 & r5 { r5 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec5: ldec6 is c0505=0 & ldec6 { }
|
||||
ldec4: r4 ldec5 is c0404=1 & ldec5 & r4 { r4 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec4: r4 is c0404=1 & c0515=0 & r4 { r4 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec4: ldec5 is c0404=0 & ldec5 { }
|
||||
ldec3: r3 ldec4 is c0303=1 & ldec4 & r3 { r3 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec3: r3 is c0303=1 & c0415=0 & r3 { r3 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec3: ldec4 is c0303=0 & ldec4 { }
|
||||
ldec2: r2 ldec3 is c0202=1 & ldec3 & r2 { r2 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec2: r2 is c0202=1 & c0315=0 & r2 { r2 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec2: ldec3 is c0202=0 & ldec3 { }
|
||||
ldec1: r1 ldec2 is c0101=1 & ldec2 & r1 { r1 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec1: r1 is c0101=1 & c0215=0 & r1 { r1 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec1: ldec2 is c0101=0 & ldec2 { }
|
||||
ldec0: r0 ldec1 is c0000=1 & ldec1 & r0 { r0 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec0: r0 is c0000=1 & c0115=0 & r0 { r0 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec0: ldec1 is c0000=0 & ldec1 { }
|
||||
ldlist_dec: { ldec0 } is ldec0 { }
|
||||
ldec15: pc is c1515=1 & pc { pc = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec15: is c1515=0 { }
|
||||
ldec14: lr,ldec15 is c1414=1 & ldec15 & lr { lr = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec14: lr is c1414=1 & c1515=0 & lr { lr = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec14: ldec15 is c1414=0 & ldec15 { }
|
||||
ldec13: sp,ldec14 is c1313=1 & ldec14 & sp { sp = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec13: sp is c1313=1 & c1415=0 & sp { sp = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec13: ldec14 is c1313=0 & ldec14 { }
|
||||
ldec12: r12,ldec13 is c1212=1 & ldec13 & r12 { r12 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec12: r12 is c1212=1 & c1315=0 & r12 { r12 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec12: ldec13 is c1212=0 & ldec13 { }
|
||||
ldec11: r11,ldec12 is c1111=1 & ldec12 & r11 { r11 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec11: r11 is c1111=1 & c1215=0 & r11 { r11 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec11: ldec12 is c1111=0 & ldec12 { }
|
||||
ldec10: r10,ldec11 is c1010=1 & ldec11 & r10 { r10 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec10: r10 is c1010=1 & c1115=0 & r10 { r10 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec10: ldec11 is c1010=0 & ldec11 { }
|
||||
ldec9: r9,ldec10 is c0909=1 & ldec10 & r9 { r9 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec9: r9 is c0909=1 & c1015=0 & r9 { r9 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec9: ldec10 is c0909=0 & ldec10 { }
|
||||
ldec8: r8,ldec9 is c0808=1 & ldec9 & r8 { r8 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec8: r8 is c0808=1 & c0915=0 & r8 { r8 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec8: ldec9 is c0808=0 & ldec9 { }
|
||||
ldec7: r7,ldec8 is c0707=1 & ldec8 & r7 { r7 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec7: r7 is c0707=1 & c0815=0 & r7 { r7 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec7: ldec8 is c0707=0 & ldec8 { }
|
||||
ldec6: r6,ldec7 is c0606=1 & ldec7 & r6 { r6 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec6: r6 is c0606=1 & c0715=0 & r6 { r6 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec6: ldec7 is c0606=0 & ldec7 { }
|
||||
ldec5: r5,ldec6 is c0505=1 & ldec6 & r5 { r5 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec5: r5 is c0505=1 & c0615=0 & r5 { r5 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec5: ldec6 is c0505=0 & ldec6 { }
|
||||
ldec4: r4,ldec5 is c0404=1 & ldec5 & r4 { r4 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec4: r4 is c0404=1 & c0515=0 & r4 { r4 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec4: ldec5 is c0404=0 & ldec5 { }
|
||||
ldec3: r3,ldec4 is c0303=1 & ldec4 & r3 { r3 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec3: r3 is c0303=1 & c0415=0 & r3 { r3 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec3: ldec4 is c0303=0 & ldec4 { }
|
||||
ldec2: r2,ldec3 is c0202=1 & ldec3 & r2 { r2 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec2: r2 is c0202=1 & c0315=0 & r2 { r2 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec2: ldec3 is c0202=0 & ldec3 { }
|
||||
ldec1: r1,ldec2 is c0101=1 & ldec2 & r1 { r1 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec1: r1 is c0101=1 & c0215=0 & r1 { r1 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec1: ldec2 is c0101=0 & ldec2 { }
|
||||
ldec0: r0,ldec1 is c0000=1 & ldec1 & r0 { r0 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec0: r0 is c0000=1 & c0115=0 & r0 { r0 = * mult_addr; mult_addr = mult_addr - 4; }
|
||||
ldec0: ldec1 is c0000=0 & ldec1 { }
|
||||
ldlist_dec: {ldec0} is ldec0 { }
|
||||
|
||||
# stlist_dec is the list of registers to be stored using DA or DB in Addressing Mode 4
|
||||
sdec15: pc is c1515=1 & pc { *:4 mult_addr = (inst_start + 8); mult_addr = mult_addr - 4; }
|
||||
sdec15: is c1515=0 { }
|
||||
sdec14: lr sdec15 is c1414=1 & sdec15 & lr { * mult_addr=lr; mult_addr = mult_addr - 4; }
|
||||
sdec14: lr is c1414=1 & c1515=0 & lr { * mult_addr=lr; mult_addr = mult_addr - 4; }
|
||||
sdec14: sdec15 is c1414=0 & sdec15 { }
|
||||
sdec13: sp sdec14 is c1313=1 & sdec14 & sp { * mult_addr=sp; mult_addr = mult_addr - 4; }
|
||||
sdec13: sp is c1313=1 & c1415=0 & sp { * mult_addr=sp; mult_addr = mult_addr - 4; }
|
||||
sdec13: sdec14 is c1313=0 & sdec14 { }
|
||||
sdec12: r12 sdec13 is c1212=1 & sdec13 & r12 { * mult_addr=r12; mult_addr = mult_addr - 4; }
|
||||
sdec12: r12 is c1212=1 & c1315=0 & r12 { * mult_addr=r12; mult_addr = mult_addr - 4; }
|
||||
sdec12: sdec13 is c1212=0 & sdec13 { }
|
||||
sdec11: r11 sdec12 is c1111=1 & sdec12 & r11 { * mult_addr=r11; mult_addr = mult_addr - 4; }
|
||||
sdec11: r11 is c1111=1 & c1215=0 & r11 { * mult_addr=r11; mult_addr = mult_addr - 4; }
|
||||
sdec11: sdec12 is c1111=0 & sdec12 { }
|
||||
sdec10: r10 sdec11 is c1010=1 & sdec11 & r10 { * mult_addr=r10; mult_addr = mult_addr - 4; }
|
||||
sdec10: r10 is c1010=1 & c1115=0 & r10 { * mult_addr=r10; mult_addr = mult_addr - 4; }
|
||||
sdec10: sdec11 is c1010=0 & sdec11 { }
|
||||
sdec9: r9 sdec10 is c0909=1 & sdec10 & r9 { * mult_addr=r9; mult_addr = mult_addr - 4; }
|
||||
sdec9: r9 is c0909=1 & c1015=0 & r9 { * mult_addr=r9; mult_addr = mult_addr - 4; }
|
||||
sdec9: sdec10 is c0909=0 & sdec10 { }
|
||||
sdec8: r8 sdec9 is c0808=1 & sdec9 & r8 { * mult_addr=r8; mult_addr = mult_addr - 4; }
|
||||
sdec8: r8 is c0808=1 & c0915=0 & r8 { * mult_addr=r8; mult_addr = mult_addr - 4; }
|
||||
sdec8: sdec9 is c0808=0 & sdec9 { }
|
||||
sdec7: r7 sdec8 is c0707=1 & sdec8 & r7 { * mult_addr=r7; mult_addr = mult_addr - 4; }
|
||||
sdec7: r7 is c0707=1 & c0815=0 & r7 { * mult_addr=r7; mult_addr = mult_addr - 4; }
|
||||
sdec7: sdec8 is c0707=0 & sdec8 { }
|
||||
sdec6: r6 sdec7 is c0606=1 & sdec7 & r6 { * mult_addr=r6; mult_addr = mult_addr - 4; }
|
||||
sdec6: r6 is c0606=1 & c0715=0 & r6 { * mult_addr=r6; mult_addr = mult_addr - 4; }
|
||||
sdec6: sdec7 is c0606=0 & sdec7 { }
|
||||
sdec5: r5 sdec6 is c0505=1 & sdec6 & r5 { * mult_addr=r5; mult_addr = mult_addr - 4; }
|
||||
sdec5: r5 is c0505=1 & c0615=0 & r5 { * mult_addr=r5; mult_addr = mult_addr - 4; }
|
||||
sdec5: sdec6 is c0505=0 & sdec6 { }
|
||||
sdec4: r4 sdec5 is c0404=1 & sdec5 & r4 { * mult_addr=r4; mult_addr = mult_addr - 4; }
|
||||
sdec4: r4 is c0404=1 & c0515=0 & r4 { * mult_addr=r4; mult_addr = mult_addr - 4; }
|
||||
sdec4: sdec5 is c0404=0 & sdec5 { }
|
||||
sdec3: r3 sdec4 is c0303=1 & sdec4 & r3 { * mult_addr=r3; mult_addr = mult_addr - 4; }
|
||||
sdec3: r3 is c0303=1 & c0415=0 & r3 { * mult_addr=r3; mult_addr = mult_addr - 4; }
|
||||
sdec3: sdec4 is c0303=0 & sdec4 { }
|
||||
sdec2: r2 sdec3 is c0202=1 & sdec3 & r2 { * mult_addr=r2; mult_addr = mult_addr - 4; }
|
||||
sdec2: r2 is c0202=1 & c0315=0 & r2 { * mult_addr=r2; mult_addr = mult_addr - 4; }
|
||||
sdec2: sdec3 is c0202=0 & sdec3 { }
|
||||
sdec1: r1 sdec2 is c0101=1 & sdec2 & r1 { * mult_addr=r1; mult_addr = mult_addr - 4; }
|
||||
sdec1: r1 is c0101=1 & c0215=0 & r1 { * mult_addr=r1; mult_addr = mult_addr - 4; }
|
||||
sdec1: sdec2 is c0101=0 & sdec2 { }
|
||||
sdec15: is c1515=0 { }
|
||||
sdec14: lr,sdec15 is c1414=1 & sdec15 & lr { * mult_addr=lr; mult_addr = mult_addr - 4; }
|
||||
sdec14: lr is c1414=1 & c1515=0 & lr { * mult_addr=lr; mult_addr = mult_addr - 4; }
|
||||
sdec14: sdec15 is c1414=0 & sdec15 { }
|
||||
sdec13: sp,sdec14 is c1313=1 & sdec14 & sp { * mult_addr=sp; mult_addr = mult_addr - 4; }
|
||||
sdec13: sp is c1313=1 & c1415=0 & sp { * mult_addr=sp; mult_addr = mult_addr - 4; }
|
||||
sdec13: sdec14 is c1313=0 & sdec14 { }
|
||||
sdec12: r12,sdec13 is c1212=1 & sdec13 & r12 { * mult_addr=r12; mult_addr = mult_addr - 4; }
|
||||
sdec12: r12 is c1212=1 & c1315=0 & r12 { * mult_addr=r12; mult_addr = mult_addr - 4; }
|
||||
sdec12: sdec13 is c1212=0 & sdec13 { }
|
||||
sdec11: r11,sdec12 is c1111=1 & sdec12 & r11 { * mult_addr=r11; mult_addr = mult_addr - 4; }
|
||||
sdec11: r11 is c1111=1 & c1215=0 & r11 { * mult_addr=r11; mult_addr = mult_addr - 4; }
|
||||
sdec11: sdec12 is c1111=0 & sdec12 { }
|
||||
sdec10: r10,sdec11 is c1010=1 & sdec11 & r10 { * mult_addr=r10; mult_addr = mult_addr - 4; }
|
||||
sdec10: r10 is c1010=1 & c1115=0 & r10 { * mult_addr=r10; mult_addr = mult_addr - 4; }
|
||||
sdec10: sdec11 is c1010=0 & sdec11 { }
|
||||
sdec9: r9,sdec10 is c0909=1 & sdec10 & r9 { * mult_addr=r9; mult_addr = mult_addr - 4; }
|
||||
sdec9: r9 is c0909=1 & c1015=0 & r9 { * mult_addr=r9; mult_addr = mult_addr - 4; }
|
||||
sdec9: sdec10 is c0909=0 & sdec10 { }
|
||||
sdec8: r8,sdec9 is c0808=1 & sdec9 & r8 { * mult_addr=r8; mult_addr = mult_addr - 4; }
|
||||
sdec8: r8 is c0808=1 & c0915=0 & r8 { * mult_addr=r8; mult_addr = mult_addr - 4; }
|
||||
sdec8: sdec9 is c0808=0 & sdec9 { }
|
||||
sdec7: r7,sdec8 is c0707=1 & sdec8 & r7 { * mult_addr=r7; mult_addr = mult_addr - 4; }
|
||||
sdec7: r7 is c0707=1 & c0815=0 & r7 { * mult_addr=r7; mult_addr = mult_addr - 4; }
|
||||
sdec7: sdec8 is c0707=0 & sdec8 { }
|
||||
sdec6: r6,sdec7 is c0606=1 & sdec7 & r6 { * mult_addr=r6; mult_addr = mult_addr - 4; }
|
||||
sdec6: r6 is c0606=1 & c0715=0 & r6 { * mult_addr=r6; mult_addr = mult_addr - 4; }
|
||||
sdec6: sdec7 is c0606=0 & sdec7 { }
|
||||
sdec5: r5,sdec6 is c0505=1 & sdec6 & r5 { * mult_addr=r5; mult_addr = mult_addr - 4; }
|
||||
sdec5: r5 is c0505=1 & c0615=0 & r5 { * mult_addr=r5; mult_addr = mult_addr - 4; }
|
||||
sdec5: sdec6 is c0505=0 & sdec6 { }
|
||||
sdec4: r4,sdec5 is c0404=1 & sdec5 & r4 { * mult_addr=r4; mult_addr = mult_addr - 4; }
|
||||
sdec4: r4 is c0404=1 & c0515=0 & r4 { * mult_addr=r4; mult_addr = mult_addr - 4; }
|
||||
sdec4: sdec5 is c0404=0 & sdec5 { }
|
||||
sdec3: r3,sdec4 is c0303=1 & sdec4 & r3 { * mult_addr=r3; mult_addr = mult_addr - 4; }
|
||||
sdec3: r3 is c0303=1 & c0415=0 & r3 { * mult_addr=r3; mult_addr = mult_addr - 4; }
|
||||
sdec3: sdec4 is c0303=0 & sdec4 { }
|
||||
sdec2: r2,sdec3 is c0202=1 & sdec3 & r2 { * mult_addr=r2; mult_addr = mult_addr - 4; }
|
||||
sdec2: r2 is c0202=1 & c0315=0 & r2 { * mult_addr=r2; mult_addr = mult_addr - 4; }
|
||||
sdec2: sdec3 is c0202=0 & sdec3 { }
|
||||
sdec1: r1,sdec2 is c0101=1 & sdec2 & r1 { * mult_addr=r1; mult_addr = mult_addr - 4; }
|
||||
sdec1: r1 is c0101=1 & c0215=0 & r1 { * mult_addr=r1; mult_addr = mult_addr - 4; }
|
||||
sdec1: sdec2 is c0101=0 & sdec2 { }
|
||||
sdec0: r0,sdec1 is c0000=1 & sdec1 & r0 { * mult_addr=r0; mult_addr = mult_addr - 4; }
|
||||
sdec0: r0 is c0000=1 & c0115=0 & r0 { * mult_addr=r0; mult_addr = mult_addr - 4; }
|
||||
sdec0: sdec1 is c0000=0 & sdec1 { }
|
||||
|
||||
sdec0: r0 sdec1 is c0000=1 & sdec1 & r0 { * mult_addr=r0; mult_addr = mult_addr - 4; }
|
||||
sdec0: r0 is c0000=1 & c0115=0 & r0 { * mult_addr=r0; mult_addr = mult_addr - 4; }
|
||||
sdec0: sdec1 is c0000=0 & sdec1 { }
|
||||
|
||||
stlist_dec: {sdec0} is sdec0 { }
|
||||
stlist_dec: {sdec0} is sdec0 { }
|
||||
|
||||
# reglist deals with Addressing Mode 4
|
||||
# it takes care of bits 0-27
|
||||
|
|
|
|||
Loading…
Reference in a new issue