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https://github.com/NationalSecurityAgency/ghidra
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[tricore] Improved DVINIT instructions
DVINIT instruction operate better using the even/odd pair for the initialization instead of using the 64-bit register. Reported by @esaulenka
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@ -2092,11 +2092,16 @@ SC: [a10]const0815Z10zz is PCPMode=0 & a10 & const0815Z10zz & op0003=8 & op0404=
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@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)
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@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)
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# DVINIT E[c], D[a], D[b] (RR)
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# DVINIT E[c], D[a], D[b] (RR)
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:dvinit Re2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Re2831 & op1627=0x1a0
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:dvinit Ree2831/Reo2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Ree2831 & Reo2831 & op1627=0x1a0
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{
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{
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#TODO divide sequence
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#TODO divide sequence
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Re2831 = sext(Rd0811);
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local dividend:4 = Rd0811;
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$(PSW_V) = ((Rd1215 == 0) || ((Rd1215 == 0xFFFFFFFF) && (Rd0811 == 0x80000000)));
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local divisor:4 = Rd1215;
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Ree2831 = dividend;
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Reo2831 = 0xFFFFFFFF * zext(dividend[31,1]);
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$(PSW_V) = ((divisor == 0) || ((divisor == 0xFFFFFFFF) && (dividend == 0x80000000)));
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$(PSW_SV) = $(PSW_V) | $(PSW_SV);
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$(PSW_SV) = $(PSW_V) | $(PSW_SV);
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$(PSW_AV) = 0;
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$(PSW_AV) = 0;
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}
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}
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@ -2104,13 +2109,15 @@ SC: [a10]const0815Z10zz is PCPMode=0 & a10 & const0815Z10zz & op0003=8 & op0404=
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@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)
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@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)
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# DVINIT.B E[c], D[a], D[b] (RR)
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# DVINIT.B E[c], D[a], D[b] (RR)
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:dvinit.b Re2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Re2831 & op1627=0x5a0
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:dvinit.b Ree2831/Reo2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Ree2831 & Reo2831 & op1627=0x5a0
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{
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{
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#TODO divide sequence
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#TODO divide sequence
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local quotient_sign = !(Rd0811[31,1] == Rd1215[31,1]);
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local dividend:4 = Rd0811;
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Re2831[24,40] = sext(Rd0811);
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local divisor:4 = Rd1215;
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ternary(Re2831[0,24], quotient_sign, 0xFFFFFF, 0);
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local quotient_sign = !(dividend[31,1] == divisor[31,1]);
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$(PSW_V) = ((Rd1215 == 0) || ((Rd1215 == 0xFFFFFFFF) && (Rd0811 == 0xFFFFFF80)));
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Ree2831 = (dividend << 24) | (0xFFFFFF * zext(quotient_sign));
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Reo2831 = dividend s>> 8;
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$(PSW_V) = ((divisor == 0) || ((divisor == 0xFFFFFFFF) && (dividend == 0xFFFFFF80)));
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$(PSW_SV) = $(PSW_V) | $(PSW_SV);
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$(PSW_SV) = $(PSW_V) | $(PSW_SV);
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$(PSW_AV) = 0;
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$(PSW_AV) = 0;
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}
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}
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@ -2118,11 +2125,15 @@ SC: [a10]const0815Z10zz is PCPMode=0 & a10 & const0815Z10zz & op0003=8 & op0404=
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@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)
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@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)
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# DVINIT.BU E[c], D[a], D[b] (RR)
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# DVINIT.BU E[c], D[a], D[b] (RR)
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:dvinit.bu Re2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Re2831 & op1627=0x4a0
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:dvinit.bu Ree2831/Reo2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Ree2831 & Reo2831 & op1627=0x4a0
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{
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{
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#TODO divide sequence
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#TODO divide sequence
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Re2831 = zext(Rd0811) << 24;
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local dividend:4 = Rd0811; # D[a]
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$(PSW_V) = (Rd1215 == 0);
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local divisor:4 = Rd1215; # D[b]
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Ree2831 = dividend << 24;
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Reo2831 = dividend >> 8;
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$(PSW_V) = (divisor == 0);
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$(PSW_SV) = $(PSW_V) | $(PSW_SV);
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$(PSW_SV) = $(PSW_V) | $(PSW_SV);
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$(PSW_AV) = 0;
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$(PSW_AV) = 0;
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}
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}
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@ -2130,12 +2141,16 @@ SC: [a10]const0815Z10zz is PCPMode=0 & a10 & const0815Z10zz & op0003=8 & op0404=
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@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)
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@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)
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# DVINIT.H E[c], D[a], D[b] (RR)
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# DVINIT.H E[c], D[a], D[b] (RR)
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:dvinit.h Re2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Re2831 & op1627=0x3a0
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:dvinit.h Ree2831/Reo2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Ree2831 & Reo2831 & op1627=0x3a0
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{
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{
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#TODO divide sequence
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#TODO divide sequence
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local quotient_sign = !(Rd0811[31,1] == Rd1215[31,1]);
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local dividend:4 = Rd0811; # D[a]
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Re2831 = (sext(Rd0811) << 16) | zext(quotient_sign * 0xffff);
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local divisor:4 = Rd1215; # D[b]
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$(PSW_V) = ((Rd1215 == 0) || ((Rd1215 == 0xFFFFFFFF) && (Rd0811 == 0xFFFF8000)));
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local quotient_sign = !(dividend[31,1] == divisor[31,1]);
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Ree2831 = (dividend << 16) | (zext(quotient_sign) * 0xFFFF);
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Reo2831 = dividend s>> 16;
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$(PSW_V) = ((divisor == 0) || ((divisor == 0xFFFFFFFF) && (dividend == 0xFFFF8000)));
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$(PSW_SV) = $(PSW_V) | $(PSW_SV);
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$(PSW_SV) = $(PSW_V) | $(PSW_SV);
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$(PSW_AV) = 0;
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$(PSW_AV) = 0;
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}
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}
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@ -2143,11 +2158,15 @@ SC: [a10]const0815Z10zz is PCPMode=0 & a10 & const0815Z10zz & op0003=8 & op0404=
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@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)
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@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)
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# DVINIT.HU E[c], D[a], D[b] (RR)
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# DVINIT.HU E[c], D[a], D[b] (RR)
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:dvinit.hu Re2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Re2831 & op1627=0x2a0
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:dvinit.hu Ree2831/Reo2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Ree2831 & Reo2831 & op1627=0x2a0
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{
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{
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#TODO divide sequence
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#TODO divide sequence
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Re2831 = zext(Rd0811) << 16;
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local dividend:4 = Rd0811; # D[a]
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$(PSW_V) = (Rd1215 == 0);
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local divisor:4 = Rd1215; # D[b]
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Ree2831 = dividend << 16;
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Reo2831 = dividend >> 16;
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$(PSW_V) = (divisor == 0);
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$(PSW_SV) = $(PSW_V) | $(PSW_SV);
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$(PSW_SV) = $(PSW_V) | $(PSW_SV);
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$(PSW_AV) = 0;
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$(PSW_AV) = 0;
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}
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}
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@ -2158,10 +2177,12 @@ SC: [a10]const0815Z10zz is PCPMode=0 & a10 & const0815Z10zz & op0003=8 & op0404=
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:dvinit.u Ree2831/Reo2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Ree2831 & Reo2831 & op1627=0xa0
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:dvinit.u Ree2831/Reo2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Ree2831 & Reo2831 & op1627=0xa0
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{
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{
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#TODO divide sequence
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#TODO divide sequence
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local tmp:4 = Rd0811;
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local dividend:4 = Rd0811; # D[a]
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local divisor:4 = Rd1215; # D[b]
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Ree2831 = dividend;
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Reo2831 = 0;
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Reo2831 = 0;
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Ree2831 = tmp;
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$(PSW_V) = (divisor == 0);
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$(PSW_V) = (Rd1215 == 0);
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$(PSW_SV) = $(PSW_V) | $(PSW_SV);
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$(PSW_SV) = $(PSW_V) | $(PSW_SV);
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$(PSW_AV) = 0;
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$(PSW_AV) = 0;
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}
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}
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