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https://github.com/NationalSecurityAgency/ghidra
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GP-1656: Simplified semantics of several PA-RISC float instructions
This commit is contained in:
ghidorahrex
parent
a290a4c8ae
commit
b39aaaedc0
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@ -1640,17 +1640,20 @@ define pcodeop diag;
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FPRT32 = float2float(FPR232);
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}
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:FCNV^fpsf^fpdf FPR264,FPRT64 is opfam=0x0C & fpclass=1 & fpc1sub=0 & fpc1sub2=0 & sfu=0 & bit5=0 & FPR264 & FPRT64 & fpsf & fpdf & freg2sgl & fptsgl {
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:FCNV^fpsf^fpdf FPR264,FPRT64 is opfam=0x0C & fpclass=1 & fpc1sub=0 & fpc1sub2=0 & sfu=0 & bit5=0 & FPR264 & FPRT64 & fpsf & fpsfraw=0 & fpdf & freg2sgl & fptsgl {
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# if src format is sgl, this is sgl to dbl
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# if src format is dbl, this is dbl to sgl
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# sgl to sgl or dbl to dbl don't make sense
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# and we don't support quad right now
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if (fpsf == 0:1) goto <SGL2DBL>;
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fptsgl = float2float(FPR264);
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goto <DONE>;
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<SGL2DBL>
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FPRT64 = float2float(freg2sgl);
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<DONE>
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}
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:FCNV^fpsf^fpdf FPR264,FPRT64 is opfam=0x0C & fpclass=1 & fpc1sub=0 & fpc1sub2=0 & sfu=0 & bit5=0 & FPR264 & FPRT64 & fpsf & fpsfraw=1 & fpdf & freg2sgl & fptsgl {
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# if src format is sgl, this is sgl to dbl
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# if src format is dbl, this is dbl to sgl
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# sgl to sgl or dbl to dbl don't make sense
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# and we don't support quad right now
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fptsgl = float2float(FPR264);
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}
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:FCNVXF^fpsf^fpdf FPR232,FPRT32 is opfam=0x0E & fpclass=1 & fpc1sub=1 & fpc1sub2=0 & FPR232 & FPRT32 & fpsf & fpdf {
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@ -1659,81 +1662,64 @@ define pcodeop diag;
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# int2float -- support single/double size ints and single/double floats
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# so handle 4 different cases
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:FCNVXF^fixedsf^fpdf FPR264,FPRT64 is opfam=0x0C & fpclass=1 & fpc1sub=1 & fpc1sub2=0 & FPR264 & FPRT64 & sfu=0 & fixedsf & fpdf & fptsgl & freg2sgl & fpsfraw & fpdfraw {
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srcIsSgl:1 = ((fpsfraw:1 == 0:1));
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srcIsDbl:1 = ((fpsfraw:1 != 0:1));
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destIsSgl:1 = ((fpdfraw:1 == 0:1));
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destIsDbl:1 = ((fpdfraw:1 != 0:1));
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isSS:1 = srcIsSgl && destIsSgl;
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isSD:1 = srcIsSgl && destIsDbl;
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isDS:1 = srcIsDbl && destIsSgl;
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# isDD:1 = srcIsDbl && destIsDbl;
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if (isSS) goto <SGLSGL>;
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if (isSD) goto <SGLDBL>;
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if (isDS) goto <DBLSGL>;
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FPRT64 = int2float(FPR264);
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goto <DONE>;
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<SGLDBL>
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FPRT64 = int2float(freg2sgl);
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goto <DONE>;
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<DBLSGL>
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fptsgl = int2float(FPR264);
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goto <DONE>;
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<SGLSGL>
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:FCNVXF^fixedsf^fpdf FPR264,FPRT64 is opfam=0x0C & fpclass=1 & fpc1sub=1 & fpc1sub2=0 & FPR264 & FPRT64 & sfu=0 & fixedsf & fpdf & fptsgl & freg2sgl & fpsfraw=0 & fpdfraw=0 {
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fptsgl = int2float(freg2sgl);
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<DONE>
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}
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:FCNVXF^fixedsf^fpdf FPR264,FPRT64 is opfam=0x0C & fpclass=1 & fpc1sub=1 & fpc1sub2=0 & FPR264 & FPRT64 & sfu=0 & fixedsf & fpdf & fptsgl & freg2sgl & fpsfraw=0 & fpdfraw=1 {
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FPRT64 = int2float(freg2sgl);
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}
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:FCNVXF^fixedsf^fpdf FPR264,FPRT64 is opfam=0x0C & fpclass=1 & fpc1sub=1 & fpc1sub2=0 & FPR264 & FPRT64 & sfu=0 & fixedsf & fpdf & fptsgl & freg2sgl & fpsfraw=1 & fpdfraw=0 {
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fptsgl = int2float(FPR264);
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}
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:FCNVXF^fixedsf^fpdf FPR264,FPRT64 is opfam=0x0C & fpclass=1 & fpc1sub=1 & fpc1sub2=0 & FPR264 & FPRT64 & sfu=0 & fixedsf & fpdf & fptsgl & freg2sgl & fpsfraw=1 & fpdfraw=1 {
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FPRT64 = int2float(FPR264);
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}
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:FCNVFX^fpsf^fixeddf FPR232,FPRT32 is opfam=0x0E & fpclass=1 & fpc1sub=2 & fpc1sub2=0 & FPR232 & FPRT32 & fpsf & fixeddf {
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temp:4 = round(FPR232);
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FPRT32 = trunc(temp);
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}
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:FCNVFX^fpsf^fixeddf FPR264,FPRT64 is opfam=0x0C & fpclass=1 & fpc1sub=2 & fpc1sub2=0 & sfu=0 & FPR264 & FPRT64 & fpsf & fixeddf & fptsgl & freg2sgl {
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# figure out if the value in the fp register is single or double precision
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# the register is always specified as a 64 bit register, so that doesn't tell us the size, we must use the fpsf format
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temp:8 = 0;
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if (fpsf == 1:1) goto <DOUBLE>;
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temp = float2float(freg2sgl); # convert single precision to double
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goto <CONVERT>;
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<DOUBLE>
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temp = FPR264;
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}
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<CONVERT>
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:FCNVFX^fpsf^fixeddf FPR264,FPRT64 is opfam=0x0C & fpclass=1 & fpc1sub=2 & fpc1sub2=0 & sfu=0 & FPR264 & FPRT64 & fpsf & fpsfraw=1 & fixeddf & fptsgl & freg2sgl {
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local temp:8 = FPR264;
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temp = round(temp);
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FPRT64 = trunc(temp);
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}
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:FCNVFX^fpsf^fixeddf FPR264,FPRT64 is opfam=0x0C & fpclass=1 & fpc1sub=2 & fpc1sub2=0 & sfu=0 & FPR264 & FPRT64 & fpsf & fpsfraw=0 & fixeddf & fptsgl & freg2sgl {
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local temp:8 = float2float(freg2sgl); # convert single precision to double
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temp = round(temp);
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FPRT64 = trunc(temp);
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}
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:FCNVFXT^fpsf^fixeddf FPR232,FPRT32 is opfam=0x0E & fpclass=1 & fpc1sub=3 & fpc1sub2=0 & FPR232 & FPRT32 & fpsf & fixeddf {
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FPRT32 = trunc(FPR232);
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}
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:FCNVFXT^fpsf^fixeddf FPR264,FPRT64 is opfam=0x0C & fpclass=1 & fpc1sub=3 & fpc1sub2=0 & sfu=0 & FPR264 & FPRT64 & fpsf & fixeddf & fpsfraw & fptsgl & freg2sgl {
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# figure out if the value in the fp register is single or double precision
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# the register is always specified as a 64 bit register, so that doesn't tell us the size, we must use the fpsf (fp source format) format
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# The source will either be the full 64 bits (double precision) or the left half of the register (single precision)
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# source format is double precision, so 64 bits are used
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isDouble:1 = (fpsf == 1:1);
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if (isDouble) goto <DOUBLE>;
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value:4 = freg2sgl; # get single precision value from left half of 64 bit register
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goto <FLOAT2INT>;
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<DOUBLE>
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value = float2float(FPR264); # convert double precision to single
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<FLOAT2INT>
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:FCNVFXT^fpsf^fixeddf FPR264,FPRT64 is opfam=0x0C & fpclass=1 & fpc1sub=3 & fpc1sub2=0 & sfu=0 & FPR264 & FPRT64 & fpsf & fpsfraw=1 & fixeddf & fpsfraw & fptsgl & freg2sgl {
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local value:4 = float2float(FPR264); # convert double precision to single
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fptsgl = trunc(value);
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}
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}
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:FCNVFXT^fpsf^fixeddf FPR264,FPRT64 is opfam=0x0C & fpclass=1 & fpc1sub=3 & fpc1sub2=0 & sfu=0 & FPR264 & FPRT64 & fpsf & fpsfraw=0 & fixeddf & fpsfraw & fptsgl & freg2sgl {
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local value:4 = freg2sgl; # get single precision value from left half of 64 bit register
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fptsgl = trunc(value);
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}
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# Floating Point Functions
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:FCPY^fpfmt FPR232,FPRT32 is opfam=0x0E & fpclass=0 & fpsub=2 & freg1=0 & FPR232 & FPRT32 & fpfmt {
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FPRT32 = FPR232;
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}
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:FCPY^fpfmt FPR264,FPRT64 is opfam=0x0C & fpclass=0 & fpsub=2 & freg1=0 & FPR264 & FPRT64 & fpfmt & fptsgl & freg2sgl {
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if (fpfmt==0:1) goto <SGL>;
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FPRT64 = FPR264;
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goto <DONE>;
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<SGL>
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:FCPY^fpfmt FPR264,FPRT64 is opfam=0x0C & fpclass=0 & fpsub=2 & freg1=0 & FPR264 & FPRT64 & fpfmt & fpsfraw=1 & fptsgl & freg2sgl {
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fptsgl = freg2sgl;
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<DONE>
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}
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:FCPY^fpfmt FPR264,FPRT64 is opfam=0x0C & fpclass=0 & fpsub=2 & freg1=0 & FPR264 & FPRT64 & fpfmt & fpsfraw=0 & fptsgl & freg2sgl {
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FPRT64 = FPR264;
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}
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:FABS^fpfmt FPR232,FPRT32 is opfam=0x0E & fpclass=0 & fpsub=3 & freg1=0 & bit5=0 & bit8=0 & FPR232 & FPRT32 & fpfmt {
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@ -1763,52 +1749,48 @@ define pcodeop diag;
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FPRT32 = FPR132 f+ FPR232;
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}
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:FADD^fpfmt FPR264,FPR164,FPRT64 is opfam=0x0C & fpclass=3 & fpsub=0 & FPR264 & FPRT64 & FPR164 & fpfmt & freg1sgl & freg2sgl & fptsgl {
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if (fpfmt==0:1) goto <SGL>;
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FPRT64 = FPR164 f+ FPR264;
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goto <DONE>;
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<SGL>
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:FADD^fpfmt FPR264,FPR164,FPRT64 is opfam=0x0C & fpclass=3 & fpsub=0 & FPR264 & FPRT64 & FPR164 & fpfmt & fpsfraw=0 & freg1sgl & freg2sgl & fptsgl {
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fptsgl = freg1sgl f+ freg2sgl;
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<DONE>
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}
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:FADD^fpfmt FPR264,FPR164,FPRT64 is opfam=0x0C & fpclass=3 & fpsub=0 & FPR264 & FPRT64 & FPR164 & fpfmt & fpsfraw=1 & freg1sgl & freg2sgl & fptsgl {
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FPRT64 = FPR164 f+ FPR264;
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}
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:FSUB^fpfmt FPR232,FPR132,FPRT32 is opfam=0x0E & fpclass=3 & fpsub=1 & FPR232 & FPR132 & FPRT32 & fpfmt {
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FPRT32 = FPR232 f- FPR132;
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}
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:FSUB^fpfmt FPR264,FPR164,FPRT64 is opfam=0x0C & fpclass=3 & fpsub=1 & FPR264 & FPRT64 & FPR164 & fpfmt & fptsgl & freg1sgl & freg2sgl {
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if (fpfmt==0:1) goto <SGL>;
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FPRT64 = FPR264 f- FPR164;
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goto <DONE>;
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<SGL>
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:FSUB^fpfmt FPR264,FPR164,FPRT64 is opfam=0x0C & fpclass=3 & fpsub=1 & FPR264 & FPRT64 & FPR164 & fpfmt & fpsfraw=0 & fptsgl & freg1sgl & freg2sgl {
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fptsgl = freg2sgl f- freg1sgl;
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<DONE>
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}
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:FSUB^fpfmt FPR264,FPR164,FPRT64 is opfam=0x0C & fpclass=3 & fpsub=1 & FPR264 & FPRT64 & FPR164 & fpfmt & fpsfraw=1 & fptsgl & freg1sgl & freg2sgl {
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FPRT64 = FPR264 f- FPR164;
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}
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:FMPY^fpfmt FPR232,FPR132,FPRT32 is opfam=0x0E & fpclass=3 & fpsub=2 & bit8=0 & FPR232 & FPR132 & FPRT32 & fpfmt {
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FPRT32 = FPR132 f* FPR232;
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}
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:FMPY^fpfmt FPR264,FPR164,FPRT64 is opfam=0x0C & fpclass=3 & fpsub=2 & bit8=0 & FPR264 & FPRT64 & FPR164 & fpfmt & fptsgl & freg1sgl & freg2sgl {
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if (fpfmt==0:1) goto <SGL>;
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FPRT64 = FPR164 f* FPR264;
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goto <DONE>;
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<SGL>
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:FMPY^fpfmt FPR264,FPR164,FPRT64 is opfam=0x0C & fpclass=3 & fpsub=2 & bit8=0 & FPR264 & FPRT64 & FPR164 & fpfmt & fpsfraw=0 & fptsgl & freg1sgl & freg2sgl {
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fptsgl = freg1sgl f* freg2sgl;
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<DONE>
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}
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:FMPY^fpfmt FPR264,FPR164,FPRT64 is opfam=0x0C & fpclass=3 & fpsub=2 & bit8=0 & FPR264 & FPRT64 & FPR164 & fpfmt & fpsfraw=1 & fptsgl & freg1sgl & freg2sgl {
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FPRT64 = FPR164 f* FPR264;
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}
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:FDIV^fpfmt FPR232,FPR132,FPRT32 is opfam=0x0E & fpclass=3 & fpsub=3 & FPR232 & FPR132 & FPRT32 & fpfmt {
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FPRT32 = FPR232 f/ FPR132;
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}
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:FDIV^fpfmt FPR264,FPR164,FPRT64 is opfam=0x0C & fpclass=3 & fpsub=3 & FPR264 & FPRT64 & FPR164 & fpfmt & fptsgl & freg1sgl & freg2sgl {
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if (fpfmt==0:1) goto <SGL>;
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FPRT64 = FPR264 f/ FPR164;
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goto <DONE>;
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<SGL>
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:FDIV^fpfmt FPR264,FPR164,FPRT64 is opfam=0x0C & fpclass=3 & fpsub=3 & FPR264 & FPRT64 & FPR164 & fpfmt & fpsfraw=0 & fptsgl & freg1sgl & freg2sgl {
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fptsgl = freg2sgl f/ freg1sgl;
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<DONE>
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}
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:FDIV^fpfmt FPR264,FPR164,FPRT64 is opfam=0x0C & fpclass=3 & fpsub=3 & FPR264 & FPRT64 & FPR164 & fpfmt & fpsfraw=1 & fptsgl & freg1sgl & freg2sgl {
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FPRT64 = FPR264 f/ FPR164;
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}
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# 64 bit version
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@ -1844,38 +1826,40 @@ define pcodeop diag;
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# Floating Point Compare
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# 32 bit register comparison
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:FCMP^fpfmt1bit^fpcmp FPR232,FPR132 is opfam=0x0E & fpclass=2 & fpsub=0 & FPR232 & FPR132 & fpfmt1bit & fpcmp & fpcmp64 {
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result:1 = 0:1;
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:FCMP^fpfmt1bit^fpcmp FPR232,FPR132 is opfam=0x0E & fpclass=2 & fpsub=0 & FPR232 & FPR132 & fpfmt1bit & bit11=0 & fpcmp {
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local result:1 = 0:1;
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# shift the previous compareBit onto the compareQueue
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compareQueue = (compareQueue << 1);
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compareQueue = compareQueue | compareBit;
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# decide how wide a comparison we are doing
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if (fpfmt1bit == 1:1) goto <DOUBLECMP>;
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# single comparison
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result = fpcmp;
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goto <WRITERESULT>;
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# do double (full 64 bit) comp here
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<DOUBLECMP>
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compareBit = result;
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}
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:FCMP^fpfmt1bit^fpcmp64 FPR232,FPR132 is opfam=0x0E & fpclass=2 & fpsub=0 & FPR232 & FPR132 & fpfmt1bit & bit11=1 & fpcmp64 {
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local result:1 = 0:1;
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# shift the previous compareBit onto the compareQueue
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compareQueue = (compareQueue << 1);
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compareQueue = compareQueue | compareBit;
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result = fpcmp64;
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<WRITERESULT>
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compareBit = result;
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}
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# 64 bit register comparison
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:FCMP^fpfmt^fpcmp64 FPR264,FPR164 is opfam=0x0C & fpclass=2 & fpsub=0 & FPR264 & FPR164 & fpfmt & fpcmp & fpcmp64 {
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result:1 = 0:1;
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:FCMP^fpfmt^fpcmp FPR264,FPR164 is opfam=0x0C & fpclass=2 & fpsub=0 & FPR264 & FPR164 & fpfmt & fpsfraw=0 & fpcmp {
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local result:1 = 0:1;
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# shift the previous compareBit onto the compareQueue
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compareQueue = (compareQueue << 1);
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compareQueue = compareQueue | compareBit;
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# decide how wide a comparison we are doing
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if (fpfmt == 1:1) goto <DOUBLECMP>;
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# single comparison
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result = fpcmp;
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goto <WRITERESULT>;
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# do double (full 64 bit) comp here
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<DOUBLECMP>
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compareBit = result;
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}
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:FCMP^fpfmt^fpcmp64 FPR264,FPR164 is opfam=0x0C & fpclass=2 & fpsub=0 & FPR264 & FPR164 & fpfmt & fpsfraw=1 & fpcmp64 {
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local result:1 = 0:1;
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# shift the previous compareBit onto the compareQueue
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compareQueue = (compareQueue << 1);
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compareQueue = compareQueue | compareBit;
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result = fpcmp64;
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<WRITERESULT>
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compareBit = result;
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}
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