mirror of
https://github.com/NationalSecurityAgency/ghidra
synced 2024-10-12 21:23:07 +00:00
GP-2718: Resolved several open ARM instruction conflicts
This commit is contained in:
parent
376f780874
commit
850e44f7c6
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@ -5,7 +5,7 @@
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endian="little"
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size="32"
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variant="v8"
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version="1.104"
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version="1.105"
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slafile="ARM8_le.sla"
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processorspec="ARMt.pspec"
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manualindexfile="../manuals/ARM.idx"
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@ -29,7 +29,7 @@
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endian="little"
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size="32"
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variant="v8T"
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version="1.104"
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version="1.105"
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slafile="ARM8_le.sla"
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processorspec="ARMtTHUMB.pspec"
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manualindexfile="../manuals/ARM.idx"
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@ -49,7 +49,7 @@
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instructionEndian="little"
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size="32"
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variant="v8LEInstruction"
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version="1.104"
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version="1.105"
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slafile="ARM8_le.sla"
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processorspec="ARMt.pspec"
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manualindexfile="../manuals/ARM.idx"
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@ -64,7 +64,7 @@
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endian="big"
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size="32"
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variant="v8"
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version="1.104"
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version="1.105"
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slafile="ARM8_be.sla"
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processorspec="ARMt.pspec"
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manualindexfile="../manuals/ARM.idx"
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@ -87,7 +87,7 @@
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endian="big"
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size="32"
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variant="v8T"
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version="1.104"
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version="1.105"
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slafile="ARM8_be.sla"
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processorspec="ARMtTHUMB.pspec"
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manualindexfile="../manuals/ARM.idx"
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@ -104,7 +104,7 @@
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endian="little"
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size="32"
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variant="v7"
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version="1.104"
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version="1.105"
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slafile="ARM7_le.sla"
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processorspec="ARMt.pspec"
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manualindexfile="../manuals/ARM.idx"
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@ -124,7 +124,7 @@
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instructionEndian="little"
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size="32"
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variant="v7LEInstruction"
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version="1.104"
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version="1.105"
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slafile="ARM7_le.sla"
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processorspec="ARMt.pspec"
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manualindexfile="../manuals/ARM.idx"
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@ -139,7 +139,7 @@
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endian="big"
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size="32"
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variant="v7"
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version="1.104"
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version="1.105"
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slafile="ARM7_be.sla"
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processorspec="ARMt.pspec"
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manualindexfile="../manuals/ARM.idx"
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@ -157,7 +157,7 @@
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endian="little"
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size="32"
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variant="Cortex"
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version="1.104"
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version="1.105"
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slafile="ARM7_le.sla"
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processorspec="ARMCortex.pspec"
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manualindexfile="../manuals/ARM.idx"
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@ -177,7 +177,7 @@
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endian="big"
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size="32"
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variant="Cortex"
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version="1.104"
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version="1.105"
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slafile="ARM7_be.sla"
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processorspec="ARMCortex.pspec"
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manualindexfile="../manuals/ARM.idx"
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@ -196,7 +196,7 @@
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endian="little"
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size="32"
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variant="v6"
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version="1.104"
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version="1.105"
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slafile="ARM6_le.sla"
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processorspec="ARMt_v6.pspec"
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manualindexfile="../manuals/ARM.idx"
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@ -216,7 +216,7 @@
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endian="big"
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size="32"
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variant="v6"
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version="1.104"
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version="1.105"
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slafile="ARM6_be.sla"
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processorspec="ARMt_v6.pspec"
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manualindexfile="../manuals/ARM.idx"
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@ -236,7 +236,7 @@
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endian="little"
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size="32"
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variant="v5t"
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version="1.104"
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version="1.105"
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slafile="ARM5t_le.sla"
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processorspec="ARMt_v45.pspec"
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manualindexfile="../manuals/ARM.idx"
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@ -254,7 +254,7 @@
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endian="big"
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size="32"
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variant="v5t"
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version="1.104"
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version="1.105"
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slafile="ARM5t_be.sla"
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processorspec="ARMt_v45.pspec"
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manualindexfile="../manuals/ARM.idx"
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@ -272,7 +272,7 @@
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endian="little"
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size="32"
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variant="v5"
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version="1.104"
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version="1.105"
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slafile="ARM5_le.sla"
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processorspec="ARM_v45.pspec"
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manualindexfile="../manuals/ARM.idx"
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@ -304,7 +304,7 @@
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endian="little"
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size="32"
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variant="v4t"
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version="1.104"
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version="1.105"
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slafile="ARM4t_le.sla"
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processorspec="ARMt_v45.pspec"
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manualindexfile="../manuals/ARM.idx"
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@ -321,7 +321,7 @@
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endian="big"
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size="32"
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variant="v4t"
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version="1.104"
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version="1.105"
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slafile="ARM4t_be.sla"
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processorspec="ARMt_v45.pspec"
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manualindexfile="../manuals/ARM.idx"
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@ -338,7 +338,7 @@
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endian="little"
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size="32"
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variant="v4"
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version="1.104"
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version="1.105"
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slafile="ARM4_le.sla"
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processorspec="ARM_v45.pspec"
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manualindexfile="../manuals/ARM.idx"
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@ -358,7 +358,7 @@
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endian="big"
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size="32"
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variant="v4"
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version="1.104"
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version="1.105"
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slafile="ARM4_be.sla"
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processorspec="ARM_v45.pspec"
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manualindexfile="../manuals/ARM.idx"
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File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
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@ -434,7 +434,7 @@ define pcodeop PolynomialMult;
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# F6.1.59 p8000 A1 op == 1 (c0808)
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:vcvt.f32.f16 Qd,Dm
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is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b01 & c1617=0b10 & c0911=0b011 & c0607=0b00 & c0404=0 & c0808=1)
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is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b01 & c1617=0b10 & c0911=0b011 & c0607=0b00 & c0404=0 & c0808=1)
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| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b01 & thv_c1617=0b10 & thv_c0911=0b011 & thv_c0607=0b00 & thv_c0404=0 & thv_c0808=1))
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& Qd & Dm
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{
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@ -443,7 +443,7 @@ define pcodeop PolynomialMult;
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# F6.1.59 p8000 A1 op == 0 (c0808)
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:vcvt.f16.f32 Dd,Qm
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is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b01 & c1617=0b10 & c0911=0b011 & c0607=0b00 & c0404=0 & c0808=0)
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is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b01 & c1617=0b10 & c0911=0b011 & c0607=0b00 & c0404=0 & c0808=0)
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| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b01 & thv_c1617=0b10 & thv_c0911=0b011 & thv_c0607=0b00 & thv_c0404=0 & thv_c0808=0))
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& Dd & Qm
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{ Dd = float2float(Qm); }
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@ -492,14 +492,14 @@ vcvt_56_128_dt: ".u32.f32"
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# F6.1.60 p8002 A1 Q == 0 (c0606)
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:vcvt^vcvt_56_64_dt Dd,Dm
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is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c0911=0b011 & c0404=0 & c0606=0)
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is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c0911=0b011 & c0404=0 & c0606=0)
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| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b11 & thv_c0911=0b011 & thv_c0404=0 & thv_c0606=0))
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& vcvt_56_64_dt & Dd & Dm
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unimpl
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# F6.1.60 p8002 A1 Q == 1 (c0606)
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:vcvt^vcvt_56_128_dt Qd,Qm
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is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c0911=0b011 & c0404=0 & c0606=1)
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is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c0911=0b011 & c0404=0 & c0606=1)
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| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b11 & thv_c0911=0b011 & thv_c0404=0 & thv_c0606=1))
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& vcvt_56_128_dt & Qd & Qm
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unimpl
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@ -576,44 +576,84 @@ vcvt_59_fbits: "#"^fbits is TMode=0 & c1621 [ fbits = 64 - c1621; ] {
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vcvt_59_fbits: "#"^fbits is TMode=1 & thv_c1621 [ fbits = 64 - thv_c1621; ] { }
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vcvt_59_32_dt: ".f32.s32"
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is ((TMode=0 & c0808=0 & c2424=0)
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| (TMode=1 & thv_c0808=0 & thv_c2828=0))
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is ((TMode=0 & c0809=2 & c2424=0)
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| (TMode=1 & thv_c0809=2 & thv_c2828=0))
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& Dd & Dm & vcvt_59_fbits_built
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{ Dd = FixedToFP(Dm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_TIEEVEN)); }
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vcvt_59_32_dt: ".f32.u32"
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is ((TMode=0 & c0808=0 & c2424=1)
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| (TMode=1 & thv_c0808=0 & thv_c2828=1))
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is ((TMode=0 & c0809=2 & c2424=1)
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| (TMode=1 & thv_c0809=2 & thv_c2828=1))
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& Dd & Dm & vcvt_59_fbits_built
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{ Dd = FixedToFP(Dm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_TIEEVEN)); }
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vcvt_59_32_dt: ".s32.f32"
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is ((TMode=0 & c0808=1 & c2424=0)
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| (TMode=1 & thv_c0808=1 & thv_c2828=0))
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is ((TMode=0 & c0809=3 & c2424=0)
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| (TMode=1 & thv_c0809=3 & thv_c2828=0))
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& Dd & Dm & vcvt_59_fbits_built
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{ Dd = FPToFixed(Dm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_ZERO)); }
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vcvt_59_32_dt: ".u32.f32"
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is ((TMode=0 & c0808=1 & c2424=1)
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| (TMode=1 & thv_c0808=1 & thv_c2828=1))
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is ((TMode=0 & c0809=3 & c2424=1)
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| (TMode=1 & thv_c0809=3 & thv_c2828=1))
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& Dd & Dm & vcvt_59_fbits_built
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{ Dd = FPToFixed(Dm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_ZERO)); }
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vcvt_59_32_dt: ".f16.s16"
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is ((TMode=0 & c0809=0 & c2424=0)
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| (TMode=1 & thv_c0809=0 & thv_c2828=0))
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& Dd & Dm & vcvt_59_fbits_built
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{ Dd = FixedToFP(Dm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_TIEEVEN)); }
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vcvt_59_32_dt: ".f16.u16"
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is ((TMode=0 & c0809=0 & c2424=1)
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| (TMode=1 & thv_c0809=0 & thv_c2828=1))
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& Dd & Dm & vcvt_59_fbits_built
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{ Dd = FixedToFP(Dm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_TIEEVEN)); }
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vcvt_59_32_dt: ".s16.f16"
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is ((TMode=0 & c0809=1 & c2424=0)
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| (TMode=1 & thv_c0809=1 & thv_c2828=0))
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& Dd & Dm & vcvt_59_fbits_built
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{ Dd = FPToFixed(Dm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_ZERO)); }
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vcvt_59_32_dt: ".u16.f16"
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is ((TMode=0 & c0809=1 & c2424=1)
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| (TMode=1 & thv_c0809=1 & thv_c2828=1))
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& Dd & Dm & vcvt_59_fbits_built
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{ Dd = FPToFixed(Dm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_ZERO)); }
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vcvt_59_64_dt: ".f32.s32"
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is ((TMode=0 & c0808=0 & c2424=0)
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| (TMode=1 & thv_c0808=0 & thv_c2828=0))
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is ((TMode=0 & c0809=2 & c2424=0)
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| (TMode=1 & thv_c0809=2 & thv_c2828=0))
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& Qd & Qm & vcvt_59_fbits_built
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{ Qd = FixedToFP(Qm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_TIEEVEN)); }
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vcvt_59_64_dt: ".f32.u32"
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is ((TMode=0 & c0808=0 & c2424=1)
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| (TMode=1 & thv_c0808=0 & thv_c2828=1))
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is ((TMode=0 & c0809=2 & c2424=1)
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| (TMode=1 & thv_c0809=2 & thv_c2828=1))
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& Qd & Qm & vcvt_59_fbits_built
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{ Qd = FixedToFP(Qm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_TIEEVEN)); }
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vcvt_59_64_dt: ".s32.f32"
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is ((TMode=0 & c0808=1 & c2424=0)
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| (TMode=1 & thv_c0808=1 & thv_c2828=0))
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is ((TMode=0 & c0809=3 & c2424=0)
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| (TMode=1 & thv_c0809=3 & thv_c2828=0))
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& Qd & Qm & vcvt_59_fbits_built
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{ Qd = FPToFixed(Qm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_ZERO)); }
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vcvt_59_64_dt: ".u32.f32"
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is ((TMode=0 & c0808=1 & c2424=1)
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| (TMode=1 & thv_c0808=1 & thv_c2828=1))
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is ((TMode=0 & c0809=3 & c2424=1)
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| (TMode=1 & thv_c0809=3 & thv_c2828=1))
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& Qd & Qm & vcvt_59_fbits_built
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{ Qd = FPToFixed(Qm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_ZERO)); }
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vcvt_59_64_dt: ".f16.s16"
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is ((TMode=0 & c0809=0 & c2424=0)
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| (TMode=1 & thv_c0809=0 & thv_c2828=0))
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& Qd & Qm & vcvt_59_fbits_built
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{ Qd = FixedToFP(Qm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_TIEEVEN)); }
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vcvt_59_64_dt: ".f16.u16"
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is ((TMode=0 & c0809=0 & c2424=1)
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| (TMode=1 & thv_c0809=0 & thv_c2828=1))
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& Qd & Qm & vcvt_59_fbits_built
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{ Qd = FixedToFP(Qm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_TIEEVEN)); }
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vcvt_59_64_dt: ".s16.f16"
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is ((TMode=0 & c0809=1 & c2424=0)
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| (TMode=1 & thv_c0809=1 & thv_c2828=0))
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& Qd & Qm & vcvt_59_fbits_built
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{ Qd = FPToFixed(Qm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_ZERO)); }
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vcvt_59_64_dt: ".u16.f16"
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is ((TMode=0 & c0809=1 & c2424=1)
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| (TMode=1 & thv_c0809=1 & thv_c2828=1))
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& Qd & Qm & vcvt_59_fbits_built
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{ Qd = FPToFixed(Qm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_ZERO)); }
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@ -622,15 +662,15 @@ vcvt_59_64_dt: ".u32.f32"
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# F6.1.63 p8012 A1 Q = 0 (c0606)
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:vcvt^vcvt_59_32_dt Dd,Dm,vcvt_59_fbits
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is ((TMode=0 & c2831=0b1111 & c2527=0b001 & c2323=1 & c2121=1 & c0911=0b111 & c0707=0 & c0404=1 & c0606=0)
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| (TMode=1 & thv_c2931=0b111 & thv_c2327=0b11111 & thv_c2121=1 & thv_c0911=0b111 & thv_c0707=0 & thv_c0404=1 & thv_c0606=0))
|
||||
is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2527=0b001 & c2323=1 & c2121=1 & c1011=0b11 & c0707=0 & c0404=1 & c0606=0)
|
||||
| (TMode=1 & thv_c2931=0b111 & thv_c2327=0b11111 & thv_c2121=1 & thv_c1011=0b11 & thv_c0707=0 & thv_c0404=1 & thv_c0606=0))
|
||||
& vcvt_59_32_dt & vcvt_59_fbits & Dd & Dm
|
||||
unimpl
|
||||
|
||||
# F6.1.63 p8012 A1 Q = 1 (c0606)
|
||||
:vcvt^vcvt_59_64_dt Qd,Qm,vcvt_59_fbits
|
||||
is ((TMode=0 & c2831=0b1111 & c2527=0b001 & c2323=1 & c2121=1 & c0911=0b111 & c0707=0 & c0404=1 & c0606=1)
|
||||
| (TMode=1 & thv_c2931=0b111 & thv_c2327=0b11111 & thv_c2121=1 & thv_c0911=0b111 & thv_c0707=0 & thv_c0404=1 & thv_c0606=1))
|
||||
is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2527=0b001 & c2323=1 & c2121=1 & c1011=0b11 & c0707=0 & c0404=1 & c0606=1)
|
||||
| (TMode=1 & thv_c2931=0b111 & thv_c2327=0b11111 & thv_c2121=1 & thv_c1011=0b11 & thv_c0707=0 & thv_c0404=1 & thv_c0606=1))
|
||||
& vcvt_59_64_dt & vcvt_59_fbits & Qd & Qm
|
||||
unimpl
|
||||
|
||||
|
@ -771,14 +811,14 @@ vcvt_amnp_simd_128_dt: ".u32" is TMode=1 & thv_c0707=1 & thv_c0809 & vcvt_amnp_s
|
|||
|
||||
# F6.1.65,69,71,73 p8019,8028,8032,8036 A1 64-bit SIMD vector variant Q = 0 (c0606)
|
||||
:vcvt^vcvt_amnp_simd_RM^vcvt_amnp_simd_64_dt^".f32" Dd,Dm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c1011=0b00 & c0404=0 & c0606=0)
|
||||
is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c1011=0b00 & c0404=0 & c0606=0)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b11 & thv_c1011=0b00 & thv_c0404=0 & thv_c0606=0))
|
||||
& vcvt_amnp_simd_RM & vcvt_amnp_simd_64_dt & Dd & Dm
|
||||
unimpl
|
||||
|
||||
# F6.1.65,69,71,73 p8019,8028,8032,8036 A1 128-bit SIMD vector variant Q = 1(c0606)
|
||||
:vcvt^vcvt_amnp_simd_RM^vcvt_amnp_simd_128_dt^".f32" Qd,Qm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c1011=0b00 & c0404=0 & c0606=1)
|
||||
is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c1011=0b00 & c0404=0 & c0606=1)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b11 & thv_c1011=0b00 & thv_c0404=0 & thv_c0606=1))
|
||||
& vcvt_amnp_simd_RM & vcvt_amnp_simd_128_dt & Qd & Qm
|
||||
unimpl
|
||||
|
@ -810,16 +850,23 @@ vcvt_amnp_fp_d_dt: ".u32" is TMode=1 & thv_c0707=0 & thv_c1617 & vcvt_amnp_fp_RM
|
|||
vcvt_amnp_fp_d_dt: ".s32" is TMode=0 & c0707=1 & c1617 & vcvt_amnp_fp_RM & Sd & Dm { Sd = FPToFixed(Dm, 64:1, 32:1, 0:1, 0:1, vcvt_amnp_fp_RM); }
|
||||
vcvt_amnp_fp_d_dt: ".s32" is TMode=1 & thv_c0707=1 & thv_c1617 & vcvt_amnp_fp_RM & Sd & Dm { Sd = FPToFixed(Dm, 64:1, 32:1, 0:1, 0:1, vcvt_amnp_fp_RM); }
|
||||
|
||||
# F6.1.66,70,72,74 p8021,8030,8034,8038 Single-precision scalar variant size = 01 (c0809)
|
||||
:vcvt^vcvt_amnp_fp_RM^vcvt_amnp_fp_s_dt^".f16" Sd,Sm
|
||||
is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b11 & c1819=0b11 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b01)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b11 & thv_c1819=0b11 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b01))
|
||||
& vcvt_amnp_fp_RM & vcvt_amnp_fp_s_dt & Sd & Sm
|
||||
unimpl
|
||||
|
||||
# F6.1.66,70,72,74 p8021,8030,8034,8038 Single-precision scalar variant size = 11 (c0809)
|
||||
:vcvt^vcvt_amnp_fp_RM^vcvt_amnp_fp_s_dt^".f32" Sd,Sm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b11 & c1819=0b11 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b10)
|
||||
is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b11 & c1819=0b11 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b10)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b11 & thv_c1819=0b11 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b10))
|
||||
& vcvt_amnp_fp_RM & vcvt_amnp_fp_s_dt & Sd & Sm
|
||||
unimpl
|
||||
|
||||
# F6.1.66,70,72,74 p8021,8030,8034,8038 Double-precision scalar variant size = 10 (c0809)
|
||||
# F6.1.66,70,72,74 p8021,8030,8034,8038 Double-precision scalar variant size = 11 (c0809)
|
||||
:vcvt^vcvt_amnp_fp_RM^vcvt_amnp_fp_d_dt^".f64" Sd,Dm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b11 & c1819=0b11 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b11)
|
||||
is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b11 & c1819=0b11 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b11)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b11 & thv_c1819=0b11 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b11))
|
||||
& vcvt_amnp_fp_RM & vcvt_amnp_fp_d_dt & Sd & Dm
|
||||
unimpl
|
||||
|
@ -950,98 +997,98 @@ define pcodeop FPMinNum;
|
|||
|
||||
# F6.1.117 p8178 A1/T1 Q = 0 (c0606)
|
||||
:vmaxnm^".f32" Dd,Dn,Dm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b00 & c0811=0b1111 & c0404=1 & c0606=0)
|
||||
is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b00 & c0811=0b1111 & c0404=1 & c0606=0)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b00 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=0))
|
||||
& Dd & Dn & Dm
|
||||
{ Dd = FPMaxNum(Dn, Dm); }
|
||||
|
||||
# F6.1.117 p8178 A1/T1 Q = 1 (c0606)
|
||||
:vmaxnm^".f32" Qd,Qn,Qm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b00 & c0811=0b1111 & c0404=1 & c0606=1)
|
||||
is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b00 & c0811=0b1111 & c0404=1 & c0606=1)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b00 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=1))
|
||||
& Qd & Qn & Qm
|
||||
{ Qd = FPMaxNum(Qn, Qm); }
|
||||
|
||||
# F6.1.117 p8178 A1/T1 Q = 0 (c0606)
|
||||
:vmaxnm^".f16" Dd,Dn,Dm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b01 & c0811=0b1111 & c0404=1 & c0606=0)
|
||||
is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b01 & c0811=0b1111 & c0404=1 & c0606=0)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b01 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=0))
|
||||
& Dd & Dn & Dm
|
||||
{ Dd = FPMaxNum(Dn, Dm); }
|
||||
|
||||
# F6.1.117 p8178 A1/T1 Q = 1 (c0606)
|
||||
:vmaxnm^".f16" Qd,Qn,Qm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b01 & c0811=0b1111 & c0404=1 & c0606=1)
|
||||
is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b01 & c0811=0b1111 & c0404=1 & c0606=1)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b01 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=1))
|
||||
& Qd & Qn & Qm
|
||||
{ Qd = FPMaxNum(Qn, Qm); }
|
||||
|
||||
# F6.1.117 p8178 A2/T2 size = 01 (c0809)
|
||||
:vmaxnm^".f16" Sd,Sn,Sm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b01)
|
||||
is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b01)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b01))
|
||||
& Sd & Sn & Sm
|
||||
{ Sd = FPMaxNum(Sn, Sm); }
|
||||
|
||||
# F6.1.117 p8178 A2/T2 size = 10 (c0809)
|
||||
:vmaxnm^".f32" Sd,Sn,Sm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b10)
|
||||
is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b10)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b10))
|
||||
& Sd & Sn & Sm
|
||||
{ Sd = FPMaxNum(Sn, Sm); }
|
||||
|
||||
# F6.1.117 p8178 A2/T2 size = 11 (c0809)
|
||||
:vmaxnm^".f64" Dd,Dn,Dm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b11)
|
||||
is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b11)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b11))
|
||||
& Dd & Dn & Dm
|
||||
{ Dd = FPMaxNum(Dn, Dm); }
|
||||
|
||||
# F6.1.120 p8178 A1/T1 Q = 0 (c0606)
|
||||
:vminnm^".f32" Dd,Dn,Dm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b10 & c0811=0b1111 & c0404=1 & c0606=0)
|
||||
is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b10 & c0811=0b1111 & c0404=1 & c0606=0)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b10 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=0))
|
||||
& Dd & Dn & Dm
|
||||
{ Dd = FPMinNum(Dn, Dm); }
|
||||
|
||||
# F6.1.120 p8178 A1/T1 Q = 1 (c0606)
|
||||
:vminnm^".f32" Qd,Qn,Qm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b10 & c0811=0b1111 & c0404=1 & c0606=1)
|
||||
is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b10 & c0811=0b1111 & c0404=1 & c0606=1)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b10 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=1))
|
||||
& Qd & Qn & Qm
|
||||
{ Qd = FPMinNum(Qn, Qm); }
|
||||
|
||||
# F6.1.120 p8178 A1/T1 Q = 0 (c0606)
|
||||
:vminnm^".f16" Dd,Dn,Dm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b11 & c0811=0b1111 & c0404=1 & c0606=0)
|
||||
is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b11 & c0811=0b1111 & c0404=1 & c0606=0)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b11 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=0))
|
||||
& Dd & Dn & Dm
|
||||
{ Dd = FPMinNum(Dn, Dm); }
|
||||
|
||||
# F6.1.120 p8178 A1/T1 Q = 1 (c0606)
|
||||
:vminnm^".f16" Qd,Qn,Qm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b11 & c0811=0b1111 & c0404=1 & c0606=1)
|
||||
is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b11 & c0811=0b1111 & c0404=1 & c0606=1)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b11 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=1))
|
||||
& Qd & Qn & Qm
|
||||
{ Qd = FPMinNum(Qn, Qm); }
|
||||
|
||||
# F6.1.120 p8178 A2/T2 size = 01 (c0809)
|
||||
:vminnm^".f16" Sd,Sn,Sm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b01)
|
||||
is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b01)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b01))
|
||||
& Sd & Sn & Sm
|
||||
{ Sd = FPMinNum(Sn, Sm); }
|
||||
|
||||
# F6.1.120 p8178 A2/T2 size = 10 (c0809)
|
||||
:vminnm^".f32" Sd,Sn,Sm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b10)
|
||||
is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b10)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b10))
|
||||
& Sd & Sn & Sm
|
||||
{ Sd = FPMinNum(Sn, Sm); }
|
||||
|
||||
# F6.1.120 p8178 A2/T2 size = 11 (c0809)
|
||||
:vminnm^".f64" Dd,Dn,Dm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b11)
|
||||
is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b11)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b11))
|
||||
& Dd & Dn & Dm
|
||||
{ Dd = FPMinNum(Dn, Dm); }
|
||||
|
@ -1091,15 +1138,15 @@ vmull_dt: ".p64"
|
|||
|
||||
# F6.1.149 p8266 VMULL (-integer and +polynomial) op=1 (c0909) (with condition U!=1 and size!=0b11 and size!=01)
|
||||
:vmull^vmull_dt Qd,Dn,Dm
|
||||
is ((TMode=0 & c2531=0b1111001 & c2424=0 & c2323=1 & ( c2121 & c2020=0) & c1011=0b11 & c0808=0 & c0606=0 & c0404=0 & c0909=1)
|
||||
| (TMode=1 & thv_c2931=0b111 & thv_c2828=0 & thv_c2327=0b11111 & (thv_c2121 & thv_c2020=0) & thv_c1011=0b11 & thv_c0808=0 & thv_c0606=0 & thv_c0404=0 & thv_c0909=1))
|
||||
is ((TMode=0 & ARMcond=0 & c2531=0b1111001 & c2424=0 & c2323=1 & ( c2121 & c2020=0) & c1011=0b11 & c0808=0 & c0606=0 & c0404=0 & c0909=1)
|
||||
| (TMode=1 & thv_c2931=0b111 & thv_c2828=0 & thv_c2327=0b11111 & (thv_c2121 & thv_c2020=0) & thv_c1011=0b11 & thv_c0808=0 & thv_c0606=0 & thv_c0404=0 & thv_c0909=1))
|
||||
& vmull_dt & Qd & Dn & Dm
|
||||
{ Qd = PolynomialMult(Dn, Dm); }
|
||||
|
||||
# F6.1.149 p8266 VMULL (+integer and -polynomial) op=0 (c0909) (with condition size!=0b11)
|
||||
:vmull^vmull_dt Qd,Dn,Dm
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is ((TMode=0 & c2531=0b1111001 & c2424 & c2323=1 & ( c2121=0 | c2020=0) & c1011=0b11 & c0808=0 & c0606=0 & c0404=0 & c0909=0)
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||||
| (TMode=1 & thv_c2931=0b111 & thv_c2828 & thv_c2327=0b11111 & (thv_c2121=0 | thv_c2020=0) & thv_c1011=0b11 & thv_c0808=0 & thv_c0606=0 & thv_c0404=0 & thv_c0909=0))
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is ((TMode=0 & ARMcond=0 & c2531=0b1111001 & c2323=1 & ( c2121=0 | c2020=0) & c1011=0b11 & c0808=0 & c0606=0 & c0404=0 & c0909=0)
|
||||
| (TMode=1 & thv_c2931=0b111 & thv_c2327=0b11111 & (thv_c2121=0 | thv_c2020=0) & thv_c1011=0b11 & thv_c0808=0 & thv_c0606=0 & thv_c0404=0 & thv_c0909=0))
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& vmull_dt & Qd & Dn & Dm
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{ Qd = VectorMultiply(Dn, Dm); }
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@ -1201,14 +1248,14 @@ vrint_fp_RM: "p"
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# F6.1.200,202,204,206 p8398,8402,8406,8410 size = 10 (c0809)
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:vrint^vrint_fp_RM^".f32" Sd,Sm
|
||||
is ((TMode=0 & c2331=0b111111101 & c1821=0b1110 & c1011=0b10 & c0607=0b01 & c0404=0 & c0809=0b10)
|
||||
is ((TMode=0 & ARMcond=0 & c2331=0b111111101 & c1821=0b1110 & c1011=0b10 & c0607=0b01 & c0404=0 & c0809=0b10)
|
||||
| (TMode=1 & thv_c2331=0b111111101 & thv_c1821=0b1110 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c0809=0b10))
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& vrint_fp_RM & Sd & Sm
|
||||
{ Sd = FPRoundInt(Sm, 32:1, vrint_fp_RM, 0:1); }
|
||||
|
||||
# F6.1.200,202,204,206 p8398,8402,8406,8410 size = 11 (c0809)
|
||||
:vrint^vrint_fp_RM^".f64" Dd,Dm
|
||||
is ((TMode=0 & c2331=0b111111101 & c1821=0b1110 & c1011=0b10 & c0607=0b01 & c0404=0 & c0809=0b11)
|
||||
is ((TMode=0 & ARMcond=0 & c2331=0b111111101 & c1821=0b1110 & c1011=0b10 & c0607=0b01 & c0404=0 & c0809=0b11)
|
||||
| (TMode=1 & thv_c2331=0b111111101 & thv_c1821=0b1110 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c0809=0b11))
|
||||
& vrint_fp_RM & Dd & Dm
|
||||
{ Dd = FPRoundInt(Dm, 32:1, vrint_fp_RM, 0:1); }
|
||||
|
@ -1286,14 +1333,14 @@ vselcond: "vs"
|
|||
|
||||
# F6.1.223 p8447 A1/T1 size = 11 doubleprec (c0809)
|
||||
:vsel^vselcond^".f64" Dd,Dn,Dm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b11100 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b11)
|
||||
is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11100 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b11)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11100 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b11))
|
||||
& vselcond & Dn & Dd & Dm
|
||||
{ Dd = zext(vselcond != 0) * Dn + zext(vselcond == 0) * Dm; }
|
||||
|
||||
# F6.1.223 p8447 A1/T1 size = 10 singleprec (c0809)
|
||||
:vsel^vselcond".f32" Sd,Sn,Sm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b11100 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b10)
|
||||
is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11100 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b10)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11100 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b10))
|
||||
& vselcond & Sn & Sd & Sm
|
||||
{ Sd = zext(vselcond != 0) * Sn + zext(vselcond == 0) * Sm; }
|
||||
|
|
Loading…
Reference in a new issue