From 1b68950ca69551ff879ee57044767a301b9d6c63 Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Mon, 17 Oct 2022 19:32:52 +0000 Subject: [PATCH] GP-2708: Fix for vmov instruction not assembling correctly. --- .../app/plugin/assembler/sleigh/ARMAssemblyTest.java | 6 +++--- Ghidra/Processors/ARM/data/languages/ARMneon.sinc | 8 ++++---- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/Ghidra/Framework/SoftwareModeling/src/test/java/ghidra/app/plugin/assembler/sleigh/ARMAssemblyTest.java b/Ghidra/Framework/SoftwareModeling/src/test/java/ghidra/app/plugin/assembler/sleigh/ARMAssemblyTest.java index 1d53e2f94b..6e7778058f 100644 --- a/Ghidra/Framework/SoftwareModeling/src/test/java/ghidra/app/plugin/assembler/sleigh/ARMAssemblyTest.java +++ b/Ghidra/Framework/SoftwareModeling/src/test/java/ghidra/app/plugin/assembler/sleigh/ARMAssemblyTest.java @@ -111,8 +111,8 @@ public class ARMAssemblyTest extends AbstractAssemblyTest { } @Test - public void testAssemble_T_vmov_i32_d0_simdExpand_0x1_0x0_0xb1() { - assertOneCompatRestExact("vmov.i32 d0,simdExpand(0x1,0x0,0xb1)", "83:ff:31:00", THUMB, - 0x00010100, "vmov.i32 d0,simdExpand(0x1,0x0,0xb1)"); + public void testAssemble_T_vmov_i32_d0_simdExpand_0x0_0x0_0xb1() { + assertOneCompatRestExact("vmov.i32 d0,simdExpand(0x0,0x0,0xb1)", "83:ff:11:00", THUMB, + 0x00010100, "vmov.i32 d0,simdExpand(0x0,0x0,0xb1)"); } } diff --git a/Ghidra/Processors/ARM/data/languages/ARMneon.sinc b/Ghidra/Processors/ARM/data/languages/ARMneon.sinc index 975155ea5d..d61955dc93 100644 --- a/Ghidra/Processors/ARM/data/languages/ARMneon.sinc +++ b/Ghidra/Processors/ARM/data/languages/ARMneon.sinc @@ -3980,14 +3980,14 @@ vmlDm: thv_Dm_4^"["^thv_M5^"]" is TMode=1 & thv_c2021=2 & thv_Dm_4 & thv_M5 Qd = VectorMultiplySubtract(Dn,vmlDm,esize2021,udt); } -:vmov.^simdExpImmDT Dd,simdExpImm_8 is (( $(AMODE) & cond=15 & c2527=1 & c2323=1 & c1921=0 & c0707=0 & Q6=0 & c0404=1 ) | - ( $(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c0707=0 & thv_Q6=0 & thv_c0404=1 )) & Dd & simdExpImmDT & simdExpImm_8 +:vmov.^simdExpImmDT Dd,simdExpImm_8 is (( $(AMODE) & cond=15 & c2527=1 & c2323=1 & c1921=0 & c0707=0 & Q6=0 & c0405=1 ) | + ( $(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c0707=0 & thv_Q6=0 & thv_c0405=1 )) & Dd & simdExpImmDT & simdExpImm_8 { Dd = simdExpImm_8; } -:vmov.^simdExpImmDT Qd,simdExpImm_16 is (( $(AMODE) & cond=15 & c2527=1 & c2323=1 & c1921=0 & c0707=0 & Q6=1 & c0404=1 ) | - ( $(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c0707=0 & thv_Q6=1 & thv_c0404=1 )) & Qd & simdExpImmDT & simdExpImm_16 +:vmov.^simdExpImmDT Qd,simdExpImm_16 is (( $(AMODE) & cond=15 & c2527=1 & c2323=1 & c1921=0 & c0707=0 & Q6=1 & c0405=1 ) | + ( $(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c0707=0 & thv_Q6=1 & thv_c0405=1 )) & Qd & simdExpImmDT & simdExpImm_16 { Qd = simdExpImm_16; }